coreboot-gerrit December 2022

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[M] Change in coreboot[master]: util/crossgcc: Update GCC from 11.2 to 12.2
by Felix Singer (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Martin L Roth. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66922 ) Change subject: util/crossgcc: Update GCC from 11.2 to 12.2 ...................................................................... Patch Set 10: (1 comment) Patchset: PS10: > maybe "coreboot/src/lib/gnat/" needs an update ? Are these just copies from the GNAT source? Yes, maybe. I'm really not into Ada/GNAT, so I can't help much there. -- To view, visit https://review.coreboot.org/c/coreboot/+/66922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia15e48847c6aea4f3188588b5092250568f16a09 Gerrit-Change-Number: 66922 Gerrit-PatchSet: 10 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Thu, 01 Dec 2022 10:51:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: util/crossgcc: Update GCC from 11.2 to 12.2
by Elyes Haouas (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Felix Singer, Martin L Roth. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66922 ) Change subject: util/crossgcc: Update GCC from 11.2 to 12.2 ...................................................................... Patch Set 10: (1 comment) Patchset: PS10: > GCC 12 has some Ada issues and there are lots of warnings which are counted as errors. […] maybe "coreboot/src/lib/gnat/" needs an update ? -- To view, visit https://review.coreboot.org/c/coreboot/+/66922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia15e48847c6aea4f3188588b5092250568f16a09 Gerrit-Change-Number: 66922 Gerrit-PatchSet: 10 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Thu, 01 Dec 2022 10:40:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: util/crossgcc: Update GCC from 11.2 to 12.2
by Felix Singer (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Martin L Roth. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66922 ) Change subject: util/crossgcc: Update GCC from 11.2 to 12.2 ...................................................................... Patch Set 10: (1 comment) Patchset: PS10: > Anything blocking this? gcc 12 adds the -Oz option over -Os (just like clang) which reduces binary s […] GCC 12 has some Ada issues and there are lots of warnings which are counted as errors. I guess we can just disable these, but I need to do a deeper look. I will try to fix the binutils issue today. -- To view, visit https://review.coreboot.org/c/coreboot/+/66922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia15e48847c6aea4f3188588b5092250568f16a09 Gerrit-Change-Number: 66922 Gerrit-PatchSet: 10 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Thu, 01 Dec 2022 10:36:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: util/crossgcc: Update GCC from 11.2 to 12.2
by Arthur Heymans (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Felix Singer, Martin L Roth. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66922 ) Change subject: util/crossgcc: Update GCC from 11.2 to 12.2 ...................................................................... Patch Set 10: (1 comment) Patchset: PS10: Anything blocking this? gcc 12 adds the -Oz option over -Os (just like clang) which reduces binary size even more :-) So I would like this in. -- To view, visit https://review.coreboot.org/c/coreboot/+/66922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia15e48847c6aea4f3188588b5092250568f16a09 Gerrit-Change-Number: 66922 Gerrit-PatchSet: 10 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Thu, 01 Dec 2022 10:32:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/alderlake: Enable the runtime debug capability
by Subrata Banik (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Paul Menzel, Krishna P Bhat D. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64434 ) Change subject: soc/intel/alderlake: Enable the runtime debug capability ...................................................................... Patch Set 8: -Code-Review -- To view, visit https://review.coreboot.org/c/coreboot/+/64434 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11d74a16bfc07ae12247f3cd1846c25268b69cc3 Gerrit-Change-Number: 64434 Gerrit-PatchSet: 8 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Thu, 01 Dec 2022 10:30:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/common: Check PMC debug trace enable request
by Subrata Banik (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Paul Menzel, Tim Wawrzynczak. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64433 ) Change subject: soc/intel/common: Check PMC debug trace enable request ...................................................................... Patch Set 8: -Code-Review -- To view, visit https://review.coreboot.org/c/coreboot/+/64433 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9718226e38233adf3de2f0df686c41caf220d246 Gerrit-Change-Number: 64433 Gerrit-PatchSet: 8 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Maulik Vaghela <maulikvaghela(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Comment-Date: Thu, 01 Dec 2022 10:30:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/alderlake: Update cpu and pch tracehub modes
by Subrata Banik (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Maulik Vaghela, Paul Menzel. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64438 ) Change subject: soc/intel/alderlake: Update cpu and pch tracehub modes ...................................................................... Patch Set 8: -Code-Review -- To view, visit https://review.coreboot.org/c/coreboot/+/64438 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I088b5d1f5569aacbf79834b44372702f8d3a189f Gerrit-Change-Number: 64438 Gerrit-PatchSet: 8 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Maulik Vaghela <maulikvaghela(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik Vaghela <maulikvaghela(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 01 Dec 2022 10:30:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/alderlake: Add support to enable PMC firmware trace
by Subrata Banik (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Maulik Vaghela, Paul Menzel, Tim Wawrzynczak. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64436 ) Change subject: soc/intel/alderlake: Add support to enable PMC firmware trace ...................................................................... Patch Set 8: -Code-Review -- To view, visit https://review.coreboot.org/c/coreboot/+/64436 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I146bff95945578b437f982ae033d655b3f92f7b4 Gerrit-Change-Number: 64436 Gerrit-PatchSet: 8 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Maulik Vaghela <maulikvaghela(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik Vaghela <maulikvaghela(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Comment-Date: Thu, 01 Dec 2022 10:29:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: nb/intel/x4x: Hook up PCI domain and CPU bus ops to devicetree
by Arthur Heymans (Code Review) 01 Dec '22

01 Dec '22

Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69295 ) ( 17 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: nb/intel/x4x: Hook up PCI domain and CPU bus ops to devicetree ...................................................................... nb/intel/x4x: Hook up PCI domain and CPU bus ops to devicetree Change-Id: I0a7b3167392c152da6459dfc202ef11b2e61400a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69295 Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/acer/g43t-am3/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb M src/mainboard/asus/p5qc/variants/p5q/devicetree.cb M src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb M src/mainboard/asus/p5qc/variants/p5q_se/devicetree.cb M src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb M src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb M src/mainboard/asus/p5ql-em/devicetree.cb M src/mainboard/asus/p5qpl-am/devicetree.cb M src/mainboard/foxconn/g41s-k/devicetree.cb M src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb M src/mainboard/intel/dg41wv/devicetree.cb M src/mainboard/intel/dg43gt/devicetree.cb M src/mainboard/lenovo/thinkcentre_a58/devicetree.cb M src/northbridge/intel/x4x/northbridge.c 19 files changed, 87 insertions(+), 48 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved diff --git a/src/mainboard/acer/g43t-am3/devicetree.cb b/src/mainboard/acer/g43t-am3/devicetree.cb index a713f34..713ac40 100644 --- a/src/mainboard/acer/g43t-am3/devicetree.cb +++ b/src/mainboard/acer/g43t-am3/devicetree.cb @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on # APIC cluster + device cpu_cluster 0 on + ops x4x_cpu_bus_ops # APIC cluster chip cpu/intel/socket_LGA775 device lapic 0 on end end @@ -9,7 +10,8 @@ device lapic 0xacac off end end end - device domain 0 on # PCI domain + device domain 0 on + ops x4x_pci_domain_ops # PCI domain subsystemid 0x8086 0x0028 inherit device pci 0.0 on end # Host Bridge device pci 2.0 on end # Integrated graphics controller diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb index ff050306..5d10628 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on # APIC cluster + device cpu_cluster 0 on + ops x4x_cpu_bus_ops # APIC cluster chip cpu/intel/socket_LGA775 device lapic 0 on end end @@ -9,7 +10,8 @@ device lapic 0xACAC off end end end - device domain 0 on # PCI domain + device domain 0 on + ops x4x_pci_domain_ops # PCI domain subsystemid 0x1458 0x5000 inherit device pci 0.0 on # Host Bridge subsystemid 0x1849 0x2e30 diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb index 89e6ebb..d0759e2 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on # APIC cluster + device cpu_cluster 0 on + ops x4x_cpu_bus_ops # APIC cluster chip cpu/intel/socket_LGA775 device lapic 0 on end end @@ -9,7 +10,8 @@ device lapic 0xACAC off end end end - device domain 0 on # PCI domain + device domain 0 on + ops x4x_pci_domain_ops # PCI domain subsystemid 0x1458 0x5000 inherit device pci 0.0 on # Host Bridge subsystemid 0x1849 0x2e30 diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb index c3c6b1b..818ceaa 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on # APIC cluster + device cpu_cluster 0 on + ops x4x_cpu_bus_ops # APIC cluster chip cpu/intel/socket_LGA775 device lapic 0 on end end @@ -9,7 +10,8 @@ device lapic 0xACAC off end end end - device domain 0 on # PCI domain + device domain 0 on + ops x4x_pci_domain_ops # PCI domain subsystemid 0x1458 0x5000 inherit device pci 0.0 on # Host Bridge subsystemid 0x1849 0x2e30 diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb index 9d22761..9f4142b 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on # APIC cluster + device cpu_cluster 0 on + ops x4x_cpu_bus_ops # APIC cluster chip cpu/intel/socket_LGA775 device lapic 0 on end end @@ -9,7 +10,8 @@ device lapic 0xACAC off end end end - device domain 0 on # PCI domain + device domain 0 on + ops x4x_pci_domain_ops # PCI domain subsystemid 0x1458 0x5000 inherit device pci 0.0 on # Host Bridge subsystemid 0x1849 0x2e30 diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb index 8693c01..e0df76b 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on # APIC cluster + device cpu_cluster 0 on + ops x4x_cpu_bus_ops # APIC cluster chip cpu/intel/socket_LGA775 device lapic 0 on end end @@ -9,7 +10,8 @@ device lapic 0xACAC off end end end - device domain 0 on # PCI domain + device domain 0 on + ops x4x_pci_domain_ops # PCI domain subsystemid 0x1458 0x5000 inherit device pci 0.0 on # Host Bridge subsystemid 0x1849 0x2e30 diff --git a/src/mainboard/asus/p5qc/variants/p5q/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5q/devicetree.cb index 9057ed7..c452672 100644 --- a/src/mainboard/asus/p5qc/variants/p5q/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5q/devicetree.cb @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on # APIC cluster + device cpu_cluster 0 on + ops x4x_cpu_bus_ops # APIC cluster chip cpu/intel/socket_LGA775 device lapic 0 on end end @@ -9,7 +10,8 @@ device lapic 0xACAC off end end end - device domain 0 on # PCI domain + device domain 0 on + ops x4x_pci_domain_ops # PCI domain device pci 0.0 on end # Host Bridge device pci 1.0 on end # PEG device pci 6.0 off end # PEG 2 diff --git a/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb index bc9dff6..b0452d4 100644 --- a/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on # APIC cluster + device cpu_cluster 0 on + ops x4x_cpu_bus_ops # APIC cluster chip cpu/intel/socket_LGA775 device lapic 0 on end end @@ -9,7 +10,8 @@ device lapic 0xacac off end end end - device domain 0 on # PCI domain + device domain 0 on + ops x4x_pci_domain_ops # PCI domain device pci 0.0 on end # Host Bridge device pci 1.0 on end # PEG device pci 2.0 off end # Integrated graphics controller diff --git a/src/mainboard/asus/p5qc/variants/p5q_se/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5q_se/devicetree.cb index 01de13f..8390bc0 100644 --- a/src/mainboard/asus/p5qc/variants/p5q_se/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5q_se/devicetree.cb @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on # APIC cluster + device cpu_cluster 0 on + ops x4x_cpu_bus_ops # APIC cluster chip cpu/intel/socket_LGA775 device lapic 0 on end end @@ -9,7 +10,8 @@ device lapic 0xacac off end end end - device domain 0 on # PCI domain + device domain 0 on + ops x4x_pci_domain_ops # PCI domain device pci 0.0 on end # Host Bridge device pci 1.0 on end # PEG device pci 2.0 off end # Integrated graphics controller diff --git a/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb index 1b50903..70e82e8 100644 --- a/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on # APIC cluster + device cpu_cluster 0 on + ops x4x_cpu_bus_ops # APIC cluster chip cpu/intel/socket_LGA775 device lapic 0 on end end @@ -9,7 +10,8 @@ device lapic 0xacac off end end end - device domain 0 on # PCI domain + device domain 0 on + ops x4x_pci_domain_ops # PCI domain device pci 0.0 on end # Host Bridge device pci 1.0 on end # PEG device pci 2.0 off end # Integrated graphics controller diff --git a/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb index 01de13f..8390bc0 100644 --- a/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on # APIC cluster + device cpu_cluster 0 on + ops x4x_cpu_bus_ops # APIC cluster chip cpu/intel/socket_LGA775 device lapic 0 on end end @@ -9,7 +10,8 @@ device lapic 0xacac off end end end - device domain 0 on # PCI domain + device domain 0 on + ops x4x_pci_domain_ops # PCI domain device pci 0.0 on end # Host Bridge device pci 1.0 on end # PEG device pci 2.0 off end # Integrated graphics controller diff --git a/src/mainboard/asus/p5ql-em/devicetree.cb b/src/mainboard/asus/p5ql-em/devicetree.cb index 242ea5a..a839b9d 100644 --- a/src/mainboard/asus/p5ql-em/devicetree.cb +++ b/src/mainboard/asus/p5ql-em/devicetree.cb @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on # APIC cluster + device cpu_cluster 0 on + ops x4x_cpu_bus_ops # APIC cluster chip cpu/intel/socket_LGA775 device lapic 0 on end end @@ -9,7 +10,8 @@ device lapic 0xacac off end end end - device domain 0 on # PCI domain + device domain 0 on + ops x4x_pci_domain_ops # PCI domain device pci 0.0 on # Host Bridge subsystemid 0x1043 0x8336 end diff --git a/src/mainboard/asus/p5qpl-am/devicetree.cb b/src/mainboard/asus/p5qpl-am/devicetree.cb index 1cbee74..82b1c61 100644 --- a/src/mainboard/asus/p5qpl-am/devicetree.cb +++ b/src/mainboard/asus/p5qpl-am/devicetree.cb @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on # APIC cluster + device cpu_cluster 0 on + ops x4x_cpu_bus_ops # APIC cluster chip cpu/intel/socket_LGA775 device lapic 0 on end end @@ -9,7 +10,8 @@ device lapic 0xacac off end end end - device domain 0 on # PCI domain + device domain 0 on + ops x4x_pci_domain_ops # PCI domain device pci 0.0 on end # Host Bridge device pci 1.0 on end # PEG device pci 2.0 on end # Integrated graphics controller diff --git a/src/mainboard/foxconn/g41s-k/devicetree.cb b/src/mainboard/foxconn/g41s-k/devicetree.cb index 9bde4b2..578f13d 100644 --- a/src/mainboard/foxconn/g41s-k/devicetree.cb +++ b/src/mainboard/foxconn/g41s-k/devicetree.cb @@ -1,7 +1,8 @@ ## SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on # APIC cluster + device cpu_cluster 0 on + ops x4x_cpu_bus_ops # APIC cluster chip cpu/intel/socket_LGA775 device lapic 0 on end end @@ -9,7 +10,8 @@ device lapic 0xACAC off end end end - device domain 0 on # PCI domain + device domain 0 on + ops x4x_pci_domain_ops # PCI domain device pci 0.0 on end # Host Bridge device pci 1.0 on end # PEG device pci 2.0 on end # Integrated graphics controller diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb index 6328bc6..d216863 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on # APIC cluster + device cpu_cluster 0 on + ops x4x_cpu_bus_ops # APIC cluster chip cpu/intel/socket_LGA775 device lapic 0 on end end @@ -9,7 +10,8 @@ device lapic 0xACAC off end end end - device domain 0 on # PCI domain + device domain 0 on + ops x4x_pci_domain_ops # PCI domain subsystemid 0x1458 0x5000 inherit device pci 0.0 on # Host Bridge subsystemid 0x1458 0x5000 diff --git a/src/mainboard/intel/dg41wv/devicetree.cb b/src/mainboard/intel/dg41wv/devicetree.cb index 5f945c1..9e5c136 100644 --- a/src/mainboard/intel/dg41wv/devicetree.cb +++ b/src/mainboard/intel/dg41wv/devicetree.cb @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on # APIC cluster + device cpu_cluster 0 on + ops x4x_cpu_bus_ops # APIC cluster chip cpu/intel/socket_LGA775 device lapic 0 on end end @@ -9,7 +10,8 @@ device lapic 0xACAC off end end end - device domain 0 on # PCI domain + device domain 0 on + ops x4x_pci_domain_ops # PCI domain subsystemid 0x1458 0x5000 inherit device pci 0.0 on # Host Bridge subsystemid 0x8086 0x5756 diff --git a/src/mainboard/intel/dg43gt/devicetree.cb b/src/mainboard/intel/dg43gt/devicetree.cb index bb2456f..5e2eb9d 100644 --- a/src/mainboard/intel/dg43gt/devicetree.cb +++ b/src/mainboard/intel/dg43gt/devicetree.cb @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on # APIC cluster + device cpu_cluster 0 on + ops x4x_cpu_bus_ops # APIC cluster chip cpu/intel/socket_LGA775 device lapic 0 on end end @@ -9,7 +10,8 @@ device lapic 0xacac off end end end - device domain 0 on # PCI domain + device domain 0 on + ops x4x_pci_domain_ops # PCI domain subsystemid 0x8086 0x0028 inherit device pci 0.0 on end # Host Bridge device pci 2.0 on end # Integrated graphics controller diff --git a/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb b/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb index e5d10d7..a4b9ac8 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb +++ b/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on # APIC cluster + device cpu_cluster 0 on + ops x4x_cpu_bus_ops # APIC cluster chip cpu/intel/socket_LGA775 device lapic 0 on end end @@ -9,7 +10,8 @@ device lapic 0xACAC off end end end - device domain 0 on # PCI domain + device domain 0 on + ops x4x_pci_domain_ops # PCI domain subsystemid 0x17aa 0x304f inherit device pci 0.0 on end # Host Bridge device pci 1.0 on end # PEG diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index ac276b6..da046d1 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -144,7 +144,7 @@ pci_write_config8(dev, D0F0_SMRAM, smram); } -static struct device_operations pci_domain_ops = { +struct device_operations x4x_pci_domain_ops = { .read_resources = mch_domain_read_resources, .set_resources = mch_domain_set_resources, .init = mch_domain_init, @@ -154,21 +154,12 @@ .acpi_name = northbridge_acpi_name, }; -static struct device_operations cpu_bus_ops = { +struct device_operations x4x_cpu_bus_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, .init = mp_cpu_bus_init, }; -static void enable_dev(struct device *dev) -{ - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) - dev->ops = &pci_domain_ops; - else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) - dev->ops = &cpu_bus_ops; -} - static void hide_pci_fn(const int dev_bit_base, const struct device *dev) { if (!dev || dev->enabled) @@ -201,6 +192,5 @@ struct chip_operations northbridge_intel_x4x_ops = { CHIP_NAME("Intel 4-Series Northbridge") - .enable_dev = enable_dev, .init = x4x_init, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/69295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a7b3167392c152da6459dfc202ef11b2e61400a Gerrit-Change-Number: 69295 Gerrit-PatchSet: 20 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: nb/intel/i945: Hook up PCI domain and CPU bus ops to devicetree
by Arthur Heymans (Code Review) 01 Dec '22

01 Dec '22

Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69294 ) ( 17 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: nb/intel/i945: Hook up PCI domain and CPU bus ops to devicetree ...................................................................... nb/intel/i945: Hook up PCI domain and CPU bus ops to devicetree Change-Id: I4f30f5275d38c3eecf54d008b3edbf68071ab10d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69294 Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/apple/macbook21/devicetree.cb M src/mainboard/asus/p5gc-mx/devicetree.cb M src/mainboard/getac/p470/devicetree.cb M src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb M src/mainboard/ibase/mb899/devicetree.cb M src/mainboard/intel/d945gclf/devicetree.cb M src/mainboard/kontron/986lcd-m/devicetree.cb M src/mainboard/lenovo/t60/devicetree.cb M src/mainboard/lenovo/x60/devicetree.cb M src/mainboard/roda/rk886ex/devicetree.cb M src/northbridge/intel/i945/northbridge.c 11 files changed, 35 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index bcce778..358fcf4 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -14,6 +14,7 @@ register "gpu_panel_power_cycle_delay" = "2" device cpu_cluster 0 on + ops i945_cpu_bus_ops chip cpu/intel/socket_m device lapic 0 on end end @@ -22,6 +23,7 @@ register "pci_mmio_size" = "768" device domain 0 on + ops i945_pci_domain_ops device pci 00.0 on # Host bridge subsystemid 0x8086 0x7270 end diff --git a/src/mainboard/asus/p5gc-mx/devicetree.cb b/src/mainboard/asus/p5gc-mx/devicetree.cb index 172f65f..ad9b961 100644 --- a/src/mainboard/asus/p5gc-mx/devicetree.cb +++ b/src/mainboard/asus/p5gc-mx/devicetree.cb @@ -3,6 +3,7 @@ chip northbridge/intel/i945 device cpu_cluster 0 on + ops i945_cpu_bus_ops chip cpu/intel/socket_LGA775 device lapic 0 on end end @@ -12,6 +13,7 @@ end device domain 0 on + ops i945_pci_domain_ops device pci 00.0 on # host bridge subsystemid 0x1458 0x5000 end diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb index 9a91b81..345bbd8 100644 --- a/src/mainboard/getac/p470/devicetree.cb +++ b/src/mainboard/getac/p470/devicetree.cb @@ -6,6 +6,7 @@ register "gfx.did" = "{ 0x80000100, 0x80000410, 0x80000320, 0x80000410, 0x00000005 }" device cpu_cluster 0 on + ops i945_cpu_bus_ops chip cpu/intel/socket_m device lapic 0 on end end @@ -14,6 +15,7 @@ register "pci_mmio_size" = "768" device domain 0 on + ops i945_pci_domain_ops device pci 00.0 on end # host bridge device pci 01.0 off end # i945 PCIe root port device pci 02.0 on end # vga controller diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb index c0f198f..28af26f 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb @@ -3,6 +3,7 @@ chip northbridge/intel/i945 device cpu_cluster 0 on + ops i945_cpu_bus_ops chip cpu/intel/socket_LGA775 device lapic 0 on end end @@ -14,6 +15,7 @@ register "pci_mmio_size" = "768" device domain 0 on + ops i945_pci_domain_ops device pci 00.0 on # host bridge subsystemid 0x1458 0x5000 end diff --git a/src/mainboard/ibase/mb899/devicetree.cb b/src/mainboard/ibase/mb899/devicetree.cb index 12104e4..1b59fcc 100644 --- a/src/mainboard/ibase/mb899/devicetree.cb +++ b/src/mainboard/ibase/mb899/devicetree.cb @@ -3,6 +3,7 @@ register "gfx" = "GMA_STATIC_DISPLAYS(0)" device cpu_cluster 0 on + ops i945_cpu_bus_ops chip cpu/intel/socket_m device lapic 0 on end end @@ -11,6 +12,7 @@ register "pci_mmio_size" = "768" device domain 0 on + ops i945_pci_domain_ops device pci 00.0 on end # host bridge device pci 01.0 off end # i945 PCIe root port device pci 02.0 on end # vga controller diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb index 669122f..0238e04 100644 --- a/src/mainboard/intel/d945gclf/devicetree.cb +++ b/src/mainboard/intel/d945gclf/devicetree.cb @@ -3,6 +3,7 @@ chip northbridge/intel/i945 device cpu_cluster 0 on + ops i945_cpu_bus_ops chip cpu/intel/socket_441 device lapic 0 on end end @@ -11,6 +12,7 @@ register "pci_mmio_size" = "768" device domain 0 on + ops i945_pci_domain_ops subsystemid 0x8086 0x464c inherit device pci 00.0 on end # host bridge device pci 01.0 off end # i945 PCIe root port diff --git a/src/mainboard/kontron/986lcd-m/devicetree.cb b/src/mainboard/kontron/986lcd-m/devicetree.cb index bd0db6d..90da56c 100644 --- a/src/mainboard/kontron/986lcd-m/devicetree.cb +++ b/src/mainboard/kontron/986lcd-m/devicetree.cb @@ -3,6 +3,7 @@ register "gfx" = "GMA_STATIC_DISPLAYS(0)" device cpu_cluster 0 on + ops i945_cpu_bus_ops chip cpu/intel/socket_m device lapic 0 on end end @@ -11,6 +12,7 @@ register "pci_mmio_size" = "768" device domain 0 on + ops i945_pci_domain_ops device pci 00.0 on end # host bridge device pci 01.0 off end # i945 PCIe x16 bridge device pci 02.0 on end # GMA950 iGPU + VGA diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 7709a87..c77af6b 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -14,6 +14,7 @@ register "gpu_panel_power_cycle_delay" = "2" device cpu_cluster 0 on + ops i945_cpu_bus_ops chip cpu/intel/socket_m device lapic 0 on end end @@ -22,6 +23,7 @@ register "pci_mmio_size" = "768" device domain 0 on + ops i945_pci_domain_ops device pci 00.0 on # Host bridge subsystemid 0x17aa 0x2015 end diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 8620062..d56ec51 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -14,6 +14,7 @@ register "gpu_panel_power_cycle_delay" = "2" device cpu_cluster 0 on + ops i945_cpu_bus_ops chip cpu/intel/socket_m device lapic 0 on end end @@ -22,6 +23,7 @@ register "pci_mmio_size" = "768" device domain 0 on + ops i945_pci_domain_ops device pci 00.0 on # Host bridge subsystemid 0x17aa 0x2017 end diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb index 6b9dbd9..4023af80 100644 --- a/src/mainboard/roda/rk886ex/devicetree.cb +++ b/src/mainboard/roda/rk886ex/devicetree.cb @@ -5,6 +5,7 @@ register "gfx" = "GMA_STATIC_DISPLAYS(0)" device cpu_cluster 0 on + ops i945_cpu_bus_ops chip cpu/intel/socket_m device lapic 0 on end end @@ -13,6 +14,7 @@ register "pci_mmio_size" = "768" device domain 0 on + ops i945_pci_domain_ops subsystemid 0x4352 0x6886 inherit device pci 00.0 on end # host bridge # auto detection: diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 3c5603c..c175576 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -122,7 +122,7 @@ pci_write_config8(dev, SMRAM, smram); } -static struct device_operations pci_domain_ops = { +struct device_operations i945_pci_domain_ops = { .read_resources = mch_domain_read_resources, .set_resources = mch_domain_set_resources, .scan_bus = pci_domain_scan_bus, @@ -155,22 +155,12 @@ .devices = pci_device_ids, }; -static struct device_operations cpu_bus_ops = { +struct device_operations i945_cpu_bus_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, .init = mp_cpu_bus_init, }; -static void enable_dev(struct device *dev) -{ - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) - dev->ops = &pci_domain_ops; - else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) - dev->ops = &cpu_bus_ops; -} - struct chip_operations northbridge_intel_i945_ops = { CHIP_NAME("Intel i945 Northbridge") - .enable_dev = enable_dev, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/69294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f30f5275d38c3eecf54d008b3edbf68071ab10d Gerrit-Change-Number: 69294 Gerrit-PatchSet: 20 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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