coreboot-gerrit December 2022

coreboot-gerrit@coreboot.org

1 participants
6828 discussions

[L] Change in coreboot[master]: soc/intel/common, alderlake: provide a list of D-states to enter LPM
by Eran Mitrani (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal. Eran Mitrani has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70166 ) Change subject: soc/intel/common, alderlake: provide a list of D-states to enter LPM ...................................................................... Patch Set 8: (6 comments) File src/soc/intel/alderlake/acpi.c: https://review.coreboot.org/c/coreboot/+/70166/comment/e26e9a23_66ae2402 PS7, Line 168: struct min_sleep_state min_pci_sleep_states[] = { > how about marking this structure as static ? Done https://review.coreboot.org/c/coreboot/+/70166/comment/1bfecb0e_9d8e036c PS7, Line 233: soc_lpi_get_constraints > can't we call `acpi_generate_lpi_constraint_table()` directly from pep. […] Done File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/70166/comment/6ad4ad05_e18ad8ca PS7, Line 30: = 0 > same Done https://review.coreboot.org/c/coreboot/+/70166/comment/8d909a54_4f8226de PS7, Line 31: }; > please one blank line Done https://review.coreboot.org/c/coreboot/+/70166/comment/2476dd7b_585870da PS7, Line 455: ar > `ar` is like array ? […] Done https://review.coreboot.org/c/coreboot/+/70166/comment/37720101_c2dcf91c PS7, Line 495: return; > I think you need to create a default entry here like what `soc_lpi_get_constraints()` does in `src/s […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/70166 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45eded3868a4987cb5eb0676c50378ac52ec3752 Gerrit-Change-Number: 70166 Gerrit-PatchSet: 8 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Fri, 02 Dec 2022 19:32:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: mb/google/rex: Implement S0ix hooks aka `MS0X` method
by Subrata Banik (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Utkarsh H Patel, Kapil Porwal, Ivy Jian, Sridhar Siricilla, Eric Lai, Sukumar Ghorai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70196 ) Change subject: mb/google/rex: Implement S0ix hooks aka `MS0X` method ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: > I do see slp_s0 toggle 1st S0is after boot. may stay high hence sub-sequent s0ix cycle does not toggle. need to prob the signals. > > Success log (1st S0ix): > [139.985900 ACPI kbli[139.988800 KB Clear Buffer] > 22-12-02 10:59:18.752 [140.223000 HI: power state 16 = S0S0ix, in 0x00df > 22-12-02 10:59:18.990 C 0x00a9] > 22-12-02 10:59:18.991 [140.288100 lid-accel: 0: init failed: 1] > 22-12-02 10:59:19.056 [140.290I: power state 5 = S0ix, in 0x00df > 22-12-02 10:59:19.061 700 tcs3400_init failed reading ID reg 0x92, ret=1] > 22-12-02 10:59:19.067 [140.292500 PD:S0->S3] > This is good info. Can you please check the GPP_H14 PAD configuration (Tx state) when you are seeing S0ix entry at the EC console. And after exiting the S0ix, please cross check the same GPP_H14 PAD. Just want to make sure that the pad is getting reset/set based on the S0ix entry and exit. -- To view, visit https://review.coreboot.org/c/coreboot/+/70196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6b5e066f228ea5dc79ae14dd803fc283fd248ce Gerrit-Change-Number: 70196 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Utkarsh H Patel <utkarsh.h.patel(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-CC: Utkarsh H Patel <utkarsh.h.patel(a)intel.corp-partner.google.com> Gerrit-Attention: Utkarsh H Patel <utkarsh.h.patel(a)intel.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Utkarsh H Patel <utkarsh.h.patel(a)intel.com> Gerrit-Attention: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Comment-Date: Fri, 02 Dec 2022 19:26:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: mb/google/rex: Implement S0ix hooks aka `MS0X` method
by Sukumar Ghorai (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Utkarsh H Patel, Subrata Banik, Kapil Porwal, Ivy Jian, Sridhar Siricilla, Eric Lai. Sukumar Ghorai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70196 ) Change subject: mb/google/rex: Implement S0ix hooks aka `MS0X` method ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: I do see slp_s0 toggle 1st S0is after boot. may stay high hence sub-sequent s0ix cycle does not toggle. need to prob the signals. Success log (1st S0ix): [139.985900 ACPI kbli[139.988800 KB Clear Buffer] 22-12-02 10:59:18.752 [140.223000 HI: power state 16 = S0S0ix, in 0x00df 22-12-02 10:59:18.990 C 0x00a9] 22-12-02 10:59:18.991 [140.288100 lid-accel: 0: init failed: 1] 22-12-02 10:59:19.056 [140.290I: power state 5 = S0ix, in 0x00df 22-12-02 10:59:19.061 700 tcs3400_init failed reading ID reg 0x92, ret=1] 22-12-02 10:59:19.067 [140.292500 PD:S0->S3] -- To view, visit https://review.coreboot.org/c/coreboot/+/70196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6b5e066f228ea5dc79ae14dd803fc283fd248ce Gerrit-Change-Number: 70196 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Utkarsh H Patel <utkarsh.h.patel(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-CC: Utkarsh H Patel <utkarsh.h.patel(a)intel.corp-partner.google.com> Gerrit-Attention: Utkarsh H Patel <utkarsh.h.patel(a)intel.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Utkarsh H Patel <utkarsh.h.patel(a)intel.com> Gerrit-Comment-Date: Fri, 02 Dec 2022 19:12:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[L] Change in coreboot[master]: soc/intel/common, alderlake: provide a list of D-states to enter LPM
by Eran Mitrani (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Tarun Tuli, Eran Mitrani. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70166 to look at the new patch set (#8). Change subject: soc/intel/common, alderlake: provide a list of D-states to enter LPM ...................................................................... soc/intel/common, alderlake: provide a list of D-states to enter LPM This was done previously for ADL. moving the code to common so it can be leveraged for other platforms (e.g. MTL) TEST=Built and tested on anahera by verifying SSDT contents Change-Id: I45eded3868a4987cb5eb0676c50378ac52ec3752 Signed-off-by: Eran Mitrani <mitrani(a)google.com> --- M src/include/acpi/acpi.h M src/soc/intel/alderlake/acpi.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/acpi/pep.c M src/soc/intel/common/block/include/intelblocks/acpi.h 5 files changed, 207 insertions(+), 165 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/70166/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/70166 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45eded3868a4987cb5eb0676c50378ac52ec3752 Gerrit-Change-Number: 70166 Gerrit-PatchSet: 8 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: [TEST ONLY] Second test upload code
by Jamie Chen (Code Review) 02 Dec '22

02 Dec '22

Jamie Chen has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/70257 ) Change subject: [TEST ONLY] Second test upload code ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/70257 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieceedc32a456dc584848954f7321f79d17630d87 Gerrit-Change-Number: 70257 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-MessageType: abandon

1 0

[S] Change in coreboot[master]: [TEST ONLY] Second test upload code
by Jamie Chen (Code Review) 02 Dec '22

02 Dec '22

Jamie Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70257 ) Change subject: [TEST ONLY] Second test upload code ...................................................................... [TEST ONLY] Second test upload code Change-Id: Ieceedc32a456dc584848954f7321f79d17630d87 Signed-off-by: jamie_chen <jamie_chen(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/xivu/overridetree.cb 1 file changed, 13 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/70257/1 diff --git a/src/mainboard/google/brya/variants/xivu/overridetree.cb b/src/mainboard/google/brya/variants/xivu/overridetree.cb index bfaa639..6054dbb 100644 --- a/src/mainboard/google/brya/variants/xivu/overridetree.cb +++ b/src/mainboard/google/brya/variants/xivu/overridetree.cb @@ -96,9 +96,9 @@ .speed = I2C_SPEED_FAST_PLUS, .speed_config[0] = { .speed = I2C_SPEED_FAST_PLUS, - .scl_lcnt = 55, - .scl_hcnt = 30, - .sda_hold = 7, + .scl_lcnt = 1, + .scl_hcnt = 2, + .sda_hold = 3, } }, .i2c[1] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/70257 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieceedc32a456dc584848954f7321f79d17630d87 Gerrit-Change-Number: 70257 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: libpayload: Outsource delay function into own header
by Thomas Heijligen (Code Review) 02 Dec '22

02 Dec '22

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70139 to look at the new patch set (#2). Change subject: libpayload: Outsource delay function into own header ...................................................................... libpayload: Outsource delay function into own header For libflashrom we need the delay functions but when including the whole libpayload.h it has conflicting symbols. Change-Id: I6e4a669b8ba25836fb870d74c200985c1bfdb387 Signed-off-by: Thomas Heijligen <src(a)posteo.de> --- M payloads/libpayload/include/libpayload.h A payloads/libpayload/include/libpayload/delay.h M payloads/libpayload/include/stddef.h 3 files changed, 98 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/70139/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/70139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e4a669b8ba25836fb870d74c200985c1bfdb387 Gerrit-Change-Number: 70139 Gerrit-PatchSet: 2 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[master]: mb/intel/adlrvp: Add RTD3 support for PCIe slot1
by Anil Kumar K (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Bora Guvendik, Anil Kumar K, Cliff Huang. Anil Kumar K has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70119 ) Change subject: mb/intel/adlrvp: Add RTD3 support for PCIe slot1 ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/70119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb7d207a7ec3763bad3e82522e86a825c1ed00b6 Gerrit-Change-Number: 70119 Gerrit-PatchSet: 2 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Comment-Date: Fri, 02 Dec 2022 18:12:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/intel/alderlake: Update cpu and pch tracehub modes
by Felix Held (Code Review) 02 Dec '22

02 Dec '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/64438 ) Change subject: soc/intel/alderlake: Update cpu and pch tracehub modes ...................................................................... soc/intel/alderlake: Update cpu and pch tracehub modes The patch gets the cpu and pch's tracehub mode from the debug area of the Descriptor Region and updates the respective UPDs. TEST=Build, verify the tracehub mode values. Update CPU' and PCH's Trace Hub modes: img=coreboot.rom printf '\x01' | dd of=$img bs=1 seek=3841 count=1 conv=notrunc printf '\x01' | dd of=$img bs=1 seek=3842 count=1 conv=notrunc Check coreboot logs: [DEBUG] rt_debug: CPU TraceHub Mode: 1 PCH Tracehub Mode: 1 Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I088b5d1f5569aacbf79834b44372702f8d3a189f Reviewed-on: https://review.coreboot.org/c/coreboot/+/64438 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland(a)gmail.com> --- M src/soc/intel/alderlake/romstage/fsp_params.c 1 file changed, 36 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index b603a42..90cabf8 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -8,6 +8,7 @@ #include <drivers/wifi/generic/wifi.h> #include <fsp/fsp_debug_event.h> #include <fsp/util.h> +#include <intelbasecode/debug_feature.h> #include <intelblocks/cpulib.h> #include <intelblocks/pcie_rp.h> #include <option.h> @@ -387,6 +388,11 @@ fill_fspm_params[i](m_cfg, config); } +static void debug_override_memory_init_params(FSP_M_CONFIG *mupd) +{ + debug_get_pch_cpu_tracehub_modes(&mupd->CpuTraceHubMode, &mupd->PchTraceHubMode); +} + void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { const struct soc_intel_alderlake_config *config; @@ -413,6 +419,10 @@ soc_memory_init_params(m_cfg, config); mainboard_memory_init_params(mupd); + + /* Override the memory init params through runtime debug capability */ + if (CONFIG(SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE)) + debug_override_memory_init_params(m_cfg); } __weak void mainboard_memory_init_params(FSPM_UPD *memupd) -- To view, visit https://review.coreboot.org/c/coreboot/+/64438 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I088b5d1f5569aacbf79834b44372702f8d3a189f Gerrit-Change-Number: 64438 Gerrit-PatchSet: 9 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Maulik Vaghela <maulikvaghela(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

[L] Change in coreboot[master]: mb/amd/mayan/gpio: Configure mayan GPIOs
by Felix Held (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Jason Glenesk, ritul guru, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70207 ) Change subject: mb/amd/mayan/gpio: Configure mayan GPIOs ...................................................................... Patch Set 1: (5 comments) File src/mainboard/amd/mayan/early_gpio.c: https://review.coreboot.org/c/coreboot/+/70207/comment/50bc0660_df0506d0 PS1, Line 39: do the gpios 78 and 79 (nvme ssd aux reset) also need to be configured in bootblock? File src/mainboard/amd/mayan/gpio.c: https://review.coreboot.org/c/coreboot/+/70207/comment/f9397e8e_db60040c PS1, Line 30: /* USB_HDR_P0/1/2/3_SMI_L */ the name says smi, but sci is probably the way to go, since we try to not do things in smm that don't need to be done in smm https://review.coreboot.org/c/coreboot/+/70207/comment/38d36ed1_e33ab102 PS1, Line 112: /* Unused */ is it unused or not available on the package? https://review.coreboot.org/c/coreboot/+/70207/comment/035390ad_bf0d6333 PS1, Line 158: PAD_SCI(GPIO_139, PULL_UP, EDGE_LOW), this isn't a gevent capable gpio https://review.coreboot.org/c/coreboot/+/70207/comment/54ca79b6_9f5ea413 PS1, Line 187: PAD_SCI(GPIO_157, PULL_UP, EDGE_LOW), this isn't a gevent capable gpio -- To view, visit https://review.coreboot.org/c/coreboot/+/70207 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I283afc716487fd8fa6d455194c382d87a3e6860b Gerrit-Change-Number: 70207 Gerrit-PatchSet: 1 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 02 Dec 2022 17:45:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2022