coreboot-gerrit December 2022

coreboot-gerrit@coreboot.org

1 participants
6828 discussions

[M] Change in coreboot[master]: soc/intel/alderlake: Add romstage early graphics support
by Jérémy Compostella (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Tarun Tuli, Subrata Banik. Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70303 ) Change subject: soc/intel/alderlake: Add romstage early graphics support ...................................................................... soc/intel/alderlake: Add romstage early graphics support BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=TO-BE-COMPLETED Change-Id: I727b28bbe180edc2574e09bf03f1534d6282bdb2 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/romstage/Makefile.inc A src/soc/intel/alderlake/romstage/graphics.c 4 files changed, 109 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/70303/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 08d4132..a44cb98 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -205,6 +205,13 @@ hex default 0x10000 +if ROMSTAGE_GFX_GMA + +config GFX_GMA_DEFAULT_MMIO + default 0x81000000 + +endif # ROMSTAGE_GFX_GMA + # Intel recommends reserving the following resources per PCIe TBT root port, # from ADL BIOS Spec (doc #627270) Revision 0.6.0 Section 7.2.5.1.5 # - 42 buses diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index a732fe6..bd0b670 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -6,6 +6,7 @@ #include <drivers/i2c/designware/dw_i2c.h> #include <drivers/intel/gma/gma.h> #include <device/pci_ids.h> +#include <drivers/intel/gma/gma.h> #include <intelblocks/cfg.h> #include <intelblocks/gpio.h> #include <intelblocks/gspi.h> @@ -673,6 +674,11 @@ /* i915 struct for GMA backlight control */ struct i915_gpu_controller_info gfx; + + /* + * IGD panel configuration + */ + struct i915_gpu_panel_config panel_cfg; }; typedef struct soc_intel_alderlake_config config_t; diff --git a/src/soc/intel/alderlake/romstage/Makefile.inc b/src/soc/intel/alderlake/romstage/Makefile.inc index 99c1d2c..9714b62 100644 --- a/src/soc/intel/alderlake/romstage/Makefile.inc +++ b/src/soc/intel/alderlake/romstage/Makefile.inc @@ -4,3 +4,4 @@ romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += romstage.c romstage-y += systemagent.c +romstage-$(CONFIG_ROMSTAGE_GFX_GMA) += graphics.c diff --git a/src/soc/intel/alderlake/romstage/graphics.c b/src/soc/intel/alderlake/romstage/graphics.c new file mode 100644 index 0000000..a449699 --- /dev/null +++ b/src/soc/intel/alderlake/romstage/graphics.c @@ -0,0 +1,81 @@ +#include <arch/cpu.h> +#include <arch/mmio.h> +#include <cpu/x86/msr.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <drivers/intel/gma/i915_reg.h> +#include <intelblocks/early_graphics.h> +#include <soc/soc_chip.h> + +static void wait_txt_clear(void) +{ + struct cpuid_result cp = cpuid_ext(1, 0); + + /* Check if TXT is supported */ + if (!(cp.ecx & (1 << 6))) + return; + + /* Some TXT public bit */ + if (!(read32((void *)0xfed30010) & 1)) + return; + + /* Wait for TXT clear */ + while (!(read8((void *)0xfed40000) & (1 << 7))) + ; +} + +void early_graphics_soc_device_init(void) +{ + pci_devfn_t gfx_dev = PCI_DEV(0, 2, 0); + + /* Minimal GFX PCI initialization with BAR0 setup. */ + pci_or_config16(gfx_dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_write_config32(gfx_dev, PCI_BASE_ADDRESS_0, + CONFIG_GFX_GMA_DEFAULT_MMIO); + pci_write_config16(gfx_dev, PCI_COMMAND, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY); + + /* Ensure memory is unlocked. When the memory is locked, some accesses + to the graphics IP may unexpectedly fail. */ + msr_t msrval = { 0 }; + wait_txt_clear(); + wrmsr(0x2e6, msrval); +} + +void early_graphics_soc_panel_init(void) +{ + const struct soc_intel_alderlake_config *soc_conf; + const struct i915_gpu_panel_config *panel_cfg; + void *mmio = (void *)CONFIG_GFX_GMA_DEFAULT_MMIO; + uint32_t reg32; + unsigned int pwm_period, pwm_polarity, pwm_duty; + + soc_conf = config_of_soc(); + panel_cfg = &soc_conf->panel_cfg; + + reg32 = ((DIV_ROUND_UP(panel_cfg->cycle_delay_ms, 100) + 1) & 0x1f) << 4; + reg32 |= PANEL_POWER_RESET; + write32(mmio + PCH_PP_CONTROL, reg32); + + reg32 = ((panel_cfg->up_delay_ms * 10) & 0x1fff) << 16; + reg32 |= (panel_cfg->backlight_on_delay_ms * 10) & 0x1fff; + write32(mmio + PCH_PP_ON_DELAYS, reg32); + + reg32 = ((panel_cfg->down_delay_ms * 10) & 0x1fff) << 16; + reg32 |= (panel_cfg->backlight_off_delay_ms * 10) & 0x1fff; + write32(mmio + PCH_PP_OFF_DELAYS, reg32); + + if (!panel_cfg->backlight_pwm_hz) + return; + + /* Configure backlight */ + pwm_polarity = panel_cfg->backlight_polarity ? BXT_BLC_PWM_POLARITY : 0; + pwm_period = DIV_ROUND_CLOSEST(CONFIG_CPU_XTAL_HZ, + panel_cfg->backlight_pwm_hz); + pwm_duty = DIV_ROUND_CLOSEST(pwm_period, 2); /* Start with 50 % */ + write32(mmio + BXT_BLC_PWM_FREQ(0), pwm_period); + write32(mmio + BXT_BLC_PWM_CTL(0), pwm_polarity); + write32(mmio + BXT_BLC_PWM_DUTY(0), pwm_duty); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/70303 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I727b28bbe180edc2574e09bf03f1534d6282bdb2 Gerrit-Change-Number: 70303 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: cpu/intel/car/romstage: Clear graphics before exiting romstage
by Jérémy Compostella (Code Review) 02 Dec '22

02 Dec '22

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70302 ) Change subject: cpu/intel/car/romstage: Clear graphics before exiting romstage ...................................................................... cpu/intel/car/romstage: Clear graphics before exiting romstage Leaving the graphics configuration with the display on confuses the FSP GOP driver and can lead to undesired graphics artifacts. This CL introduces the GRAPHICS_OFF_BEFORE_RAMSTAGE configuration flag to trigger graphic off procedure. BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=TO-BE-COMPLETED Change-Id: I31b6470478177938f988afe11febaadd165c4b52 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/cpu/intel/car/romstage.c M src/device/Kconfig 2 files changed, 35 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/70302/1 diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 7df512d..70948e9 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -6,6 +6,7 @@ #include <commonlib/helpers.h> #include <console/console.h> #include <cpu/x86/smm.h> +#include <intelblocks/early_graphics.h> #include <program_loading.h> #include <romstage_common.h> #include <security/vboot/vboot_common.h> @@ -65,6 +66,9 @@ if (CONFIG(SMM_TSEG)) smm_list_regions(); + if (CONFIG(GRAPHICS_OFF_BEFORE_RAMSTAGE)) + early_graphics_stop(); + prepare_and_run_postcar(); /* We do not return here. */ } diff --git a/src/device/Kconfig b/src/device/Kconfig index b0000f6..2e0e529 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -146,6 +146,17 @@ endchoice +config GRAPHICS_OFF_BEFORE_RAMSTAGE + bool "Turn off graphics before jumping to ramstage" + depends on MAINBOARD_USE_ROMSTAGE_LIBGFXINIT + default y if RUN_FSP_GOP + default n + help + Clear graphics configuration at the end of romstage. + Leaving graphic configuration performed by libgfxinit with + the display turned on confuses the FSP GOP driver and it can + lead to undesirable graphic artifacts. + config PRE_GRAPHICS_DELAY_MS int "Graphics initialization delay in ms" default 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/70302 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31b6470478177938f988afe11febaadd165c4b52 Gerrit-Change-Number: 70302 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: drivers/intel/gma: Enable AlderLake libgfxinit support
by Jérémy Compostella (Code Review) 02 Dec '22

02 Dec '22

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70301 ) Change subject: drivers/intel/gma: Enable AlderLake libgfxinit support ...................................................................... drivers/intel/gma: Enable AlderLake libgfxinit support This CL requires the following libgfxinit patches: - https://review.coreboot.org/c/libgfxinit/+/65087 - https://review.coreboot.org/c/libgfxinit/+/65178 - https://review.coreboot.org/c/libgfxinit/+/67489 - https://review.coreboot.org/c/libgfxinit/+/65140 - https://review.coreboot.org/c/libgfxinit/+/67490 - https://review.coreboot.org/c/libgfxinit/+/67491 - https://review.coreboot.org/c/libgfxinit/+/67492 - https://review.coreboot.org/c/libgfxinit/+/67493 - https://review.coreboot.org/c/libgfxinit/+/67494 - https://review.coreboot.org/c/libgfxinit/+/67495 - https://review.coreboot.org/c/libgfxinit/+/67496 - https://review.coreboot.org/c/libgfxinit/+/67497 - https://review.coreboot.org/c/libgfxinit/+/67498 - https://review.coreboot.org/c/libgfxinit/+/67499 - https://review.coreboot.org/c/libgfxinit/+/67500 - https://review.coreboot.org/c/libgfxinit/+/67800 - https://review.coreboot.org/c/libgfxinit/+/67801 - https://review.coreboot.org/c/libgfxinit/+/67802 - https://review.coreboot.org/c/libgfxinit/+/69341 BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=TO-BE-COMPLETED Change-Id: I2de94556f8105447788aaa02340ad669fb68ca0c Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/drivers/intel/gma/Kconfig 1 file changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/70301/1 diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index c923e0b..20dee17 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -139,6 +139,7 @@ default "Haswell" if NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL default "Ironlake" if NORTHBRIDGE_INTEL_IRONLAKE || NORTHBRIDGE_INTEL_SANDYBRIDGE default "G45" if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X + default "Tigerlake" if SOC_INTEL_ALDERLAKE config GFX_GMA_PCH string @@ -147,6 +148,7 @@ default "Lynx_Point" if NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL default "Sunrise_Point" if SOC_INTEL_COMMON_SKYLAKE_BASE default "Cannon_Point" if SOC_INTEL_CANNONLAKE_BASE + default "Alder_Point" if SOC_INTEL_ALDERLAKE default "No_PCH" config GFX_GMA_PANEL_1_PORT -- To view, visit https://review.coreboot.org/c/coreboot/+/70301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2de94556f8105447788aaa02340ad669fb68ca0c Gerrit-Change-Number: 70301 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: drivers/intel/fsp2_0/memory_init: inform user of memory training
by Jérémy Compostella (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Andrey Petrov. Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70300 ) Change subject: drivers/intel/fsp2_0/memory_init: inform user of memory training ...................................................................... drivers/intel/fsp2_0/memory_init: inform user of memory training If memory training is going to happen and early graphics is supported by the mainboard, the `CONFIG_DISPLAY_MSG_DURING_MEMORY_TRAINING' option makes coreboot display (on screen) the `CONFIG_MEMORY_TRAINING_MSG' text message to inform the user that memory training is in progress. Memory training can take a while and an impatient end user facing a black screen for a while may reset the device unnecessarily. Note: macro compilation had to be used because the `CONFIG_MEMORY_TRAINING_MSG' is a string and as such is not systematically defined. Change-Id: I4ea15123eed1a4355c5ff7d815925032d4151de0 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/memory_init.c 2 files changed, 63 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/70300/1 diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 8c36063..e7677ec 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -39,6 +39,22 @@ 1. Added ExtendedImageRevision field in FSP_INFO_HEADER 2. Added FSP_NON_VOLATILE_STORAGE_HOB2 +config INFORM_USER_OF_MEMORY_TRAINING + bool + default n + depends on ROMSTAGE_GFX_GMA + help + Display a message on-screen to inform the end-user that + memory training is in progress + +config MEMORY_TRAINING_TEXT + string "Text to display during memory training" + default "Memory training in progress, please wait..." + depends on INFORM_USER_OF_MEMORY_TRAINING + help + Message to be displayed while memory training is in + progress. It should not exceed 80 characters. + if PLATFORM_USES_FSP2_0 config PLATFORM_USES_FSP2_X86_32 diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 99b0fea..61e6f1d 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -10,9 +10,11 @@ #include <elog.h> #include <fsp/api.h> #include <fsp/util.h> +#include <intelblocks/early_graphics.h> #include <memrange.h> #include <mode_switch.h> #include <mrc_cache.h> +#include <pc80/vga.h> #include <program_loading.h> #include <romstage_handoff.h> #include <security/tpm/tspi.h> @@ -221,6 +223,20 @@ struct memranges memmap; }; +static void inform_user_of_memory_training(bool start) +{ +#if CONFIG(INFORM_USER_OF_MEMORY_TRAINING) + static bool vga_ready; + const char *str = start ? CONFIG_MEMORY_TRAINING_TEXT : ""; + + if (!vga_ready) + vga_ready = early_graphics_init(); + + if (vga_ready) + vga_line_write_centered(12, str); +#endif +} + static void do_fsp_memory_init(const struct fspm_context *context, bool s3wake) { uint32_t status; @@ -288,6 +304,10 @@ post_code(POST_MEM_PREINIT_PREP_END); + /* Inform the end user that memory training is in progress. */ + if (!arch_upd->NvsBufferPtr) + inform_user_of_memory_training(true); + /* Call FspMemoryInit */ fsp_raminit = (void *)(uintptr_t)(hdr->image_base + hdr->fsp_memory_init_entry_offset); fsp_debug_before_memory_init(fsp_raminit, upd, &fspm_upd); @@ -307,6 +327,10 @@ post_code(POST_FSP_MEMORY_EXIT); timestamp_add_now(TS_FSP_MEMORY_INIT_END); + /* Memory training is over, clear the end-user notification. */ + if (!arch_upd->NvsBufferPtr) + inform_user_of_memory_training(false); + /* Handle any errors returned by FspMemoryInit */ fsp_handle_reset(status); if (status != FSP_SUCCESS) { -- To view, visit https://review.coreboot.org/c/coreboot/+/70300 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ea15123eed1a4355c5ff7d815925032d4151de0 Gerrit-Change-Number: 70300 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: soc/intel/common/block: Add Intel VGA early graphics support
by Jérémy Compostella (Code Review) 02 Dec '22

02 Dec '22

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70299 ) Change subject: soc/intel/common/block: Add Intel VGA early graphics support ...................................................................... soc/intel/common/block: Add Intel VGA early graphics support This patch introduces an early graphics driver which can be used in romstage in cache-as-ram mode. The implementation relies on `libgfxinit' and provide VGA text mode support. SoCs wanting to take advantage of this driver must implement the following functions: - `void early_graphics_soc_device_init(void)' to set the graphic device MMIO to the `CONFIG_GFX_GMA_DEFAULT_MMIO' value (typically PCI graphic device Base Address Register 0). - `void early_graphics_soc_panel_init(void)' to set the panel power sequence timing parameters. BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=TO-BE-COMPLETED Change-Id: Ie4ad1215e5fadd0adc1271b6bd6ddb0ea258cb5b Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/drivers/intel/gma/gma-gfx_init.ads M src/drivers/intel/gma/hires_fb/gma-gfx_init.adb M src/drivers/intel/gma/libgfxinit.h M src/drivers/intel/gma/text_fb/gma-gfx_init.adb M src/soc/intel/common/block/graphics/Kconfig M src/soc/intel/common/block/graphics/Makefile.inc A src/soc/intel/common/block/graphics/early_graphics.c A src/soc/intel/common/block/include/intelblocks/early_graphics.h 8 files changed, 149 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/70299/1 diff --git a/src/drivers/intel/gma/gma-gfx_init.ads b/src/drivers/intel/gma/gma-gfx_init.ads index 4998d33..fc45672 100644 --- a/src/drivers/intel/gma/gma-gfx_init.ads +++ b/src/drivers/intel/gma/gma-gfx_init.ads @@ -11,6 +11,9 @@ procedure gfxinit (lightup_ok : out Interfaces.C.int); pragma Export (C, gfxinit, "gma_gfxinit"); + procedure gfxstop (stop_ok : out Interfaces.C.int); + pragma Export (C, gfxstop, "gma_gfxstop"); + ---------------------------------------------------------------------------- function c_fb_add_framebuffer_info diff --git a/src/drivers/intel/gma/hires_fb/gma-gfx_init.adb b/src/drivers/intel/gma/hires_fb/gma-gfx_init.adb index b213030..83516af 100644 --- a/src/drivers/intel/gma/hires_fb/gma-gfx_init.adb +++ b/src/drivers/intel/gma/hires_fb/gma-gfx_init.adb @@ -97,4 +97,17 @@ end if; end gfxinit; + procedure gfxstop (stop_ok : out Interfaces.C.int) + is + success : boolean; + begin + HW.GFX.GMA.Initialize (Clean_State => True, + Success => success); + if success then + stop_ok := 1; + else + stop_ok := 0; + end if; + end gfxstop; + end GMA.GFX_Init; diff --git a/src/drivers/intel/gma/libgfxinit.h b/src/drivers/intel/gma/libgfxinit.h index 9a7e1c6..3270b91 100644 --- a/src/drivers/intel/gma/libgfxinit.h +++ b/src/drivers/intel/gma/libgfxinit.h @@ -17,6 +17,7 @@ }; void gma_gfxinit(int *lightup_ok); +void gma_gfxstop(int *stop_ok); int gma_read_edid(unsigned char edid[], int port); #endif diff --git a/src/drivers/intel/gma/text_fb/gma-gfx_init.adb b/src/drivers/intel/gma/text_fb/gma-gfx_init.adb index d273852..da1e609 100644 --- a/src/drivers/intel/gma/text_fb/gma-gfx_init.adb +++ b/src/drivers/intel/gma/text_fb/gma-gfx_init.adb @@ -56,4 +56,17 @@ end if; end gfxinit; + procedure gfxstop (stop_ok : out Interfaces.C.int) + is + success : boolean; + begin + HW.GFX.GMA.Initialize (Clean_State => True, + Success => success); + if success then + stop_ok := 1; + else + stop_ok := 0; + end if; + end gfxstop; + end GMA.GFX_Init; diff --git a/src/soc/intel/common/block/graphics/Kconfig b/src/soc/intel/common/block/graphics/Kconfig index 8520e53..c63f5c2 100644 --- a/src/soc/intel/common/block/graphics/Kconfig +++ b/src/soc/intel/common/block/graphics/Kconfig @@ -1,5 +1,6 @@ config SOC_INTEL_COMMON_BLOCK_GRAPHICS bool + select ROMSTAGE_VGA if MAINBOARD_USE_ROMSTAGE_LIBGFXINIT help Intel Processor common Graphics support diff --git a/src/soc/intel/common/block/graphics/Makefile.inc b/src/soc/intel/common/block/graphics/Makefile.inc index ac7df44..9c8cad9 100644 --- a/src/soc/intel/common/block/graphics/Makefile.inc +++ b/src/soc/intel/common/block/graphics/Makefile.inc @@ -1,2 +1,3 @@ ## SPDX-License-Identifier: GPL-2.0-only ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS) += graphics.c +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS) += early_graphics.c diff --git a/src/soc/intel/common/block/graphics/early_graphics.c b/src/soc/intel/common/block/graphics/early_graphics.c new file mode 100644 index 0000000..d2092db --- /dev/null +++ b/src/soc/intel/common/block/graphics/early_graphics.c @@ -0,0 +1,58 @@ +#include <acpi/acpi.h> +#include <console/console.h> +#include <drivers/intel/gma/libgfxinit.h> +#include <intelblocks/early_graphics.h> + +static bool initialized; + +/* SoC Overrides */ +__weak void early_graphics_soc_device_init(void) +{ + /* + * User needs to implement SoC override. + */ +} + +__weak void early_graphics_soc_panel_init(void) +{ + /* + * User needs to implement SoC override. + */ +} + +bool early_graphics_init(void) +{ + static bool attempted; + int ret; + + if (attempted) + return initialized; + + attempted = true; + + if (!CONFIG(MAINBOARD_USE_ROMSTAGE_LIBGFXINIT)) + return false; + + early_graphics_soc_device_init(); + early_graphics_soc_panel_init(); + + gma_gfxinit(&ret); + initialized = !!ret; + + return initialized; +} + +void early_graphics_stop(void) +{ + int ret; + + if (!initialized) + return; + + /* Graphics MMIO device configuration may have been corrupted since it + * has been initialized. The execution of a binary block such as FSP may + * indeed have reset the PCI BAR0 address of the graphic device. */ + early_graphics_soc_device_init(); + + gma_gfxstop(&ret); +} diff --git a/src/soc/intel/common/block/include/intelblocks/early_graphics.h b/src/soc/intel/common/block/include/intelblocks/early_graphics.h new file mode 100644 index 0000000..275c17c --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/early_graphics.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_INTEL_COMMON_BLOCK_GRAPHICS_EARLY_H +#define SOC_INTEL_COMMON_BLOCK_GRAPHICS_EARLY_H + +#include <stdbool.h> + +/* + * SoC overrides + * + * All new SoC must implement below functionality. + */ + +/* Perform minimal graphic MMIO configuration. */ +void early_graphics_soc_device_init(void); + +/* Configure display panel */ +void early_graphics_soc_panel_init(void); + +/* + * Early graphics module API + * Graphics at this stage is limited to VGA text mode. + */ + +/* Initialize graphics. Return true if VGA text mode is ready to use. */ +bool early_graphics_init(void); + +/* Clear graphics configuration, turn off the displays. */ +void early_graphics_stop(void); + +#endif /* SOC_INTEL_COMMON_BLOCK_GRAPHICS_EARLY_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/70299 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4ad1215e5fadd0adc1271b6bd6ddb0ea258cb5b Gerrit-Change-Number: 70299 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: drivers/pc80/vga: Add romstage support
by Jérémy Compostella (Code Review) 02 Dec '22

02 Dec '22

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70278 ) Change subject: drivers/pc80/vga: Add romstage support ...................................................................... drivers/pc80/vga: Add romstage support BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=TO-BE-COMPLETED Change-Id: I81309871e8db71657b2a9816708141f121d767d3 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/drivers/pc80/vga/Kconfig M src/drivers/pc80/vga/Makefile.inc 2 files changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/70278/1 diff --git a/src/drivers/pc80/vga/Kconfig b/src/drivers/pc80/vga/Kconfig index 7da71af..0df65bc 100644 --- a/src/drivers/pc80/vga/Kconfig +++ b/src/drivers/pc80/vga/Kconfig @@ -2,3 +2,8 @@ bool help Include legacy VGA support code. + +config ROMSTAGE_VGA + bool + help + Include legacy VGA support code in romstage. diff --git a/src/drivers/pc80/vga/Makefile.inc b/src/drivers/pc80/vga/Makefile.inc index 3e31de1..5eb7da9 100644 --- a/src/drivers/pc80/vga/Makefile.inc +++ b/src/drivers/pc80/vga/Makefile.inc @@ -5,4 +5,9 @@ ramstage-$(CONFIG_VGA) += vga_font_8x16.c ramstage-$(CONFIG_VGA) += vga.c +romstage-$(CONFIG_ROMSTAGE_VGA) += vga_io.c +romstage-$(CONFIG_ROMSTAGE_VGA) += vga_palette.c +romstage-$(CONFIG_ROMSTAGE_VGA) += vga_font_8x16.c +romstage-$(CONFIG_ROMSTAGE_VGA) += vga.c + endif -- To view, visit https://review.coreboot.org/c/coreboot/+/70278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81309871e8db71657b2a9816708141f121d767d3 Gerrit-Change-Number: 70278 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: drivers/pc80/vga: display a string centered on a line
by Jérémy Compostella (Code Review) 02 Dec '22

02 Dec '22

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70277 ) Change subject: drivers/pc80/vga: display a string centered on a line ...................................................................... drivers/pc80/vga: display a string centered on a line This patch introduces the `vga_line_write_centered(unsigned int line, const char *string)' function to display a centered line of text. The string length is limited to eighy characters. BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=TO-BE-COMPLETED Change-Id: Ie742795bb44bbea8cf24222e7bd4f355a6fece2f Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/drivers/pc80/vga/vga.c M src/include/pc80/vga.h 2 files changed, 41 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/70277/1 diff --git a/src/drivers/pc80/vga/vga.c b/src/drivers/pc80/vga/vga.c index d970fea..1719cba 100644 --- a/src/drivers/pc80/vga/vga.c +++ b/src/drivers/pc80/vga/vga.c @@ -274,6 +274,28 @@ } /* + * fills a line centering the given string. + * The string is truncated it exceeds 80 characters. + */ +void +vga_line_write_centered(unsigned int line, const char *string) +{ + unsigned short *p = (unsigned short *) VGA_FB + (80 * line); + size_t i, margin, len = strlen(string); + + if (len > 80) + len = 80; + margin = 40 - (len / 2); + + for (i = 0; i < 80; i++) { + if (i < margin || i > 80 - margin) + p[i] = 0x0F00; + else + p[i] = 0x0F00 | string[i - margin]; + } +} + +/* * set up everything to get a basic 80x25 textmode. */ void diff --git a/src/include/pc80/vga.h b/src/include/pc80/vga.h index 4b7b26c..9e72f6f 100644 --- a/src/include/pc80/vga.h +++ b/src/include/pc80/vga.h @@ -19,5 +19,6 @@ void vga_frame_set(unsigned int line, unsigned int character); void vga_line_write(unsigned int line, const char *string); +void vga_line_write_centered(unsigned int line, const char *string); #endif /* VGA_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/70277 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie742795bb44bbea8cf24222e7bd4f355a6fece2f Gerrit-Change-Number: 70277 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: drivers/intel/gma: Hook up libgfxinit in romstage
by Jérémy Compostella (Code Review) 02 Dec '22

02 Dec '22

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70276 ) Change subject: drivers/intel/gma: Hook up libgfxinit in romstage ...................................................................... drivers/intel/gma: Hook up libgfxinit in romstage A mainboard port needs to: - select `CONFIG_ROMSTAGE_MAINBOARD_HAS_LIBGFXINIT' - implement the Ada package `GMA.Mainboard' with a single function `ports' that returns a list of ports to be probed for displays. - set the desired `GFX_GMA_DEFAULT_MMIO' IO memory address to use in romstage for the graphic device. This CL requires the libgfxinit https://review.coreboot.org/c/libgfxinit/+/69855 patch. BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=TO-BE-COMPLETED Change-Id: I3c2101de10dc5df54fe873e43bbe0f1c4dccff44 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/arch/x86/car.ld M src/device/Kconfig M src/drivers/intel/gma/Kconfig M src/drivers/intel/gma/Makefile.inc 4 files changed, 107 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/70276/1 diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index dc075c6..d1048a3 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -73,6 +73,9 @@ #if CONFIG(ROMSTAGE_LIBHWBASE) *(.data.hw__*_E) #endif +#if CONFIG(ROMSTAGE_GFX_GMA) + *(.data.gma*_E) +#endif . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _ebss = .; RECORD_SIZE(bss) diff --git a/src/device/Kconfig b/src/device/Kconfig index 34600ad..b0000f6 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -4,7 +4,7 @@ config HAVE_VGA_TEXT_FRAMEBUFFER bool - depends on !NO_GFX_INIT + depends on !(NO_GFX_INIT && NO_ROMSTAGE_GFX_INIT) help Selected by graphics drivers that support legacy VGA text mode. @@ -58,6 +58,13 @@ Selected by mainboards that implement support for `libgfxinit`. Usually this requires a list of ports to be probed for displays. +config MAINBOARD_HAS_ROMSTAGE_LIBGFXINIT + def_bool n + help + Selected by mainboards that implement support for `libgfxinit` + in romstage. Usually this requires a list of ports to be + probed for displays. + choice prompt "Graphics initialization" default NO_GFX_INIT if VGA_ROM_RUN_DEFAULT && PAYLOAD_SEABIOS @@ -117,6 +124,28 @@ endchoice +choice + prompt "Early (romstage) graphics initialization" + default MAINBOARD_USE_ROMSTAGE_LIBGFXINIT if MAINBOARD_HAS_ROMSTAGE_LIBGFXINIT + default NO_ROMSTAGE_GFX_INIT + +config NO_ROMSTAGE_GFX_INIT + bool "None" + help + Select this to not perform any graphics initialization at + romstage. + +config MAINBOARD_USE_ROMSTAGE_LIBGFXINIT + bool "Use libgfxinit" + depends on MAINBOARD_HAS_ROMSTAGE_LIBGFXINIT + select ROMSTAGE_VGA + help + Use the SPARK library `libgfxinit` for the romstage native + graphics initialization. This requires an Ada + toolchain. Graphics at romstage is limited to VGA text mode. + +endchoice + config PRE_GRAPHICS_DELAY_MS int "Graphics initialization delay in ms" default 0 diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index 87f6d12..c923e0b 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -90,15 +90,29 @@ depends on MAINBOARD_USE_LIBGFXINIT || INTEL_GMA_LIBGFXINIT_EDID select RAMSTAGE_LIBHWBASE +config ROMSTAGE_GFX_GMA + def_bool y + depends on SOC_INTEL_ALDERLAKE + depends on MAINBOARD_USE_ROMSTAGE_LIBGFXINIT + select ROMSTAGE_LIBHWBASE + +config GFX_GMA_DEFAULT_MMIO + hex + depends on HWBASE_STATIC_MMIO && (GFX_GMA || ROMSTAGE_GFX_GMA) + help + Graphic MMIO address + config GFX_GMA_PANEL_1_ON_EDP bool - depends on GFX_GMA || MAINBOARD_HAS_LIBGFXINIT + depends on GFX_GMA || MAINBOARD_HAS_LIBGFXINIT \ + || MAINBOARD_HAS_ROMSTAGE_LIBGFXINIT default n if GFX_GMA_PANEL_1_ON_LVDS default y config GFX_GMA_PANEL_1_ON_LVDS bool - depends on GFX_GMA || MAINBOARD_HAS_LIBGFXINIT + depends on GFX_GMA || MAINBOARD_HAS_LIBGFXINIT \ + || MAINBOARD_HAS_ROMSTAGE_LIBGFXINIT default y if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_IRONLAKE default n @@ -111,7 +125,7 @@ bool default n -if GFX_GMA +if GFX_GMA || ROMSTAGE_GFX_GMA config GFX_GMA_DYN_CPU def_bool y diff --git a/src/drivers/intel/gma/Makefile.inc b/src/drivers/intel/gma/Makefile.inc index 5588e5a..6db1321 100644 --- a/src/drivers/intel/gma/Makefile.inc +++ b/src/drivers/intel/gma/Makefile.inc @@ -20,24 +20,39 @@ $(call add_vbt_to_cbfs, vbt.bin, $(call strip_quotes,$(CONFIG_INTEL_GMA_VBT_FILE))) -ifeq ($(CONFIG_GFX_GMA),y) +ifneq (,$(filter y, $(CONFIG_GFX_GMA) $(CONFIG_ROMSTAGE_GFX_GMA))) + +gfx-gma-stages = \ + $(if $(filter y,$(CONFIG_ROMSTAGE_GFX_GMA)),romstage) \ + $(if $(filter y,$(CONFIG_GFX_GMA)),ramstage) \ $(call add-special-class,gfxinit) -gfxinit-handler = $(eval ramstage-srcs += $(1)$(2)) +gfxinit-handler +=$(foreach stage, $(gfx-gma-stages), \ + $(eval $(stage)-srcs += $$(addprefix $(1),$(2)))) $(call add-special-class,gfxinit-gen) -gfxinit-gen-handler = \ +gfxinit-gen-handler += \ $(eval additional-dirs += $(dir $(2))) \ - $(eval ramstage-srcs += $(2)) \ - $(eval ramstage-ads-deps += $(2)) \ - $(eval ramstage-adb-deps += $(2)) \ + $(foreach stage, $(gfx-gma-stages), \ + $(eval $(stage)-srcs += $(2)) \ + $(eval $(stage)-ads-deps += $(2)) \ + $(eval $(stage)-adb-deps += $(2))) \ $(eval $(2): $(obj)/config.h) +ifeq ($(CONFIG_GFX_GMA_DEFAULT_MMIO),) CONFIG_GFX_GMA_DEFAULT_MMIO := 0 # dummy, will be overwritten at runtime +else +$(call to-ada-hex,CONFIG_GFX_GMA_DEFAULT_MMIO) +endif subdirs-y += ../../../../3rdparty/libgfxinit -ramstage-y += gma.ads gma.adb +$(foreach stage,$(gfx-gma-stages), \ + $(eval $(stage)-y += gma.ads gma.adb)) + +endif # CONFIG_GFX_GMA || CONFIG_ROMSTAGE_GFX_GMA + +ifeq ($(CONFIG_GFX_GMA),y) ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-gfx_init.ads ifeq ($(CONFIG_LINEAR_FRAMEBUFFER),y) @@ -47,3 +62,11 @@ endif endif # CONFIG_GFX_GMA + +ifeq ($(CONFIG_ROMSTAGE_GFX_GMA),y) + +romstage-$(CONFIG_MAINBOARD_USE_ROMSTAGE_LIBGFXINIT) += \ + gma-gfx_init.ads \ + text_fb/gma-gfx_init.adb + +endif # CONFIG_ROMSTAGE_GFX_GMA -- To view, visit https://review.coreboot.org/c/coreboot/+/70276 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c2101de10dc5df54fe873e43bbe0f1c4dccff44 Gerrit-Change-Number: 70276 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: lib: Hook up libhwbase in romstage
by Jérémy Compostella (Code Review) 02 Dec '22

02 Dec '22

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70275 ) Change subject: lib: Hook up libhwbase in romstage ...................................................................... lib: Hook up libhwbase in romstage It's hidden behind the configuration option `CONFIG_ROMSTAGE_LIBHWBASE'. This also adds some glue code to use the coreboot console for debug output and our monotonic timer framework as timer backend. Running Ada code in romstage and more particular libhwbase brings a few challenges as global initialized variables are not supported in Cache-As-Ram mode. 1. The libhwbase dynamic mmio driver implementation makes the Gnat compiler generate some global initialized variables. For this reason, when compiled for romstage or for romstage and ramstage the static mmio driver is enforced (`HWBASE_STATIC_MMIO'). 2. The Gnat compiler generates elaboration functions to initialize program data at runtime. These elaboration functions are called by the romstage_adainit() function. The data references symbols suffixed by `_E'. Even though these symbols, at compilation time, do not contain any data and are filled with zeros, the Gnat compiler installs them in the .data section. Since these symbols are actually filled with zeros, it is safe to install them in the .bss section. cf. https://docs.adacore.com/gnat_ugn-docs/html/gnat_ugn/gnat_ugn/elaboration_o… This patch requires the libhwbase https://review.coreboot.org/c/libhwbase/+/69854 CL. BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=TO-BE-COMPLETED Change-Id: I670249d33506e886a683e55d1589cb2bf9b16aa3 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/arch/x86/car.ld M src/console/Makefile.inc M src/lib/Kconfig M src/lib/Makefile.inc 4 files changed, 85 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/70275/1 diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 47afd78..dc075c6 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -67,6 +67,12 @@ *(.bss.*) *(.sbss) *(.sbss.*) + /* '*_E' GNAT generated global variables actually are un-initialized + * (filled with zeros) variables which are initialized at + * runtime. Therefore, they can be placed in the _bss region. */ +#if CONFIG(ROMSTAGE_LIBHWBASE) + *(.data.hw__*_E) +#endif . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _ebss = .; RECORD_SIZE(bss) diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index e2a20d7..4296426 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -5,6 +5,8 @@ ifeq ($(CONFIG_HWBASE_DEBUG_CB),y) ramstage-$(CONFIG_RAMSTAGE_LIBHWBASE) += hw-debug_sink.ads ramstage-$(CONFIG_RAMSTAGE_LIBHWBASE) += hw-debug_sink.adb +romstage-$(CONFIG_ROMSTAGE_LIBHWBASE) += hw-debug_sink.ads +romstage-$(CONFIG_ROMSTAGE_LIBHWBASE) += hw-debug_sink.adb endif smm-$(CONFIG_DEBUG_SMI) += init.c console.c vtxprintf.c printk.c diff --git a/src/lib/Kconfig b/src/lib/Kconfig index 96181c9..837d8ac 100644 --- a/src/lib/Kconfig +++ b/src/lib/Kconfig @@ -21,6 +21,12 @@ help Selected by features that require `libhwbase` in ramstage. +config ROMSTAGE_LIBHWBASE + bool + select ROMSTAGE_ADA + help + Selected by features that require `libhwbase` in romstage. + config FLATTENED_DEVICE_TREE bool help @@ -68,11 +74,22 @@ help Name of the FMAP region created in the default FMAP to cache SPD data. -if RAMSTAGE_LIBHWBASE +if RAMSTAGE_LIBHWBASE && !ROMSTAGE_LIBHWBASE config HWBASE_DYNAMIC_MMIO def_bool y +endif + +if ROMSTAGE_LIBHWBASE + +config HWBASE_STATIC_MMIO + def_bool y + +endif + +if RAMSTAGE_LIBHWBASE || ROMSTAGE_LIBHWBASE + config HWBASE_DEFAULT_MMCONF hex default ECAM_MMCONF_BASE_ADDRESS diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 600c6dc..6897ac5 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -342,28 +342,34 @@ ramstage-$(CONFIG_RAMSTAGE_ADA) += cb.ads romstage-$(CONFIG_ROMSTAGE_ADA) += cb.ads -ifeq ($(CONFIG_RAMSTAGE_LIBHWBASE),y) +ifneq (,$(filter y, $(CONFIG_RAMSTAGE_LIBHWBASE) $(CONFIG_ROMSTAGE_LIBHWBASE))) to-ada-hex = $(eval $(1) := 16\\\#$(patsubst 0x%,%,$($(1)))\\\#) $(call to-ada-hex,CONFIG_HWBASE_DEFAULT_MMCONF) +libhwbase-stages = $(foreach stage, romstage ramstage, \ + $(if $(filter y,$(CONFIG_$(call toupper,$(stage))_LIBHWBASE)),$(stage))) + $(call add-special-class,hw) -hw-handler = $(eval ramstage-srcs += $$(addprefix $(1),$(2))) +hw-handler +=$(foreach stage, $(libhwbase-stages), \ + $(eval $(stage)-srcs += $$(addprefix $(1),$(2)))) $(call add-special-class,hw-gen) hw-gen-handler = \ $(eval additional-dirs += $(dir $(2))) \ - $(eval ramstage-srcs += $(2)) \ - $(eval ramstage-ads-deps += $(2)) \ - $(eval ramstage-adb-deps += $(2)) \ + $(foreach stage, $(libhwbase-stages), \ + $(eval $(stage)-srcs += $(2)) \ + $(eval $(stage)-ads-deps += $(2)) \ + $(eval $(stage)-adb-deps += $(2))) \ $(eval $(2): $(obj)/config.h) subdirs-y += ../../3rdparty/libhwbase -ramstage-$(CONFIG_HAVE_MONOTONIC_TIMER) += hw-time-timer.adb +$(foreach stage,$(libhwbase-stages), \ + $(eval $(stage)-$(CONFIG_HAVE_MONOTONIC_TIMER) += hw-time-timer.adb)) -endif # CONFIG_RAMSTAGE_LIBHWBASE +endif # CONFIG_ROMSTAGE_LIBHWBASE || CONFIG_RAMSTAGE_LIBHWBASE romstage-y += spd_bin.c -- To view, visit https://review.coreboot.org/c/coreboot/+/70275 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I670249d33506e886a683e55d1589cb2bf9b16aa3 Gerrit-Change-Number: 70275 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: Add option to use Ada code in romstage
by Jérémy Compostella (Code Review) 02 Dec '22

02 Dec '22

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70274 ) Change subject: Add option to use Ada code in romstage ...................................................................... Add option to use Ada code in romstage If selected, libgnat is linked into romstage. In addition, a call to romstage_adainit() is added to support Ada program data intialization. BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=TO-BE-COMPLETED Change-Id: I74f0460f6b14fde2b4bd6391e1782b2e5b217707 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M Makefile M src/cpu/intel/car/romstage.c M src/include/adainit.h M src/lib/Kconfig M src/lib/Makefile.inc M src/lib/gnat/Makefile.inc 6 files changed, 48 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/70274/1 diff --git a/Makefile b/Makefile index 58cd85b..d09032d 100644 --- a/Makefile +++ b/Makefile @@ -315,6 +315,9 @@ ifeq ($(CONFIG_RAMSTAGE_ADA),y) ramstage-srcs += $(obj)/ramstage/$(notdir $(KCONFIG_AUTOADS)) endif +ifeq ($(CONFIG_ROMSTAGE_ADA),y) +romstage-srcs += $(obj)/romstage/$(notdir $(KCONFIG_AUTOADS)) +endif # To track dependencies, we need all Ada specification (.ads) files in # *-srcs. Extract / filter all specification files that have a matching diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index c7c218b..7df512d 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <adainit.h> #include <arch/romstage.h> #include <arch/symbols.h> #include <commonlib/helpers.h> @@ -40,6 +41,18 @@ if (CONFIG(VBOOT_EARLY_EC_SYNC)) vboot_sync_ec(); + /* + * We can generally jump between C and Ada code back and forth + * without trouble. But since we don't have an Ada main() we + * have to do some Ada package initializations that GNAT would + * do there. This has to be done before calling any Ada code. + * + * The package initializations should not have any dependen- + * cies on C code. So we can call them here early, and don't + * have to worry at which point we can start to use Ada. + */ + romstage_adainit(); + mainboard_romstage_entry(); /* Check the stack. */ diff --git a/src/include/adainit.h b/src/include/adainit.h index 4953d44..389499e 100644 --- a/src/include/adainit.h +++ b/src/include/adainit.h @@ -21,4 +21,10 @@ static inline void ramstage_adainit(void) {} #endif +#if CONFIG(ROMSTAGE_ADA) +void romstage_adainit(void); +#else +static inline void romstage_adainit(void) {} +#endif + #endif /* _ADAINIT_H */ diff --git a/src/lib/Kconfig b/src/lib/Kconfig index ae96fc6..96181c9 100644 --- a/src/lib/Kconfig +++ b/src/lib/Kconfig @@ -10,6 +10,11 @@ help Selected by features that use Ada code in ramstage. +config ROMSTAGE_ADA + bool + help + Selected by features that use Ada code in romstage. + config RAMSTAGE_LIBHWBASE bool select RAMSTAGE_ADA diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 1c7bc22..600c6dc 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -340,6 +340,7 @@ $(RMODTOOL) -i $< -o $@ ramstage-$(CONFIG_RAMSTAGE_ADA) += cb.ads +romstage-$(CONFIG_ROMSTAGE_ADA) += cb.ads ifeq ($(CONFIG_RAMSTAGE_LIBHWBASE),y) diff --git a/src/lib/gnat/Makefile.inc b/src/lib/gnat/Makefile.inc index 065ba71..0dd642d 100644 --- a/src/lib/gnat/Makefile.inc +++ b/src/lib/gnat/Makefile.inc @@ -54,3 +54,6 @@ ifeq ($(CONFIG_RAMSTAGE_ADA),y) ramstage-libs += $(obj)/libgnat-$(ARCH-ramstage-y)/libgnat.a endif +ifeq ($(CONFIG_ROMSTAGE_ADA),y) +romstage-libs += $(obj)/libgnat-$(ARCH-romstage-y)/libgnat.a +endif -- To view, visit https://review.coreboot.org/c/coreboot/+/70274 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74f0460f6b14fde2b4bd6391e1782b2e5b217707 Gerrit-Change-Number: 70274 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: newchange

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2022