coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: soc/mediatek/mt8188: Fix AP hang when enabling cpufreq-hw driver
by Liju-Clr Chen (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Paul Menzel, Yu-Ping Wu. Liju-Clr Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69088 ) Change subject: soc/mediatek/mt8188: Fix AP hang when enabling cpufreq-hw driver ...................................................................... Patch Set 12: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69088/comment/725161d7_21b89e1f PS11, Line 10: Side-band > side-band Done -- To view, visit https://review.coreboot.org/c/coreboot/+/69088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67b08c38a31a7eae1bc59543a5148a78b61456d6 Gerrit-Change-Number: 69088 Gerrit-PatchSet: 12 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 03 Nov 2022 06:22:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: nb/intel/i945/raminit.c: Try and read whole SPD if DEBUG_RAM_SETUP.
by build bot (Jenkins) (Code Review) 03 Nov '22

03 Nov '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69157 ) Change subject: nb/intel/i945/raminit.c: Try and read whole SPD if DEBUG_RAM_SETUP. ...................................................................... Patch Set 1: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162257): https://review.coreboot.org/c/coreboot/+/69157/comment/529626d9_2571ef65 PS1, Line 6: Subject line should not end with a period. -- To view, visit https://review.coreboot.org/c/coreboot/+/69157 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I770ea9987ea9f616a32ea907bee9a153f4ff133d Gerrit-Change-Number: 69157 Gerrit-PatchSet: 1 Gerrit-Owner: Roc Vallès i Domènech Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 03 Nov 2022 06:22:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/mediatek/mt8188: Disable input-gating for big-core SRAM
by Liju-Clr Chen (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Hung-Te Lin, Liju-Clr Chen. Hello Hung-Te Lin, build bot (Jenkins), Rex-BC Chen, Angel Pons, Yidi Lin, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69089 to look at the new patch set (#12). Change subject: soc/mediatek/mt8188: Disable input-gating for big-core SRAM ...................................................................... soc/mediatek/mt8188: Disable input-gating for big-core SRAM The input-gating is an experimental feature (but unfortunately default enabled) and would lead to crash on MT8188, so we have to disable it in the firmware stage. BUG=b:233720142 TEST=CPUfreq in kernel test pass. Change-Id: Ifd68fe9362587955cdb8598c4cc5c2d0eefe53ca Signed-off-by: Liju-Clr Chen <liju-clr.chen(a)mediatek.com> --- M src/soc/mediatek/mt8188/Makefile.inc A src/soc/mediatek/mt8188/cpu_input_gating.c A src/soc/mediatek/mt8188/include/soc/cpu_input_gating.h M src/soc/mediatek/mt8188/soc.c 4 files changed, 45 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/69089/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/69089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd68fe9362587955cdb8598c4cc5c2d0eefe53ca Gerrit-Change-Number: 69089 Gerrit-PatchSet: 12 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/mediatek/mt8188: Fix AP hang when enabling cpufreq-hw driver
by Liju-Clr Chen (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Hung-Te Lin, Liju-Clr Chen, Paul Menzel, Yu-Ping Wu. Hello Hung-Te Lin, build bot (Jenkins), Rex-BC Chen, Angel Pons, Yidi Lin, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69088 to look at the new patch set (#12). Change subject: soc/mediatek/mt8188: Fix AP hang when enabling cpufreq-hw driver ...................................................................... soc/mediatek/mt8188: Fix AP hang when enabling cpufreq-hw driver When enabling cpufreq-hw driver, it is required for MCUPM to access secure registers. Therefore, we enable side-band to allow MCUPM to access the secure registers. BUG=b:236331463 TEST=It works well after boot to login shell. Change-Id: I67b08c38a31a7eae1bc59543a5148a78b61456d6 Signed-off-by: Liju-Clr Chen <liju-clr.chen(a)mediatek.com> --- M src/soc/mediatek/mt8188/devapc.c M src/soc/mediatek/mt8188/include/soc/devapc.h 2 files changed, 23 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/69088/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/69088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67b08c38a31a7eae1bc59543a5148a78b61456d6 Gerrit-Change-Number: 69088 Gerrit-PatchSet: 12 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: nb/intel/i945/raminit.c: Try and read whole SPD if DEBUG_RAM_SETUP.
by Roc Vallès i Domènech (Code Review) 03 Nov '22

03 Nov '22

Roc Vallès i Domènech has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69157 ) Change subject: nb/intel/i945/raminit.c: Try and read whole SPD if DEBUG_RAM_SETUP. ...................................................................... nb/intel/i945/raminit.c: Try and read whole SPD if DEBUG_RAM_SETUP. If DEBUG_RAM_SETUP is set, dram_print_spd_ddr2() will be called. This will printk fields of the SPD which are above the checksum. Unless these are read, gibberish will be printed. Thus, we make a modest attempt to read the rest of the SPD. Change-Id: I770ea9987ea9f616a32ea907bee9a153f4ff133d Signed-off-by: Roc Vallès Domènech <vallesroc(a)gmail.com> --- M src/northbridge/intel/i945/raminit.c 1 file changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/69157/1 diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 2613b81..ada4abe 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -358,6 +358,19 @@ hexdump(raw_spd, 64); } + /* + * With DEBUG_RAM_SETUP, spd_decode_ddr2() will print fields + * that are above the first 64 bytes. + */ + if (CONFIG(DEBUG_RAM_SETUP) && raw_spd[0] > 64) { + bytes_read = i2c_eeprom_read(device, 64, + raw_spd[0] <= SPD_SIZE_MAX_DDR2 ? raw_spd[0]-64 + : SPD_SIZE_MAX_DDR2-64, &raw_spd[64]); + if (bytes_read < raw_spd[0]-64) { + printk(BIOS_WARNING, "SPD could not be read entirely " + "past checksum.\n"); + } + } if (spd_decode_ddr2(&dimm_info, raw_spd) != SPD_STATUS_OK) { printk(BIOS_WARNING, "Encountered problems with SPD, " "skipping this DIMM.\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/69157 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I770ea9987ea9f616a32ea907bee9a153f4ff133d Gerrit-Change-Number: 69157 Gerrit-PatchSet: 1 Gerrit-Owner: Roc Vallès i Domènech Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: util/eventlog: Correct the capitalization for diagnostics types
by 9elements QA (Code Review) 03 Nov '22

03 Nov '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69025 ) Change subject: util/eventlog: Correct the capitalization for diagnostics types ...................................................................... Patch Set 3: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/133016 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/133015 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/133014 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/133013 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/133012 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/133011 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/133010 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/133009 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/133008 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/133007 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/133006 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/133005 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/133004 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/133003 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/133002 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/133001 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/69025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6c1df9e8d2ee6f8ae11b962e76b52f3c6663c42 Gerrit-Change-Number: 69025 Gerrit-PatchSet: 3 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Nov 2022 06:16:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/xeon_sp: Don't sort struct device cpus for numa
by Shuming Chu (Shuming) (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Arthur Heymans, Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Christian Walter, Angel Pons, TangYiwei. Shuming Chu (Shuming) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68912 ) Change subject: soc/intel/xeon_sp: Don't sort struct device cpus for numa ...................................................................... Patch Set 4: (7 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/68912/comment/b5255799_3ec0981a PS3, Line 9: reassign > reassign*s* Done https://review.coreboot.org/c/coreboot/+/68912/comment/f513a9d1_01ce15f6 PS3, Line 12: break > break*s* Done https://review.coreboot.org/c/coreboot/+/68912/comment/9672c376_cf06bd79 PS3, Line 15: This moves the sorting to of the lapic_ids to the srat table generation > Yes, the `to` is spurious Done File src/soc/intel/xeon_sp/cpx/cpu.c: https://review.coreboot.org/c/coreboot/+/68912/comment/c90902e6_10320c8a PS3, Line 81: apic_id > Should be package_id I don't see any place update package_id and the bottom layer uses apic_id to get package information so I suppose keep using apic_id? File src/soc/intel/xeon_sp/include/soc/util.h: https://review.coreboot.org/c/coreboot/+/68912/comment/92216128_9c7d5308 PS3, Line 15: uint8_t get_cpu_package(const uint32_t apic_id); > Should we name it get_cpu_socket()? This function uses apic_id to get package information and the bottom layer uses the name "package", maybe keep the name here? File src/soc/intel/xeon_sp/nb_acpi.c: https://review.coreboot.org/c/coreboot/+/68912/comment/705f46aa_613a108b PS3, Line 41: if (num_cpus > 1) > We don't need these checks, bubblesort bails out early if there's less than 2 elements to sort. Remove the checker. File src/soc/intel/xeon_sp/util.c: https://review.coreboot.org/c/coreboot/+/68912/comment/70666811_47c8415d PS3, Line 161: uint8_t get_cpu_package(const uint32_t apic_id) > Could we add some comments here? Such as what it means by a "package" in this context? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/68912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I372bcea1932d28e9bf712cc712f19a76fe3199b1 Gerrit-Change-Number: 68912 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: TangYiwei Gerrit-Comment-Date: Thu, 03 Nov 2022 06:10:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur.heymans(a)9elements.com> Comment-In-Reply-To: Jonathan Zhang <jonzhang(a)fb.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/nissa/var/craask: Add wifi sar table
by Tyler Wang (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Kangheui Won, Tim Wawrzynczak, Reka Norman, Nick Vaccaro. Tyler Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68660 ) Change subject: mb/google/nissa/var/craask: Add wifi sar table ...................................................................... Patch Set 6: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/68660 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c92f0ab53ece12a97068f09241e5298909116aa Gerrit-Change-Number: 68660 Gerrit-PatchSet: 6 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cathy Chen <cathy_chen(a)quanta.corp-partner.google.com> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Thu, 03 Nov 2022 06:01:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brask
by Will Tsai (Code Review) 03 Nov '22

03 Nov '22

Will Tsai has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/69156 ) Change subject: mb/google/brask ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/69156 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5956df38cf17ff05d469988daf74943a5b94f1c Gerrit-Change-Number: 69156 Gerrit-PatchSet: 1 Gerrit-Owner: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-MessageType: abandon

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[S] Change in coreboot[master]: mb/google/brask
by Will Tsai (Code Review) 03 Nov '22

03 Nov '22

Will Tsai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69156 ) Change subject: mb/google/brask ...................................................................... mb/google/brask test Signed-off-by: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Change-Id: Ic5956df38cf17ff05d469988daf74943a5b94f1c --- M src/mainboard/google/brya/variants/kuldax/ramstage.c 1 file changed, 13 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/69156/1 diff --git a/src/mainboard/google/brya/variants/kuldax/ramstage.c b/src/mainboard/google/brya/variants/kuldax/ramstage.c index 4bec1d4..fc22c4a 100644 --- a/src/mainboard/google/brya/variants/kuldax/ramstage.c +++ b/src/mainboard/google/brya/variants/kuldax/ramstage.c @@ -20,7 +20,7 @@ const struct system_power_limits sys_limits[] = { /* SKU_ID, TDP (Watts), psys_pl2 (Watts) */ - { PCI_DID_INTEL_ADL_P_ID_10, 15, 65 }, + { PCI_DID_INTEL_ADL_P_ID_10, 15, 333 }, { PCI_DID_INTEL_ADL_P_ID_7, 15, 150 }, { PCI_DID_INTEL_ADL_P_ID_6, 15, 150 }, { PCI_DID_INTEL_ADL_P_ID_5, 28, 150 }, -- To view, visit https://review.coreboot.org/c/coreboot/+/69156 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5956df38cf17ff05d469988daf74943a5b94f1c Gerrit-Change-Number: 69156 Gerrit-PatchSet: 1 Gerrit-Owner: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2022