coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: soc/mediatek/mt8188: Disable input-gating for big-core SRAM
by Yu-Ping Wu (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Hung-Te Lin, Liju-Clr Chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69089 ) Change subject: soc/mediatek/mt8188: Disable input-gating for big-core SRAM ...................................................................... Patch Set 12: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd68fe9362587955cdb8598c4cc5c2d0eefe53ca Gerrit-Change-Number: 69089 Gerrit-PatchSet: 12 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Thu, 03 Nov 2022 06:40:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/mediatek/mt8188: Fix AP hang when enabling cpufreq-hw driver
by Yu-Ping Wu (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Hung-Te Lin, Liju-Clr Chen, Rex-BC Chen, Paul Menzel. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69088 ) Change subject: soc/mediatek/mt8188: Fix AP hang when enabling cpufreq-hw driver ...................................................................... Patch Set 12: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67b08c38a31a7eae1bc59543a5148a78b61456d6 Gerrit-Change-Number: 69088 Gerrit-PatchSet: 12 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 03 Nov 2022 06:40:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/cmn: Clear interrupt status after HECI-1 has been received
by Sridhar Siricilla (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Arthur Heymans, Marc Jones, Wonkyu Kim, Subrata Banik, Jonathan Zhang, Johnny Lin, Daocheng Bu, Rizwan Qureshi, Jingle Hsu, Shuming Chu (Shuming), Shelly Chang. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66579 ) Change subject: soc/intel/cmn: Clear interrupt status after HECI-1 has been received ...................................................................... Patch Set 4: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/66579/comment/b5d5c56a_b65b80a5 PS4, Line 15: get_me_fw_version > My test result: […] Thanks Lin for test results, it is clear the code clears the interrupt too early in your platform. Since coreboot code works in poll mode and communication between Host & CSE is request/response model, and clearing interrupt status again, I don't see any side effects. The change seems to be fine to me. -- To view, visit https://review.coreboot.org/c/coreboot/+/66579 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cf21112870e53a11134d43e461b735ead239717 Gerrit-Change-Number: 66579 Gerrit-PatchSet: 4 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Daocheng Bu <daocheng.bu(a)intel.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Reviewer: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Daocheng Bu <daocheng.bu(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Comment-Date: Thu, 03 Nov 2022 06:39:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Johnny Lin <Johnny_Lin(a)wiwynn.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel: Include <cpu/cpu.h> instead of <arch/cpu.h>
by Werner Zeh (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Tarun Tuli, Kapil Porwal, Lean Sheng Tan, Elyes Haouas. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69032 ) Change subject: soc/intel: Include <cpu/cpu.h> instead of <arch/cpu.h> ...................................................................... Patch Set 1: Code-Review+1 (3 comments) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/69032/comment/1025f2e0_2e9393a6 PS1, Line 11: #include <intelblocks/cse_layout.h> : #include <intelblocks/cse.h> nit: I would leave this two ion their original order, looks somehow weird this way...But up to you. File src/soc/intel/elkhartlake/bootblock/report_platform.c: https://review.coreboot.org/c/coreboot/+/69032/comment/27d92ac4_5aefb5fd PS1, Line 11: #include <device/pci.h> Same order comment applies here. File src/soc/intel/icelake/bootblock/report_platform.c: https://review.coreboot.org/c/coreboot/+/69032/comment/b6ff2f94_e58087d0 PS1, Line 10: #include <device/pci.h> And here as well as in other files re-ordering PCI includes. -- To view, visit https://review.coreboot.org/c/coreboot/+/69032 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7da9c672ee230dfaebd943247639b78d675957e4 Gerrit-Change-Number: 69032 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 03 Nov 2022 06:29:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/cmn: Clear interrupt status after HECI-1 has been received
by Johnny Lin (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Arthur Heymans, Marc Jones, Wonkyu Kim, Subrata Banik, Jonathan Zhang, Daocheng Bu, Rizwan Qureshi, Jingle Hsu, Sridhar Siricilla, Shuming Chu (Shuming), Shelly Chang. Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66579 ) Change subject: soc/intel/cmn: Clear interrupt status after HECI-1 has been received ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/66579/comment/8fe0be4c_749ab08a PS4, Line 15: get_me_fw_version > Thanks Johnny for clarification. […] My test result: The interrupt status is not set before and after line 542 clear_int(); The interrupt status is set right before line 572 return CSE_TX_RX_SUCCESS; File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/66579/comment/95163074_cb99689d PS4, Line 542: clear_int(); > Is this too early in your platform? Can you check interrupt status before this code clears? Yes it's too early. -- To view, visit https://review.coreboot.org/c/coreboot/+/66579 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cf21112870e53a11134d43e461b735ead239717 Gerrit-Change-Number: 66579 Gerrit-PatchSet: 4 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Daocheng Bu <daocheng.bu(a)intel.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Reviewer: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Daocheng Bu <daocheng.bu(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Comment-Date: Thu, 03 Nov 2022 06:28:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Johnny Lin <Johnny_Lin(a)wiwynn.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/mediatek/mt8188: Disable input-gating for big-core SRAM
by Yidi Lin (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Hung-Te Lin, Liju-Clr Chen, Yu-Ping Wu. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69089 ) Change subject: soc/mediatek/mt8188: Disable input-gating for big-core SRAM ...................................................................... Patch Set 12: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/69089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd68fe9362587955cdb8598c4cc5c2d0eefe53ca Gerrit-Change-Number: 69089 Gerrit-PatchSet: 12 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 03 Nov 2022 06:27:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: [Test] Disable BT offload
by Tyler Wang (Code Review) 03 Nov '22

03 Nov '22

Tyler Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69158 ) Change subject: [Test] Disable BT offload ...................................................................... [Test] Disable BT offload Change-Id: I17248add2d25f653c93ea8181510bf0354c73f55 --- M src/mainboard/google/brya/variants/craask/gpio.c M src/mainboard/google/brya/variants/craask/overridetree.cb 2 files changed, 9 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/69158/1 diff --git a/src/mainboard/google/brya/variants/craask/gpio.c b/src/mainboard/google/brya/variants/craask/gpio.c index f075ba0..00d1885 100644 --- a/src/mainboard/google/brya/variants/craask/gpio.c +++ b/src/mainboard/google/brya/variants/craask/gpio.c @@ -21,24 +21,6 @@ PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE), /* H23 : WWAN_SAR_DETECT_ODL */ PAD_CFG_GPO(GPP_H23, 1, DEEP), - - /* Configure the virtual CNVi Bluetooth I2S GPIO pads */ - /* BT_I2S_BCLK */ - PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), - /* BT_I2S_SYNC */ - PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3), - /* BT_I2S_SDO */ - PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3), - /* BT_I2S_SDI */ - PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3), - /* SSP2_SCLK */ - PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), - /* SSP2_SFRM */ - PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), - /* SSP_TXD */ - PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), - /* SSP_RXD */ - PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), }; /* Early pad configuration in bootblock */ diff --git a/src/mainboard/google/brya/variants/craask/overridetree.cb b/src/mainboard/google/brya/variants/craask/overridetree.cb index c77787f..8643bc4 100644 --- a/src/mainboard/google/brya/variants/craask/overridetree.cb +++ b/src/mainboard/google/brya/variants/craask/overridetree.cb @@ -103,9 +103,6 @@ .vnn_icc_max_ma = 500, }" - # Enable the Cnvi BT Audio Offload - register "cnvi_bt_audio_offload" = "1" - register "power_limits_config[ADL_N_041_6W_CORE]" = "{ .tdp_pl1_override = 6, .tdp_pl2_override = 12, -- To view, visit https://review.coreboot.org/c/coreboot/+/69158 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17248add2d25f653c93ea8181510bf0354c73f55 Gerrit-Change-Number: 69158 Gerrit-PatchSet: 1 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/mediatek/mt8188: Fix AP hang when enabling cpufreq-hw driver
by Yidi Lin (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Hung-Te Lin, Liju-Clr Chen, Rex-BC Chen, Paul Menzel, Yu-Ping Wu. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69088 ) Change subject: soc/mediatek/mt8188: Fix AP hang when enabling cpufreq-hw driver ...................................................................... Patch Set 12: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/69088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67b08c38a31a7eae1bc59543a5148a78b61456d6 Gerrit-Change-Number: 69088 Gerrit-PatchSet: 12 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 03 Nov 2022 06:26:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: nb/intel/i945/raminit.c: Try and read whole SPD if DEBUG_RAM_SETUP
by Roc Vallès i Domènech (Code Review) 03 Nov '22

03 Nov '22

Roc Vallès i Domènech has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/69157 ) Change subject: nb/intel/i945/raminit.c: Try and read whole SPD if DEBUG_RAM_SETUP ...................................................................... nb/intel/i945/raminit.c: Try and read whole SPD if DEBUG_RAM_SETUP If DEBUG_RAM_SETUP is set, dram_print_spd_ddr2() will be called. This will printk fields of the SPD which are above the checksum. Unless these are read, gibberish will be printed. Thus, we make a modest attempt to read the rest of the SPD. Change-Id: I770ea9987ea9f616a32ea907bee9a153f4ff133d Signed-off-by: Roc Vallès Domènech <vallesroc(a)gmail.com> --- M src/northbridge/intel/i945/raminit.c 1 file changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/69157/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69157 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I770ea9987ea9f616a32ea907bee9a153f4ff133d Gerrit-Change-Number: 69157 Gerrit-PatchSet: 2 Gerrit-Owner: Roc Vallès i Domènech Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/mediatek/mt8188: Disable input-gating for big-core SRAM
by Liju-Clr Chen (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Liju-Clr Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69089 ) Change subject: soc/mediatek/mt8188: Disable input-gating for big-core SRAM ...................................................................... Patch Set 12: (1 comment) File src/soc/mediatek/mt8188/include/soc/cpu_input_gating.h: https://review.coreboot.org/c/coreboot/+/69089/comment/f7859c9a_177c998b PS11, Line 6: inputgating > also here Done -- To view, visit https://review.coreboot.org/c/coreboot/+/69089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd68fe9362587955cdb8598c4cc5c2d0eefe53ca Gerrit-Change-Number: 69089 Gerrit-PatchSet: 12 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 03 Nov 2022 06:23:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit November 2022