coreboot-gerrit November 2022

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[S] Change in coreboot[master]: src/cpu: Remove unnecessary space after casts
by Elyes Haouas (Code Review) 18 Nov '22

18 Nov '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69801 ) Change subject: src/cpu: Remove unnecessary space after casts ...................................................................... src/cpu: Remove unnecessary space after casts Change-Id: I12463d4d26c03c85fa018b421bb9166fbfeb0b60 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/cpu/intel/car/romstage.c 1 file changed, 11 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/69801/1 diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 4c68ded..c7c218b 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -32,7 +32,7 @@ printk(BIOS_DEBUG, "Romstage stack size limited to 0x%x!\n", size); - stack_base = (u32 *) (_ecar_stack - size); + stack_base = (u32 *)(_ecar_stack - size); for (i = 0; i < num_guards; i++) stack_base[i] = stack_guard; -- To view, visit https://review.coreboot.org/c/coreboot/+/69801 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12463d4d26c03c85fa018b421bb9166fbfeb0b60 Gerrit-Change-Number: 69801 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: security: Remove unnecessary space after casts
by Elyes Haouas (Code Review) 18 Nov '22

18 Nov '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69800 ) Change subject: security: Remove unnecessary space after casts ...................................................................... security: Remove unnecessary space after casts Change-Id: Ibd41382d0e0ef58498ac925dc9e10b54a76a798a Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/security/intel/stm/StmPlatformSmm.c M src/security/tpm/tss/tcg-1.2/tss.c M src/security/tpm/tss/tcg-1.2/tss_structures.h M src/security/vboot/vbnv.c 4 files changed, 22 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/69800/1 diff --git a/src/security/intel/stm/StmPlatformSmm.c b/src/security/intel/stm/StmPlatformSmm.c index bcf935c..e5b3cf1 100644 --- a/src/security/intel/stm/StmPlatformSmm.c +++ b/src/security/intel/stm/StmPlatformSmm.c @@ -85,7 +85,7 @@ TXT_PROCESSOR_SMM_DESCRIPTOR *psd; - smbase_processor = (void *) SMM_DEFAULT_BASE;//we are here + smbase_processor = (void *)SMM_DEFAULT_BASE;//we are here psd = smbase + SMM_PSD_OFFSET; printk(BIOS_DEBUG, @@ -121,8 +121,8 @@ read_gdtr(&gdtr); - gdtr.base -= (uintptr_t) smbase_processor; - gdtr.base += (uintptr_t) smbase; + gdtr.base -= (uintptr_t)smbase_processor; + gdtr.base += (uintptr_t)smbase; psd->smm_gdt_ptr = gdtr.base; psd->smm_gdt_size = gdtr.limit + 1; // the stm will subtract, so add @@ -159,7 +159,7 @@ // some processor to receive a bad value // calculate the location in SMRAM addr_calc = mseg - CONFIG_BIOS_RESOURCE_LIST_SIZE; - stm_resource_heap = (uint8_t *) addr_calc; + stm_resource_heap = (uint8_t *)addr_calc; if (cpu == 0) { diff --git a/src/security/tpm/tss/tcg-1.2/tss.c b/src/security/tpm/tss/tcg-1.2/tss.c index 6b79aab..39c44ec 100644 --- a/src/security/tpm/tss/tcg-1.2/tss.c +++ b/src/security/tpm/tss/tcg-1.2/tss.c @@ -51,7 +51,7 @@ { uint32_t size; from_tpm_uint32(buffer + sizeof(uint16_t), &size); - return (int) size; + return (int)size; } /* Gets the code field of a TPM command. */ diff --git a/src/security/tpm/tss/tcg-1.2/tss_structures.h b/src/security/tpm/tss/tcg-1.2/tss_structures.h index 4a976c8..689bb4b 100644 --- a/src/security/tpm/tss/tcg-1.2/tss_structures.h +++ b/src/security/tpm/tss/tcg-1.2/tss_structures.h @@ -21,13 +21,13 @@ #define TPM_NV_PER_READ_STCLEAR (((uint32_t)1)<<31) #define TPM_NV_PER_WRITE_STCLEAR (((uint32_t)1)<<14) -#define TPM_TAG_RQU_COMMAND ((uint16_t) 0xc1) -#define TPM_TAG_RQU_AUTH1_COMMAND ((uint16_t) 0xc2) -#define TPM_TAG_RQU_AUTH2_COMMAND ((uint16_t) 0xc3) +#define TPM_TAG_RQU_COMMAND ((uint16_t)0xc1) +#define TPM_TAG_RQU_AUTH1_COMMAND ((uint16_t)0xc2) +#define TPM_TAG_RQU_AUTH2_COMMAND ((uint16_t)0xc3) -#define TPM_TAG_RSP_COMMAND ((uint16_t) 0xc4) -#define TPM_TAG_RSP_AUTH1_COMMAND ((uint16_t) 0xc5) -#define TPM_TAG_RSP_AUTH2_COMMAND ((uint16_t) 0xc6) +#define TPM_TAG_RSP_COMMAND ((uint16_t)0xc4) +#define TPM_TAG_RSP_AUTH1_COMMAND ((uint16_t)0xc5) +#define TPM_TAG_RSP_AUTH2_COMMAND ((uint16_t)0xc6) typedef uint8_t TSS_BOOL; typedef uint16_t TPM_STRUCTURE_TAG; diff --git a/src/security/vboot/vbnv.c b/src/security/vboot/vbnv.c index 26946fd..e9223c0 100644 --- a/src/security/vboot/vbnv.c +++ b/src/security/vboot/vbnv.c @@ -24,7 +24,7 @@ } } - return (uint8_t) (crc >> 8); + return (uint8_t)(crc >> 8); } void vbnv_reset(uint8_t *vbnv_copy) -- To view, visit https://review.coreboot.org/c/coreboot/+/69800 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd41382d0e0ef58498ac925dc9e10b54a76a798a Gerrit-Change-Number: 69800 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/alderlake/include/soc/ufs.h: Remove PWRM size redefinition
by Michał Żygowski (Code Review) 18 Nov '22

18 Nov '22

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69799 ) Change subject: soc/intel/alderlake/include/soc/ufs.h: Remove PWRM size redefinition ...................................................................... soc/intel/alderlake/include/soc/ufs.h: Remove PWRM size redefinition The change CB:68251 introduced redefinition of PCH_PWRM_BASE_SIZE. PCH_PWRM_BASE_SIZE is already defined in soc/iomap.h and does not need to be defined in soc/ufs.h again just for the UFS ACPI source in src/soc/intel/common/block/acpi/acpi/ufs.asl. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I0997ee8bcc406cac14e0837f3fe2e0a3499c7611 --- M src/soc/intel/alderlake/include/soc/ufs.h 1 file changed, 16 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/69799/1 diff --git a/src/soc/intel/alderlake/include/soc/ufs.h b/src/soc/intel/alderlake/include/soc/ufs.h index e3a98f2..604f48f 100644 --- a/src/soc/intel/alderlake/include/soc/ufs.h +++ b/src/soc/intel/alderlake/include/soc/ufs.h @@ -24,5 +24,5 @@ #define R_SCS_PCR_1078 0x1078 #define R_PMC_PWRM_LTR_IGN 0x1b0c -#define PCH_PWRM_BASE_SIZE 0x1e30 + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/69799 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0997ee8bcc406cac14e0837f3fe2e0a3499c7611 Gerrit-Change-Number: 69799 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mainboard/msi/ms7d25/vboot-rwab.fmd: Add HSPHY cache region
by build bot (Jenkins) (Code Review) 18 Nov '22

18 Nov '22

Attention is currently required from: Michał Kopeć. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68988 ) Change subject: mainboard/msi/ms7d25/vboot-rwab.fmd: Add HSPHY cache region ...................................................................... Patch Set 2: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/68988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4793fc9457f58e914ef3e18cce1294f230462bd Gerrit-Change-Number: 68988 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Fri, 18 Nov 2022 14:00:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: soc/intel/common/block/oc_wdt: Add OC watchdog common block
by build bot (Jenkins) (Code Review) 18 Nov '22

18 Nov '22

Attention is currently required from: Michał Żygowski, Michał Kopeć. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68944 ) Change subject: soc/intel/common/block/oc_wdt: Add OC watchdog common block ...................................................................... Patch Set 3: (5 comments) File src/soc/intel/common/block/oc_wdt/oc_wdt.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164017): https://review.coreboot.org/c/coreboot/+/68944/comment/2bb77856_b76885fd PS3, Line 66: readback = inl(PCH_OC_WDT_CTL); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164017): https://review.coreboot.org/c/coreboot/+/68944/comment/06ae8ae9_6fc2ba50 PS3, Line 66: readback = inl(PCH_OC_WDT_CTL); please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164017): https://review.coreboot.org/c/coreboot/+/68944/comment/b9da85a6_2dfaec7b PS3, Line 66: readback = inl(PCH_OC_WDT_CTL); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164017): https://review.coreboot.org/c/coreboot/+/68944/comment/e9803e38_940b2821 PS3, Line 81: printk (BIOS_ERR, "Watchdog: Failure detected\n"); space prohibited between function name and open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164017): https://review.coreboot.org/c/coreboot/+/68944/comment/f6b2b847_dcf532ad PS3, Line 192: printk (BIOS_ERR, "Watchdog: timer expiration detected.\n"); space prohibited between function name and open parenthesis '(' -- To view, visit https://review.coreboot.org/c/coreboot/+/68944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib494aa0c7581351abca8b496fc5895b2c7cbc5bc Gerrit-Change-Number: 68944 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Fri, 18 Nov 2022 13:58:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: [WIP] mb/prodrive/atlas: Populate smbios table with VPD from ECs EMI
by David Milosevic (Code Review) 18 Nov '22

18 Nov '22

Attention is currently required from: Maximilian Brune, Angel Pons, Arthur Heymans, Lean Sheng Tan. David Milosevic has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68137 ) Change subject: [WIP] mb/prodrive/atlas: Populate smbios table with VPD from ECs EMI ...................................................................... Patch Set 11: (5 comments) File src/mainboard/prodrive/atlas/emi.c: https://review.coreboot.org/c/coreboot/+/68137/comment/741de193_1ece74e3 PS11, Line 59: u8 bytes[4] = { 0 }; > use u32. Using a byte-literal here makes more sense. I need to read single bytes (in case n mod 4 != 0) and store them one by one into the user buffer. If I would use a u32 here, I would also need to shift the bytes out of it. https://review.coreboot.org/c/coreboot/+/68137/comment/5f0caadc_eedcd833 PS11, Line 71: buff[idx++] = bytes[i]; > Use memcpy I need to store the bytes one by one and stop as soon as the desired reading length is reached, since EMI only allows 4-byte aligned read access. Using memcpy for just one byte does not make much sense. https://review.coreboot.org/c/coreboot/+/68137/comment/ec5ff8ce_5f3a16ea PS11, Line 68: if (idx == n) : return; : : buff[idx++] > Can you put those conditions in the for loop? That makes it easier to read. I could do that but then we would need the same branch right after the for-loop in order to determine which condition led to exiting the loop (i greater/equals to 4 or idx equals to n). This would only duplicate the checks. Your proposal would look like this for(u8 i = 0; i < 4 && idx != n; i++) buff[idx++] = bytes[i]; // same check if(idx == n) return; File src/mainboard/prodrive/atlas/vpd.h: https://review.coreboot.org/c/coreboot/+/68137/comment/ca085be6_14bde4fa PS11, Line 13: __packed > __packed is a NOOP needed here. Yep, I can remove that. File src/mainboard/prodrive/atlas/vpd.c: https://review.coreboot.org/c/coreboot/+/68137/comment/97516e15_1e1cf01b PS11, Line 36: PN_LENGTH > Do you need this in the read_region code? reading 4byte aligned data and dealing with it later is pr […] This is not the read_region code. vpd_get() uses emi_read_region() to read PN_LENGTH bytes from the EMI region since emi_read_region() is designed to work with arbitrary lengths and not only a multiple of 4-bytes. vpd.c in general is responsible for returning you a non-null terminated byte sequence that represents your desired VPD. -- To view, visit https://review.coreboot.org/c/coreboot/+/68137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47bb4883c43ff344a9bda92c3106dd025533b391 Gerrit-Change-Number: 68137 Gerrit-PatchSet: 11 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Fri, 18 Nov 2022 13:54:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/alderlake/hsphy: Add possibility to cache HSPHY in flash
by Michał Żygowski (Code Review) 18 Nov '22

18 Nov '22

Attention is currently required from: Tarun Tuli, Martin L Roth, Subrata Banik. Hello build bot (Jenkins), Tarun Tuli, Martin L Roth, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68987 to look at the new patch set (#2). Change subject: soc/intel/alderlake/hsphy: Add possibility to cache HSPHY in flash ...................................................................... soc/intel/alderlake/hsphy: Add possibility to cache HSPHY in flash Tge patch adds a possibility to cache the PCIe 5.0 HSPHY firmware in the SPI flash. New flashmap region is created for that purpose. The goal of caching is to reduce the dependency on CSME and the HECI IP LOAD command which may fail when the CSME is disabled, e.g. soft disabled by HECI command or HAP disabled. This change allows to keep PCIe 5.0 functioning even if CSME/HECI is not functional. TEST=Boot Ubuntu 22.04 on MSI PRO Z690-A and notice PCIe 5.0 port is functional after loading the HSPHY from cache. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I5a37f5b06706ff30d92f60f1bf5dc900edbde96f --- M Makefile.inc M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/alderlake/hsphy.c M util/cbfstool/default-x86.fmd 5 files changed, 223 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/68987/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a37f5b06706ff30d92f60f1bf5dc900edbde96f Gerrit-Change-Number: 68987 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: cpu/intel/socket_*: Clean up Kconfig files
by Elyes Haouas (Code Review) 18 Nov '22

18 Nov '22

Attention is currently required from: Stefan Ott, Nico Huber, Angel Pons, Arthur Heymans, Kyösti Mälkki, Alexander Couzens. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69447 ) Change subject: cpu/intel/socket_*: Clean up Kconfig files ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69447/comment/c566361c_c1d3c267 PS3, Line 10: Move MAX_CPUS to mainboards. > > > Set the max CPUs in socket Kconfig doesn't make sense! […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/69447 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2265ac716e90720e7ccc550239737d40c2f7a0a Gerrit-Change-Number: 69447 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Fri, 18 Nov 2022 13:37:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/common/block/smbus/Kconfig: Drop unused Kconfig symbol
by Elyes Haouas (Code Review) 18 Nov '22

18 Nov '22

Attention is currently required from: Michael Niewöhner. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69331 ) Change subject: soc/intel/common/block/smbus/Kconfig: Drop unused Kconfig symbol ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > it's unused bc CB:44507 is still in review 44507 still active? -- To view, visit https://review.coreboot.org/c/coreboot/+/69331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic46e1663609068439069f666beca17ed76c679f0 Gerrit-Change-Number: 69331 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Fri, 18 Nov 2022 13:28:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/nissa/var/craask: Disable SAR Proximity Sensor GPIO pin
by Tyler Wang (Code Review) 18 Nov '22

18 Nov '22

Attention is currently required from: Tarun Tuli. Tyler Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69790 ) Change subject: mb/google/nissa/var/craask: Disable SAR Proximity Sensor GPIO pin ...................................................................... Patch Set 3: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/69790 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b2a2516890b68036e96d1a542e6a10a098cb6a7 Gerrit-Change-Number: 69790 Gerrit-PatchSet: 3 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cathy Chen <cathy_chen(a)quanta.corp-partner.google.com> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Comment-Date: Fri, 18 Nov 2022 13:26:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2022