coreboot-gerrit November 2022

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[M] Change in coreboot[master]: intelblocks/cse: Add functions to check and change PTT state
by Michał Żygowski (Code Review) 18 Nov '22

18 Nov '22

Attention is currently required from: Michał Żygowski. Hello build bot (Jenkins), Michał Kopeć, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68919 to look at the new patch set (#2). Change subject: intelblocks/cse: Add functions to check and change PTT state ...................................................................... intelblocks/cse: Add functions to check and change PTT state Add functions that allow checking and changing PTT state at runtime. Can be useful for platforms that want to use dTPM instead and have no means to stitch ME firmware binary with disabled PTT. The changing function also checks for the current feature states via HECI to ensure that the feature state will not be changed if not needed. TEST=Successfully switch to dTPM on Comet Lake i5-10210U SoC. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I8426c46eada2d503d6ee72324c5d0025da3f2028 --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 196 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/68919/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8426c46eada2d503d6ee72324c5d0025da3f2028 Gerrit-Change-Number: 68919 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: cbmem_top: Change the return value to uintptr_t
by Jakub Czapiga (Code Review) 18 Nov '22

18 Nov '22

Attention is currently required from: Raul Rangel, Jeff Daly, Jonathan Zhang, Matt DeVillier, Julius Werner, Angel Pons, Arthur Heymans, Andrey Petrov, Lance Zhao, Jason Glenesk, Johnny Lin, Tim Wawrzynczak, Christian Walter, Vanessa Eusebio, Fred Reitberger, Elyes Haouas, Felix Held, Tim Chu. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69163 ) Change subject: cbmem_top: Change the return value to uintptr_t ...................................................................... Patch Set 14: (1 comment) Patchset: PS7: > I do not see what this patch aims to achieve. Casts are removed from platform code, but are introduced in common (src/lib/) code. CB:69078 makes sense to me, but this patch not so much. (Opening for discussion) -- To view, visit https://review.coreboot.org/c/coreboot/+/69163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib757c0548f6f643747ba8d70228b3d6dfa5182cd Gerrit-Change-Number: 69163 Gerrit-PatchSet: 14 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Lance Zhao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 18 Nov 2022 14:19:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: util/chromeos/gen_test_hwid.sh: Replace usage of hexdump
by Michał Żygowski (Code Review) 18 Nov '22

18 Nov '22

Attention is currently required from: Julius Werner. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68133 ) Change subject: util/chromeos/gen_test_hwid.sh: Replace usage of hexdump ...................................................................... Patch Set 1: (1 comment) File util/chromeos/gen_test_hwid.sh: https://review.coreboot.org/c/coreboot/+/68133/comment/492e3b08_65563031 PS1, Line 16: xargs > Yeah but you're passing it into `tail`, why do leading spaces matter? Right... I don't know what I was thinking... Maybe I wanted to keep the old behavior too much. Removed the xargs -- To view, visit https://review.coreboot.org/c/coreboot/+/68133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icad93933335b8c5ebd8fee74cc9aaed36bb56482 Gerrit-Change-Number: 68133 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 18 Nov 2022 14:16:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: util/chromeos/gen_test_hwid.sh: Replace usage of hexdump
by Michał Żygowski (Code Review) 18 Nov '22

18 Nov '22

Attention is currently required from: Michał Żygowski. Hello build bot (Jenkins), Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68133 to look at the new patch set (#2). Change subject: util/chromeos/gen_test_hwid.sh: Replace usage of hexdump ...................................................................... util/chromeos/gen_test_hwid.sh: Replace usage of hexdump Hexdump command is not available in coreboot-sdk. Replace it with equivalent implementation using commands that are present in the container. TEST=Passed "VP46XX" as prefix variable and it produced the same crc32 result before and after the change. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Icad93933335b8c5ebd8fee74cc9aaed36bb56482 --- M util/chromeos/gen_test_hwid.sh 1 file changed, 18 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/68133/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icad93933335b8c5ebd8fee74cc9aaed36bb56482 Gerrit-Change-Number: 68133 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: src/northbridge: Remove unnecessary space after casts
by build bot (Jenkins) (Code Review) 18 Nov '22

18 Nov '22

Attention is currently required from: Angel Pons. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69813 ) Change subject: src/northbridge: Remove unnecessary space after casts ...................................................................... Patch Set 1: (2 comments) File src/northbridge/intel/haswell/report_platform.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164038): https://review.coreboot.org/c/coreboot/+/69813/comment/3658919a_7877a6f9 PS1, Line 25: u32 *p = (u32*)cpu_string; "(foo*)" should be "(foo *)" File src/northbridge/intel/sandybridge/raminit_common.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164038): https://review.coreboot.org/c/coreboot/+/69813/comment/9b93ac1d_b60d7b53 PS1, Line 2825: mchbar_write32(PM_PDWN_CONFIG, get_power_down_mode(ctrl)<< 8 | 64); need consistent spacing around '<<' (ctx:VxW) -- To view, visit https://review.coreboot.org/c/coreboot/+/69813 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6c1a17d15e24ecdc56b0cc9cb7e7dc7d6e6936b Gerrit-Change-Number: 69813 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 18 Nov 2022 14:14:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: src/soc/nvidia: Remove unnecessary space after casts
by build bot (Jenkins) (Code Review) 18 Nov '22

18 Nov '22

Attention is currently required from: Julius Werner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69810 ) Change subject: src/soc/nvidia: Remove unnecessary space after casts ...................................................................... Patch Set 1: (1 comment) File src/soc/nvidia/tegra210/spi.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164035): https://review.coreboot.org/c/coreboot/+/69810/comment/09fe6419_d00e62ab PS1, Line 481: (uintptr_t)& spi->regs->tx_fifo); space prohibited after that '&' (ctx:VxW) -- To view, visit https://review.coreboot.org/c/coreboot/+/69810 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I096e88158027ac22cf93a9450c869807dbc14670 Gerrit-Change-Number: 69810 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 18 Nov 2022 14:13:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: src/superio: Remove unnecessary space after casts
by Elyes Haouas (Code Review) 18 Nov '22

18 Nov '22

Attention is currently required from: Felix Held. Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69814 ) Change subject: src/superio: Remove unnecessary space after casts ...................................................................... src/superio: Remove unnecessary space after casts Change-Id: Iab76316f345fb0cf2ca2a3eaf40f64a1f1b7fc13 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/superio/aspeed/common/aspeed.h M src/superio/fintek/f81803a/fan_control.c 2 files changed, 12 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/69814/1 diff --git a/src/superio/aspeed/common/aspeed.h b/src/superio/aspeed/common/aspeed.h index 3673a71..f41ca0f 100644 --- a/src/superio/aspeed/common/aspeed.h +++ b/src/superio/aspeed/common/aspeed.h @@ -408,7 +408,7 @@ #define ASPEED_EXIT_KEY 0xAA #define TO_BE_UPDATE 0 -#define AndMask32(HighBit, LowBit) ~((((uint32_t) 1 << (HighBit - LowBit + 1)) - 1) << LowBit) +#define AndMask32(HighBit, LowBit) ~((((uint32_t)1 << (HighBit - LowBit + 1)) - 1) << LowBit) typedef enum { GPIOA = 0, diff --git a/src/superio/fintek/f81803a/fan_control.c b/src/superio/fintek/f81803a/fan_control.c index 06a8338..8b5ddac 100644 --- a/src/superio/fintek/f81803a/fan_control.c +++ b/src/superio/fintek/f81803a/fan_control.c @@ -281,7 +281,7 @@ if (value > 100) return message_invalid_2(HWM_STATUS_INVALID_SECTION_VALUE, fan); temp = (255 * value) / 100; - value = (u8) (temp & 0x00ff); + value = (u8)(temp & 0x00ff); write_hwm_reg(base_address, index, value); index++; } -- To view, visit https://review.coreboot.org/c/coreboot/+/69814 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab76316f345fb0cf2ca2a3eaf40f64a1f1b7fc13 Gerrit-Change-Number: 69814 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: src/northbridge: Remove unnecessary space after casts
by Elyes Haouas (Code Review) 18 Nov '22

18 Nov '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69813 ) Change subject: src/northbridge: Remove unnecessary space after casts ...................................................................... src/northbridge: Remove unnecessary space after casts Change-Id: If6c1a17d15e24ecdc56b0cc9cb7e7dc7d6e6936b Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/northbridge/amd/pi/00730F01/acpi_tables.c M src/northbridge/intel/gm45/acpi.c M src/northbridge/intel/haswell/report_platform.c M src/northbridge/intel/i440bx/raminit.c M src/northbridge/intel/ironlake/gma.c M src/northbridge/intel/ironlake/northbridge.c M src/northbridge/intel/ironlake/quickpath.c M src/northbridge/intel/ironlake/raminit.c M src/northbridge/intel/pineview/northbridge.c M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_native.c 12 files changed, 58 insertions(+), 48 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/69813/1 diff --git a/src/northbridge/amd/pi/00730F01/acpi_tables.c b/src/northbridge/amd/pi/00730F01/acpi_tables.c index cf88cfa..4febfaf 100644 --- a/src/northbridge/amd/pi/00730F01/acpi_tables.c +++ b/src/northbridge/amd/pi/00730F01/acpi_tables.c @@ -13,7 +13,7 @@ IO_APIC_ADDR, 0); /* TODO: Remove the hardcode */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS + 1, + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, CONFIG_MAX_CPUS + 1, 0xFEC20000, 24); current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) diff --git a/src/northbridge/intel/gm45/acpi.c b/src/northbridge/intel/gm45/acpi.c index 30d3fed..246fe9a 100644 --- a/src/northbridge/intel/gm45/acpi.c +++ b/src/northbridge/intel/gm45/acpi.c @@ -63,7 +63,7 @@ current = start; printk(BIOS_DEBUG, "ACPI: * DMAR\n"); - dmar = (acpi_dmar_t *) current; + dmar = (acpi_dmar_t *)current; acpi_create_dmar(dmar, 0, acpi_fill_dmar); current += dmar->header.length; current = acpi_align_current(current); diff --git a/src/northbridge/intel/haswell/report_platform.c b/src/northbridge/intel/haswell/report_platform.c index 0b5319b..c989ebf 100644 --- a/src/northbridge/intel/haswell/report_platform.c +++ b/src/northbridge/intel/haswell/report_platform.c @@ -22,7 +22,7 @@ if (cpuidr.eax < 0x80000004) { strcpy(cpu_string, "Platform info not available"); } else { - u32 *p = (u32*) cpu_string; + u32 *p = (u32*)cpu_string; for (i = 2; i <= 4; i++) { cpuidr = cpuid(index + i); *p++ = cpuidr.eax; diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c index 93cbeb9..b3f8780 100644 --- a/src/northbridge/intel/i440bx/raminit.c +++ b/src/northbridge/intel/i440bx/raminit.c @@ -358,7 +358,7 @@ /* Configure the RAM command. */ reg16 = pci_read_config16(NB, SDRAMC); reg16 &= 0xff1f; /* Clear bits 7-5. */ - reg16 |= (u16) (command << 5); /* Write command into bits 7-5. */ + reg16 |= (u16)(command << 5); /* Write command into bits 7-5. */ pci_write_config16(NB, SDRAMC, reg16); /* diff --git a/src/northbridge/intel/ironlake/gma.c b/src/northbridge/intel/ironlake/gma.c index 8084560..a9f16a1 100644 --- a/src/northbridge/intel/ironlake/gma.c +++ b/src/northbridge/intel/ironlake/gma.c @@ -179,8 +179,8 @@ res->flags |= IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_ASSIGNED; pci_write_config32(dev, PCI_BASE_ADDRESS_2, 0xd0000001); pci_write_config32(dev, PCI_BASE_ADDRESS_2 + 4, 0); - res->base = (resource_t) 0xd0000000; - res->size = (resource_t) 0x10000000; + res->base = (resource_t)0xd0000000; + res->size = (resource_t)0x10000000; } static void gma_generate_ssdt(const struct device *device) diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c index 4935ea9..bbd4052 100644 --- a/src/northbridge/intel/ironlake/northbridge.c +++ b/src/northbridge/intel/ironlake/northbridge.c @@ -48,8 +48,8 @@ 0xff800000-0xffffffff ROM. */ resource = new_resource(dev, index++); - resource->base = (resource_t) HPET_BASE_ADDRESS; - resource->size = (resource_t) 0x00100000; + resource->base = (resource_t)HPET_BASE_ADDRESS; + resource->size = (resource_t)0x00100000; resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; diff --git a/src/northbridge/intel/ironlake/quickpath.c b/src/northbridge/intel/ironlake/quickpath.c index 81621d2..56cd14b 100644 --- a/src/northbridge/intel/ironlake/quickpath.c +++ b/src/northbridge/intel/ironlake/quickpath.c @@ -98,9 +98,9 @@ (freq1_reduced - freq2_reduced)) / freq2_reduced; result->freq4_to_2_remainder = -(char)((freq1_reduced - freq2_reduced) + - ((u8) freq4 - + ((u8)freq4 - (freq1_reduced - - freq2_reduced)) % (u8) freq2_reduced); + freq2_reduced)) % (u8)freq2_reduced); } else { if (freq2_reduced > freq1_reduced) { result->freq4_to_max_remainder = @@ -275,11 +275,11 @@ + vv.freq_min_reduced - 1, vv.freq_max_reduced) - 1; u32 y = - (u8) ((vv.freq_max_reduced - vv.freq_min_reduced) + + (u8)((vv.freq_max_reduced - vv.freq_min_reduced) + vv.freq_max_reduced * multiplier) | (vv. - freqs_reversed << 8) | ((u8) (vv.freq_min_reduced * - multiplier) << 16) | ((u8) (vv. + freqs_reversed << 8) | ((u8)(vv.freq_min_reduced * + multiplier) << 16) | ((u8)(vv. freq_min_reduced * multiplier) diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index e3b0b33..e1482be 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -1651,7 +1651,7 @@ u32 curroffset = comp3 * 8 * 60 + 2 * comp1 + 8 * comp2; read128((total_rank << 28) | (curroffset << 3), - (u64 *) re); + (u64 *)re); failxor[0] |= get_etalon2(flip, curroffset) ^ re[0]; failxor[1] |= diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index 7e29db9..151cc01 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -26,8 +26,8 @@ struct resource *resource; resource = new_resource(dev, index++); - resource->base = (resource_t) HPET_BASE_ADDRESS; - resource->size = (resource_t) 0x00100000; + resource->base = (resource_t)HPET_BASE_ADDRESS; + resource->size = (resource_t)0x00100000; resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 90053b4..eda3a65 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -526,7 +526,7 @@ s->pioffset = 1; } else { PRINTK_DEBUG("MCH set to unknown (%02x)\n", - (uint8_t) s->selected_timings.mem_clock & 0xff); + (uint8_t)s->selected_timings.mem_clock & 0xff); } } @@ -723,7 +723,7 @@ if (wl > 2) { flag = 1; } - reg16 = (u8) (wl - 1 - flag); + reg16 = (u8)(wl - 1 - flag); reg16 |= reg16 << 4; reg16 |= flag << 8; mchbar_clrsetbits16(C0WRDATACTRL, 0x1ff, reg16); @@ -794,11 +794,11 @@ reg32 = (2 << 29) | (1 << 28) | (1 << 23); mchbar_clrsetbits32(WRWMCONFIG, 0xffb << 20, reg32); - reg8 = (u8) ((mchbar_read16(C0CYCTRKACT) & 0xe000) >> 13); - reg8 |= (u8) ((mchbar_read16(C0CYCTRKACT + 2) & 1) << 3); + reg8 = (u8)((mchbar_read16(C0CYCTRKACT) & 0xe000) >> 13); + reg8 |= (u8)((mchbar_read16(C0CYCTRKACT + 2) & 1) << 3); mchbar_clrsetbits8(BYPACTSF, 0xf << 4, reg8 << 4); - reg8 = (u8) ((mchbar_read32(C0CYCTRKRD) & 0x000f0000) >> 17); + reg8 = (u8)((mchbar_read32(C0CYCTRKRD) & 0x000f0000) >> 17); mchbar_clrsetbits8(BYPACTSF, 0xf, reg8); /* FIXME: Why not clear everything at once? */ @@ -875,12 +875,12 @@ u32 reg32; /* CTRL0 and CTRL1 */ - reg32 = ((u32) pll->dbsel[f][i]) << 20; - reg32 |= ((u32) pll->dben[f][i]) << 21; - reg32 |= ((u32) pll->dbsel[f][i]) << 22; - reg32 |= ((u32) pll->dben[f][i]) << 23; - reg32 |= ((u32) pll->clkdelay[f][i]) << 24; - reg32 |= ((u32) pll->clkdelay[f][i]) << 27; + reg32 = ((u32)pll->dbsel[f][i]) << 20; + reg32 |= ((u32)pll->dben[f][i]) << 21; + reg32 |= ((u32)pll->dbsel[f][i]) << 22; + reg32 |= ((u32)pll->dben[f][i]) << 23; + reg32 |= ((u32)pll->clkdelay[f][i]) << 24; + reg32 |= ((u32)pll->clkdelay[f][i]) << 27; mchbar_clrsetbits32(C0CTLTX2, 0x01bf0000, reg32); reg8 = pll->pi[f][i]; @@ -888,12 +888,12 @@ mchbar_clrsetbits8(C0TXCTL1DLL, 0x3f, reg8); /* CTRL2 and CTRL3 */ - reg32 = ((u32) pll->dbsel[f][i]) << 12; - reg32 |= ((u32) pll->dben[f][i]) << 13; - reg32 |= ((u32) pll->dbsel[f][i]) << 8; - reg32 |= ((u32) pll->dben[f][i]) << 9; - reg32 |= ((u32) pll->clkdelay[f][i]) << 14; - reg32 |= ((u32) pll->clkdelay[f][i]) << 10; + reg32 = ((u32)pll->dbsel[f][i]) << 12; + reg32 |= ((u32)pll->dben[f][i]) << 13; + reg32 |= ((u32)pll->dbsel[f][i]) << 8; + reg32 |= ((u32)pll->dben[f][i]) << 9; + reg32 |= ((u32)pll->clkdelay[f][i]) << 14; + reg32 |= ((u32)pll->clkdelay[f][i]) << 10; mchbar_clrsetbits32(C0CMDTX2, 0xff << 8, reg32); reg8 = pll->pi[f][i]; @@ -912,12 +912,12 @@ rank = j % 4; dqs = j / 4; - reg32 |= ((u32) pll->dben[f][clk]) << (dqs + 9); - reg32 |= ((u32) pll->dbsel[f][clk]) << dqs; + reg32 |= ((u32)pll->dben[f][clk]) << (dqs + 9); + reg32 |= ((u32)pll->dbsel[f][clk]) << dqs; mchbar_clrsetbits32(C0DQSRyTX1(rank), 1 << (dqs + 9) | 1 << dqs, reg32); - reg32 = ((u32) pll->clkdelay[f][clk]) << ((dqs * 2) + 16); + reg32 = ((u32)pll->clkdelay[f][clk]) << ((dqs * 2) + 16); mchbar_clrsetbits32(C0DQSDQRyTX3(rank), 1 << (dqs * 2 + 17) | 1 << (dqs * 2 + 16), reg32); @@ -936,12 +936,12 @@ rank = j % 4; dq = j / 4; - reg32 |= ((u32) pll->dben[f][clk]) << (dq + 9); - reg32 |= ((u32) pll->dbsel[f][clk]) << dq; + reg32 |= ((u32)pll->dben[f][clk]) << (dq + 9); + reg32 |= ((u32)pll->dbsel[f][clk]) << dq; mchbar_clrsetbits32(C0DQRyTX1(rank), 1 << (dq + 9) | 1 << dq, reg32); - reg32 = ((u32) pll->clkdelay[f][clk]) << (dq*2); + reg32 = ((u32)pll->clkdelay[f][clk]) << (dq*2); mchbar_clrsetbits32(C0DQSDQRyTX3(rank), 1 << (dq * 2 + 1) | 1 << (dq * 2), reg32); reg8 = pll->pi[f][clk]; @@ -1414,8 +1414,8 @@ ; reg32 = mchbar_read32(XCOMP); - rcompp = (u8) ((reg32 & ~(1 << 31)) >> 24); - rcompn = (u8) ((reg32 & ~(0xff800000)) >> 16); + rcompp = (u8)((reg32 & ~(1 << 31)) >> 24); + rcompn = (u8)((reg32 & ~(0xff800000)) >> 16); FOR_EACH_RCOMP_GROUP(i) { srup = (mchbar_read8(C0RCOMPCTRLx(i) + 1) & 0xc0) >> 6; @@ -2134,7 +2134,7 @@ FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { nranks++; - dra = (u8) ((mchbar_read32(C0DRA01) >> (8 * r)) & 0x7f); + dra = (u8)((mchbar_read32(C0DRA01) >> (8 * r)) & 0x7f); curranksize = drbtab[dra]; if (maxranksize == 0) { maxranksize = curranksize; diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 9ef491b..5f2ea79 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -693,9 +693,9 @@ /* Convert CAS to MCH register friendly */ if (ctrl->CAS < 12) { - mch_cas = (u16) ((ctrl->CAS - 4) << 1); + mch_cas = (u16)((ctrl->CAS - 4) << 1); } else { - mch_cas = (u16) (ctrl->CAS - 12); + mch_cas = (u16)(ctrl->CAS - 12); mch_cas = ((mch_cas << 1) | 0x1); } @@ -1732,7 +1732,7 @@ FOR_ALL_LANES { u64 res = mchbar_read32(lane_base[lane] + GDCRTRAININGRESULT1(channel)); - res |= ((u64) mchbar_read32(lane_base[lane] + + res |= ((u64)mchbar_read32(lane_base[lane] + GDCRTRAININGRESULT2(channel))) << 32; old = ctrl->timings[channel][slotrank].lanes[lane].tx_dqs; @@ -2822,7 +2822,7 @@ } /* 64 DCLKs until idle, decision per rank */ - mchbar_write32(PM_PDWN_CONFIG, get_power_down_mode(ctrl) << 8 | 64); + mchbar_write32(PM_PDWN_CONFIG, get_power_down_mode(ctrl)<< 8 | 64); FOR_ALL_CHANNELS mchbar_write32(PM_TRML_M_CONFIG_ch(channel), 0x00000aaa); diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 7141116..a46390c 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -555,7 +555,7 @@ * Exit early to prevent a system hang. */ reg1 = mchbar_read32(MC_BIOS_DATA); - val2 = (u8) reg1; + val2 = (u8)reg1; if (val2) return; @@ -577,7 +577,7 @@ /* Step 3 - Verify lock frequency */ reg1 = mchbar_read32(MC_BIOS_DATA); - val2 = (u8) reg1; + val2 = (u8)reg1; if (val2 >= ctrl->FRQ) { printk(BIOS_DEBUG, "MPLL frequency is set at : %d MHz\n", (1000 << 8) / ctrl->tCK); -- To view, visit https://review.coreboot.org/c/coreboot/+/69813 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6c1a17d15e24ecdc56b0cc9cb7e7dc7d6e6936b Gerrit-Change-Number: 69813 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 0

[L] Change in coreboot[master]: src/device: Remove unnecessary space after casts
by build bot (Jenkins) (Code Review) 18 Nov '22

18 Nov '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69804 ) Change subject: src/device: Remove unnecessary space after casts ...................................................................... Patch Set 1: (49 comments) File src/device/oprom/x86emu/ops.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/0fc6c032_e3e97720 PS1, Line 1592: imm = (s8)fetch_byte_imm(); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/5b2a2960_e64c3672 PS1, Line 1592: imm = (s8)fetch_byte_imm(); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/5abc7363_5ffce2b8 PS1, Line 1602: imm = (s8)fetch_byte_imm(); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/2aede2d8_0be29751 PS1, Line 1602: imm = (s8)fetch_byte_imm(); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/f5ef4dfe_d224b179 PS1, Line 1614: imm = (s8)fetch_byte_imm(); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/2a39e80a_a44b38bc PS1, Line 1614: imm = (s8)fetch_byte_imm(); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/4f419ab9_a07addcb PS1, Line 1622: imm = (s8)fetch_byte_imm(); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/f3324d3e_afae1dea PS1, Line 1622: imm = (s8)fetch_byte_imm(); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/1ff1c454_71ea2130 PS1, Line 3580: tmp = (u16)mem_access_word(3 * 4 + 2); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/cee3fdb1_5c80804a PS1, Line 4090: ip = (s8)fetch_byte_imm(); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/2461a94e_ff342df7 PS1, Line 4091: ip += (s16)M.x86.R_IP; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/2e1f1928_1659cf17 PS1, Line 4114: ip = (s8)fetch_byte_imm(); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/048cfef3_04888b60 PS1, Line 4115: ip += (s16)M.x86.R_IP; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/97ee2a7f_b576eabe PS1, Line 4138: ip = (s8)fetch_byte_imm(); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/fdd672e6_ef7a999e PS1, Line 4139: ip += (s16)M.x86.R_IP; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/82469b1d_ed1ff07a PS1, Line 4276: ip32 = (s32)fetch_long_imm(); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/4c2d9dee_48e00e8f PS1, Line 4276: ip32 = (s32)fetch_long_imm(); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/2e1c59df_5dd14197 PS1, Line 4277: ip32 += (s16)M.x86.R_IP; /* CHECK SIGN */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/be8f2819_7b76eadb PS1, Line 4277: ip32 += (s16)M.x86.R_IP; /* CHECK SIGN */ please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/cd25a782_43d38ef8 PS1, Line 4281: ip16 = (s16)fetch_word_imm(); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/ac0e3de6_08dc0c64 PS1, Line 4281: ip16 = (s16)fetch_word_imm(); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/d189007a_f4549617 PS1, Line 4282: ip16 += (s16)M.x86.R_IP; /* CHECK SIGN */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/786b4350_ff92cca1 PS1, Line 4282: ip16 += (s16)M.x86.R_IP; /* CHECK SIGN */ please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/ca73c3ee_0d97b520 PS1, Line 5195: M.x86.R_IP = (u16)(*destreg); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/32a59a3f_4405eb8f PS1, Line 5195: M.x86.R_IP = (u16)(*destreg); please, no spaces at the start of a line File src/device/oprom/x86emu/ops2.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/527b7d6c_4dded6d0 PS1, Line 293: target = (s16)fetch_word_imm(); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/96afe14f_a218fd86 PS1, Line 294: target += (s16)M.x86.R_IP; please, no spaces at the start of a line File src/device/oprom/x86emu/prim_ops.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/58c2a1aa_0844fe5f PS1, Line 1205: } else { suspect code indent for conditional statements (8, 12) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/26940eed_9b95f8e3 PS1, Line 1206: res = (u8)d; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/9e2ec71a_2fe89799 PS1, Line 1206: res = (u8)d; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/cc707c7f_aa53ae57 PS1, Line 1245: } else { suspect code indent for conditional statements (8, 12) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/c2135fe0_7ca503fd PS1, Line 1246: res = (u16)d; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/3c8befdf_cbcfb380 PS1, Line 1246: res = (u16)d; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/6afdbe79_e993a143 PS1, Line 1318: } else { suspect code indent for conditional statements (8, 12) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/71d0d27f_18318ef3 PS1, Line 1319: res = (u8)d; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/33b8e0d2_4a778891 PS1, Line 1319: res = (u8)d; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/6896b5b6_9013a70c PS1, Line 2063: M.x86.R_AL = (s8)div; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/8d77a0ce_29eec4d5 PS1, Line 2064: M.x86.R_AH = (s8)mod; please, no spaces at the start of a line File src/device/oprom/yabel/compat/functions.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/431054f4_08f2a7d8 PS1, Line 49: u8* vmem = (u8 *)CONFIG_YABEL_VIRTMEM_LOCATION; "foo* bar" should be "foo *bar" Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/f45d5895_7e8d9392 PS1, Line 51: u8* vmem = (u8 *)(16*1024*1024); /* default to 16MB */ "foo* bar" should be "foo *bar" File src/device/oprom/yabel/compat/of.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/ff6478a1_b18145f1 PS1, Line 37: #define p32cast (int)(unsigned long) (void *) Macros with complex values should be enclosed in parentheses File src/device/oprom/yabel/device.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/3eb5ebcb_8f005437 PS1, Line 154: *((u32*)addr) = cpu_to_le32(val); "(foo*)" should be "(foo *)" Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/203707e0_676c87d3 PS1, Line 176: *((u16*)addr) = cpu_to_le16(val); "(foo*)" should be "(foo *)" Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/ffc3f473_a1e76622 PS1, Line 187: val = cpu_to_le16(*((u16*)addr)); "(foo*)" should be "(foo *)" File src/device/oprom/yabel/interrupt.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/09851326_2d817a39 PS1, Line 235: char_code = (u8)* keycode & 0xff; space prohibited after that '*' (ctx:VxW) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/a32376a0_e83db464 PS1, Line 250: *keycode = (u64)((((u16) scan_code) << 8) | char_code); Possible repeated word: 'keycode' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/edc9b076_3d6987a7 PS1, Line 276: M.x86.R_AX = (u16)* keycode; space prohibited after that '*' (ctx:VxW) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/4b6f4282_0fb09cbb PS1, Line 291: M.x86.R_AX = (u16)* keycode; space prohibited after that '*' (ctx:VxW) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164029): https://review.coreboot.org/c/coreboot/+/69804/comment/1bef0cdd_d9ea159d PS1, Line 321: M.x86.R_AX = (u16)* keycode; space prohibited after that '*' (ctx:VxW) -- To view, visit https://review.coreboot.org/c/coreboot/+/69804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11593245fedc26489e3506d773aaff1ad34188b1 Gerrit-Change-Number: 69804 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 18 Nov 2022 14:11:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: src/soc/samsung: Remove unnecessary space after casts
by Elyes Haouas (Code Review) 18 Nov '22

18 Nov '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69812 ) Change subject: src/soc/samsung: Remove unnecessary space after casts ...................................................................... src/soc/samsung: Remove unnecessary space after casts Change-Id: I32b41eded11e4e575627fec3947a75c08fdfd0a6 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/soc/samsung/exynos5420/fimd.c 1 file changed, 11 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/69812/1 diff --git a/src/soc/samsung/exynos5420/fimd.c b/src/soc/samsung/exynos5420/fimd.c index 53c9fe4..bf236d3 100644 --- a/src/soc/samsung/exynos5420/fimd.c +++ b/src/soc/samsung/exynos5420/fimd.c @@ -182,7 +182,7 @@ cfg |= (EXYNOS_VIDCON0_CLKSEL_SCLK | EXYNOS_VIDCON0_CLKVALUP_ALWAYS | EXYNOS_VIDCON0_VCLKEN_NORMAL | EXYNOS_VIDCON0_CLKDIR_DIVIDED); - src_clock = (unsigned long long) get_lcd_clk(); + src_clock = (unsigned long long)get_lcd_clk(); /* get quotient and remainder. */ remainder = src_clock % pixel_clock; -- To view, visit https://review.coreboot.org/c/coreboot/+/69812 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32b41eded11e4e575627fec3947a75c08fdfd0a6 Gerrit-Change-Number: 69812 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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