coreboot-gerrit November 2022

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[S] Change in coreboot[master]: src/soc/cavium: Remove unnecessary space after casts
by Elyes Haouas (Code Review) 18 Nov '22

18 Nov '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69811 ) Change subject: src/soc/cavium: Remove unnecessary space after casts ...................................................................... src/soc/cavium: Remove unnecessary space after casts Change-Id: Ieb094096e9e204e59a1f3fcf716d906e7736fb43 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/soc/cavium/cn81xx/twsi.c 1 file changed, 12 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/69811/1 diff --git a/src/soc/cavium/cn81xx/twsi.c b/src/soc/cavium/cn81xx/twsi.c index b1c1e66..f06989b 100644 --- a/src/soc/cavium/cn81xx/twsi.c +++ b/src/soc/cavium/cn81xx/twsi.c @@ -497,7 +497,7 @@ twsi_sw.u = 0; twsi_sw.s.op = TWSI_SW_EOP_IA; twsi_sw.s.eop_ia = TWSI_DATA; - twsi_sw.s.data = (u32) (slave_addr << 1) | TWSI_OP_WRITE; + twsi_sw.s.data = (u32)(slave_addr << 1) | TWSI_OP_WRITE; twsi_write_sw(baseaddr, twsi_sw); twsi_write_ctl(baseaddr, TWSI_CTL_ENAB); @@ -574,7 +574,7 @@ twsi_sw.s.op = TWSI_SW_EOP_IA; twsi_sw.s.eop_ia = TWSI_DATA; - twsi_sw.s.data = (u32) (slave_addr << 1) | TWSI_OP_READ; + twsi_sw.s.data = (u32)(slave_addr << 1) | TWSI_OP_READ; twsi_write_sw(baseaddr, twsi_sw); twsi_write_ctl(baseaddr, TWSI_CTL_ENAB); -- To view, visit https://review.coreboot.org/c/coreboot/+/69811 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb094096e9e204e59a1f3fcf716d906e7736fb43 Gerrit-Change-Number: 69811 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: src/soc/nvidia: Remove unnecessary space after casts
by Elyes Haouas (Code Review) 18 Nov '22

18 Nov '22

Attention is currently required from: Julius Werner. Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69810 ) Change subject: src/soc/nvidia: Remove unnecessary space after casts ...................................................................... src/soc/nvidia: Remove unnecessary space after casts Change-Id: I096e88158027ac22cf93a9450c869807dbc14670 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/soc/nvidia/tegra124/dp.c M src/soc/nvidia/tegra124/sor.c M src/soc/nvidia/tegra210/dp.c M src/soc/nvidia/tegra210/sor.c M src/soc/nvidia/tegra210/spi.c 5 files changed, 19 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/69810/1 diff --git a/src/soc/nvidia/tegra124/dp.c b/src/soc/nvidia/tegra124/dp.c index 5da2c06..de98d65 100644 --- a/src/soc/nvidia/tegra124/dp.c +++ b/src/soc/nvidia/tegra124/dp.c @@ -28,7 +28,7 @@ static inline u32 tegra_dpaux_readl(struct tegra_dc_dp_data *dp, u32 reg) { - void *addr = dp->aux_base + (u32) (reg << 2); + void *addr = dp->aux_base + (u32)(reg << 2); u32 reg_val = READL(addr); return reg_val; } @@ -36,7 +36,7 @@ static inline void tegra_dpaux_writel(struct tegra_dc_dp_data *dp, u32 reg, u32 val) { - void *addr = dp->aux_base + (u32) (reg << 2); + void *addr = dp->aux_base + (u32)(reg << 2); WRITEL(val, addr); } diff --git a/src/soc/nvidia/tegra124/sor.c b/src/soc/nvidia/tegra124/sor.c index 3d2750f..8246a09 100644 --- a/src/soc/nvidia/tegra124/sor.c +++ b/src/soc/nvidia/tegra124/sor.c @@ -42,7 +42,7 @@ static inline u32 tegra_sor_readl(struct tegra_dc_sor_data *sor, u32 reg) { - void *addr = sor->base + (u32) (reg << 2); + void *addr = sor->base + (u32)(reg << 2); u32 reg_val = READL(addr); return reg_val; } @@ -50,7 +50,7 @@ static inline void tegra_sor_writel(struct tegra_dc_sor_data *sor, u32 reg, u32 val) { - void *addr = sor->base + (u32) (reg << 2); + void *addr = sor->base + (u32)(reg << 2); WRITEL(val, addr); } diff --git a/src/soc/nvidia/tegra210/dp.c b/src/soc/nvidia/tegra210/dp.c index f3bc208..f6f955c 100644 --- a/src/soc/nvidia/tegra210/dp.c +++ b/src/soc/nvidia/tegra210/dp.c @@ -36,7 +36,7 @@ static inline u32 tegra_dpaux_readl(struct tegra_dc_dp_data *dp, u32 reg) { - void *addr = dp->aux_base + (u32) (reg << 2); + void *addr = dp->aux_base + (u32)(reg << 2); u32 reg_val = READL(addr); return reg_val; } @@ -44,7 +44,7 @@ static inline void tegra_dpaux_writel(struct tegra_dc_dp_data *dp, u32 reg, u32 val) { - void *addr = dp->aux_base + (u32) (reg << 2); + void *addr = dp->aux_base + (u32)(reg << 2); WRITEL(val, addr); } diff --git a/src/soc/nvidia/tegra210/sor.c b/src/soc/nvidia/tegra210/sor.c index 91ea5f4..c24e0d6 100644 --- a/src/soc/nvidia/tegra210/sor.c +++ b/src/soc/nvidia/tegra210/sor.c @@ -44,7 +44,7 @@ static inline u32 tegra_sor_readl(struct tegra_dc_sor_data *sor, u32 reg) { - void *addr = sor->base + (u32) (reg << 2); + void *addr = sor->base + (u32)(reg << 2); u32 reg_val = READL(addr); return reg_val; } @@ -52,7 +52,7 @@ static inline void tegra_sor_writel(struct tegra_dc_sor_data *sor, u32 reg, u32 val) { - void *addr = sor->base + (u32) (reg << 2); + void *addr = sor->base + (u32)(reg << 2); WRITEL(val, addr); } diff --git a/src/soc/nvidia/tegra210/spi.c b/src/soc/nvidia/tegra210/spi.c index f8db110..b7bc685 100644 --- a/src/soc/nvidia/tegra210/spi.c +++ b/src/soc/nvidia/tegra210/spi.c @@ -478,7 +478,7 @@ dcache_clean_by_mva(spi->out_buf, bytes); write32(&spi->dma_out->regs->apb_ptr, - (uintptr_t) & spi->regs->tx_fifo); + (uintptr_t)& spi->regs->tx_fifo); write32(&spi->dma_out->regs->ahb_ptr, (uintptr_t)spi->out_buf); setbits32(&spi->dma_out->regs->csr, APB_CSR_DIR); setup_dma_params(spi, spi->dma_out); -- To view, visit https://review.coreboot.org/c/coreboot/+/69810 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I096e88158027ac22cf93a9450c869807dbc14670 Gerrit-Change-Number: 69810 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: src/soc/mediatek: Remove unnecessary space after casts
by Elyes Haouas (Code Review) 18 Nov '22

18 Nov '22

Attention is currently required from: Hung-Te Lin. Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69809 ) Change subject: src/soc/mediatek: Remove unnecessary space after casts ...................................................................... src/soc/mediatek: Remove unnecessary space after casts Change-Id: I871579cc434820294f285298fe43da4cd1da27a3 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/spm.c 2 files changed, 17 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/69809/1 diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index ec39049..c772885 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -985,14 +985,14 @@ u16 debug_cnt_perbyte, current_pass = 0, pass_byte_cnt = 0; for (u8 dqs = 0; dqs < DQS_NUMBER; dqs++) { - u8 dqs_result_r = (u8) ((result_r >> (8 * dqs)) & 0xff); - u8 dqs_result_f = (u8) ((result_f >> (8 * dqs)) & 0xff); + u8 dqs_result_r = (u8)((result_r >> (8 * dqs)) & 0xff); + u8 dqs_result_f = (u8)((result_f >> (8 * dqs)) & 0xff); if (pass_byte_cnt & (1 << dqs)) continue; current_pass = 0; - debug_cnt_perbyte = (u16) debug_cnt[dqs]; + debug_cnt_perbyte = (u16)debug_cnt[dqs]; if (dqs_result_r == 0 && dqs_result_f == 0 && debug_cnt_perbyte == GATING_GOLDEND_DQSCNT) current_pass = 1; @@ -2135,7 +2135,7 @@ dramc_dbg("%d ", dly); for (size_t bit = 0; bit < DQ_DATA_WIDTH; bit++) { - bool bit_fail = (err_value & ((u32) 1 << bit)) != 0; + bool bit_fail = (err_value & ((u32)1 << bit)) != 0; /* pass window bigger than 7, * consider as real pass window. @@ -2401,7 +2401,7 @@ SET32_BITFIELDS(&ch[chn].ao.padctrl, PADCTRL_DQIENQKEND, 1, PADCTRL_DQIENLATEBEGIN, 1); - return (u8) best_step; + return (u8)best_step; } static void dramc_dual_rank_rx_datlat_cal(u8 chn, u8 freq_group, u8 datlat0, u8 datlat1) diff --git a/src/soc/mediatek/mt8183/spm.c b/src/soc/mediatek/mt8183/spm.c index 5fba84d..83e814f 100644 --- a/src/soc/mediatek/mt8183/spm.c +++ b/src/soc/mediatek/mt8183/spm.c @@ -156,7 +156,7 @@ write32(&mtk_spm->pcm_im_host_rw_ptr, PCM_IM_HOST_EN_LSB | PCM_IM_HOST_W_EN_LSB | i); write32(&mtk_spm->pcm_im_host_rw_dat, - (u32) *(pcm->buf + i)); + (u32)*(pcm->buf + i)); } write32(&mtk_spm->pcm_im_host_rw_ptr, 0); } @@ -168,7 +168,7 @@ for (i = 0; i < pcm->desc.size; i++) { write32(&mtk_spm->pcm_im_host_rw_ptr, PCM_IM_HOST_EN_LSB | i); if ((read32(&mtk_spm->pcm_im_host_rw_dat)) != - (u32) *(pcm->buf + i)) + (u32)*(pcm->buf + i)) spm_load_pcm_code(pcm); } write32(&mtk_spm->pcm_im_host_rw_ptr, 0); -- To view, visit https://review.coreboot.org/c/coreboot/+/69809 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I871579cc434820294f285298fe43da4cd1da27a3 Gerrit-Change-Number: 69809 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: src/soc/ti: Remove unnecessary space after casts
by Elyes Haouas (Code Review) 18 Nov '22

18 Nov '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69808 ) Change subject: src/soc/ti: Remove unnecessary space after casts ...................................................................... src/soc/ti: Remove unnecessary space after casts Change-Id: If4564abf060410726b0b245ba002a35ca9d30769 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/soc/ti/am335x/uart.c 1 file changed, 11 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/69808/1 diff --git a/src/soc/ti/am335x/uart.c b/src/soc/ti/am335x/uart.c index b19ba96..0543475 100644 --- a/src/soc/ti/am335x/uart.c +++ b/src/soc/ti/am335x/uart.c @@ -149,7 +149,7 @@ void uart_init(unsigned int idx) { struct am335x_uart *uart = uart_platform_baseptr(idx); - uint16_t div = (uint16_t) uart_baudrate_divisor( + uint16_t div = (uint16_t)uart_baudrate_divisor( get_uart_baudrate(), uart_platform_refclk(), 16); am335x_uart_init(uart, div); } -- To view, visit https://review.coreboot.org/c/coreboot/+/69808 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4564abf060410726b0b245ba002a35ca9d30769 Gerrit-Change-Number: 69808 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: src/soc/qualcomm: Remove unnecessary space after casts
by Elyes Haouas (Code Review) 18 Nov '22

18 Nov '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69807 ) Change subject: src/soc/qualcomm: Remove unnecessary space after casts ...................................................................... src/soc/qualcomm: Remove unnecessary space after casts Change-Id: Ic6c711fe3fad19c24ca4c01f8d0a4bc002f14bd6 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/soc/qualcomm/common/include/soc/qspi_common.h M src/soc/qualcomm/common/qspi.c M src/soc/qualcomm/common/qupv3_config.c M src/soc/qualcomm/common/usb/qusb_phy.c M src/soc/qualcomm/common/usb/snps_usb_phy.c M src/soc/qualcomm/ipq40xx/blobs_init.c M src/soc/qualcomm/ipq40xx/spi.c M src/soc/qualcomm/ipq806x/blobs_init.c M src/soc/qualcomm/qcs405/spi.c M src/soc/qualcomm/sc7280/pcie.c 10 files changed, 47 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/69807/1 diff --git a/src/soc/qualcomm/common/include/soc/qspi_common.h b/src/soc/qualcomm/common/include/soc/qspi_common.h index 6a1496a..a0c8e46 100644 --- a/src/soc/qualcomm/common/include/soc/qspi_common.h +++ b/src/soc/qualcomm/common/include/soc/qspi_common.h @@ -30,7 +30,7 @@ }; check_member(qcom_qspi_regs, rd_fifo, 0x50); -static struct qcom_qspi_regs * const qcom_qspi = (void *) QSPI_BASE; +static struct qcom_qspi_regs * const qcom_qspi = (void *)QSPI_BASE; // MSTR_CONFIG register diff --git a/src/soc/qualcomm/common/qspi.c b/src/soc/qualcomm/common/qspi.c index 1c345cc..c053d65 100644 --- a/src/soc/qualcomm/common/qspi.c +++ b/src/soc/qualcomm/common/qspi.c @@ -66,7 +66,7 @@ uint32_t mstr_int_status; write32(&qcom_qspi->mstr_int_sts, 0xFFFFFFFF); - write32(&qcom_qspi->next_dma_desc_addr, (uint32_t)(uintptr_t) chain); + write32(&qcom_qspi->next_dma_desc_addr, (uint32_t)(uintptr_t)chain); while (1) { mstr_int_status = read32(&qcom_qspi->mstr_int_sts); @@ -87,15 +87,15 @@ if (desc->direction == MASTER_READ) { if (desc->bounce_length == 0) dcache_invalidate_by_mva( - (void *)(uintptr_t) desc->data_address, + (void *)(uintptr_t)desc->data_address, desc->length); else { - src = (void *)(uintptr_t) desc->bounce_src; - dst = (void *)(uintptr_t) desc->bounce_dst; + src = (void *)(uintptr_t)desc->bounce_src; + dst = (void *)(uintptr_t)desc->bounce_dst; memcpy(dst, src, desc->bounce_length); } } - desc = (void *)(uintptr_t) desc->next_descriptor; + desc = (void *)(uintptr_t)desc->next_descriptor; } curr_desc_idx = -1; } @@ -112,7 +112,7 @@ index = ++curr_desc_idx; next = &dma->descriptors[index]; - next->data_address = (uint32_t) (uintptr_t) dma->buffers[index]; + next->data_address = (uint32_t)(uintptr_t) dma->buffers[index]; next->next_descriptor = 0; next->direction = MASTER_READ; @@ -131,7 +131,7 @@ next->bounce_length = 0; if (current) - current->next_descriptor = (uint32_t)(uintptr_t) next; + current->next_descriptor = (uint32_t)(uintptr_t)next; return next; } @@ -164,13 +164,13 @@ desc = allocate_descriptor(); desc->direction = write; desc->multi_io_mode = data_mode; - ptr = (void *)(uintptr_t) desc->data_address; + ptr = (void *)(uintptr_t)desc->data_address; if (write) { memcpy(ptr, data, data_bytes); } else { - desc->bounce_src = (uint32_t)(uintptr_t) ptr; - desc->bounce_dst = (uint32_t)(uintptr_t) data; + desc->bounce_src = (uint32_t)(uintptr_t)ptr; + desc->bounce_dst = (uint32_t)(uintptr_t)data; desc->bounce_length = data_bytes; } @@ -185,7 +185,7 @@ desc = allocate_descriptor(); desc->direction = write; desc->multi_io_mode = data_mode; - desc->data_address = (uint32_t)(uintptr_t) data; + desc->data_address = (uint32_t)(uintptr_t)data; desc->length = data_bytes; if (write) @@ -291,7 +291,7 @@ return -1; } - queue_data((uint8_t *) (out_bytes ? dout : din), + queue_data((uint8_t *)(out_bytes ? dout : din), in_bytes | out_bytes, mode, !!out_bytes); flush_chain(); diff --git a/src/soc/qualcomm/common/qupv3_config.c b/src/soc/qualcomm/common/qupv3_config.c index b243fdd..919c11b 100644 --- a/src/soc/qualcomm/common/qupv3_config.c +++ b/src/soc/qualcomm/common/qupv3_config.c @@ -188,7 +188,7 @@ struct gsi_fw_hdr *gsi_hdr; struct gsi_fw_iep *fwIep; struct gsi_fw_iram *fwIRam; - struct gsi_regs *regs = (struct gsi_regs *)(uintptr_t) addr; + struct gsi_regs *regs = (struct gsi_regs *)(uintptr_t)addr; static const char * const filename = "fallback/gsi_fw"; /* Assign firmware header base */ @@ -241,7 +241,7 @@ { struct qupv3_common_reg *qupv3_common; /* HPG section 3.1.2 */ - qupv3_common = (struct qupv3_common_reg *)(uintptr_t) addr; + qupv3_common = (struct qupv3_common_reg *)(uintptr_t)addr; setbits32(&qupv3_common->qupv3_common_cfg_reg, QUPV3_COMMON_CFG_FAST_SWITCH_TO_HIGH_DISABLE_BMSK); diff --git a/src/soc/qualcomm/common/usb/qusb_phy.c b/src/soc/qualcomm/common/usb/qusb_phy.c index 494f7cd..ddb087f 100644 --- a/src/soc/qualcomm/common/usb/qusb_phy.c +++ b/src/soc/qualcomm/common/usb/qusb_phy.c @@ -96,7 +96,7 @@ hs_phy_reg = &qusb_phy; - hs_phy_reg->board_data = (struct usb_board_data *) board_data; + hs_phy_reg->board_data = (struct usb_board_data *)board_data; /* PWR_CTRL: set the power down bit to disable the PHY */ diff --git a/src/soc/qualcomm/common/usb/snps_usb_phy.c b/src/soc/qualcomm/common/usb/snps_usb_phy.c index 1b2d869..d04694b 100644 --- a/src/soc/qualcomm/common/usb/snps_usb_phy.c +++ b/src/soc/qualcomm/common/usb/snps_usb_phy.c @@ -36,7 +36,7 @@ void hs_usb_phy_init(void *board_data) { struct usb_board_data *override_data = - (struct usb_board_data *) board_data; + (struct usb_board_data *)board_data; clrsetbits32(&hs_phy_reg->cfg0, UTMI_PHY_CMN_CTRL_OVERRIDE_EN, UTMI_PHY_CMN_CTRL_OVERRIDE_EN); diff --git a/src/soc/qualcomm/ipq40xx/blobs_init.c b/src/soc/qualcomm/ipq40xx/blobs_init.c index 60e4f0d..ef19053 100644 --- a/src/soc/qualcomm/ipq40xx/blobs_init.c +++ b/src/soc/qualcomm/ipq40xx/blobs_init.c @@ -31,7 +31,7 @@ (blob_mbn->mbn_total_size > blob_size)) return NULL; - blob_dest = (void *) blob_mbn->mbn_destination; + blob_dest = (void *)blob_mbn->mbn_destination; if (blob_mbn->mbn_destination) { /* Copy the blob to the appropriate memory location. */ diff --git a/src/soc/qualcomm/ipq40xx/spi.c b/src/soc/qualcomm/ipq40xx/spi.c index 0893dfc..ab8f530 100644 --- a/src/soc/qualcomm/ipq40xx/spi.c +++ b/src/soc/qualcomm/ipq40xx/spi.c @@ -591,7 +591,7 @@ write_force_cs(slave, 1); if (dout != NULL) { - ret = blsp_spi_write(ds, txp, (unsigned int) out_bytes); + ret = blsp_spi_write(ds, txp, (unsigned int)out_bytes); if (ret != SUCCESS) goto out; } diff --git a/src/soc/qualcomm/ipq806x/blobs_init.c b/src/soc/qualcomm/ipq806x/blobs_init.c index 15068a5..851ee81 100644 --- a/src/soc/qualcomm/ipq806x/blobs_init.c +++ b/src/soc/qualcomm/ipq806x/blobs_init.c @@ -27,7 +27,7 @@ (blob_mbn->mbn_total_size > blob_size)) return NULL; - blob_dest = (void *) blob_mbn->mbn_destination; + blob_dest = (void *)blob_mbn->mbn_destination; if (blob_mbn->mbn_destination) { /* Copy the blob to the appropriate memory location. */ memcpy(blob_dest, blob_mbn + 1, blob_mbn->mbn_total_size); @@ -99,7 +99,7 @@ return; } - load_addr = (u32) load_ipq_blob("rpm.mbn"); + load_addr = (u32)load_ipq_blob("rpm.mbn"); if (!load_addr) die("could not find or map RPM code\n"); diff --git a/src/soc/qualcomm/qcs405/spi.c b/src/soc/qualcomm/qcs405/spi.c index e212b84..4863188 100644 --- a/src/soc/qualcomm/qcs405/spi.c +++ b/src/soc/qualcomm/qcs405/spi.c @@ -660,7 +660,7 @@ return ret; if (dout != NULL) { - ret = blsp_spi_write(ds, txp, (unsigned int) out_bytes); + ret = blsp_spi_write(ds, txp, (unsigned int)out_bytes); if (ret != SUCCESS) goto out; } diff --git a/src/soc/qualcomm/sc7280/pcie.c b/src/soc/qualcomm/sc7280/pcie.c index 28d520c..edc73b0 100644 --- a/src/soc/qualcomm/sc7280/pcie.c +++ b/src/soc/qualcomm/sc7280/pcie.c @@ -140,13 +140,13 @@ }; static pcie_cntlr_cfg_t pcie_host = { - .parf = (void *) PCIE1_PCIE_PARF, - .dbi_base = (void *) PCIE1_GEN3X2_PCIE_DBI, - .elbi = (void *) PCIE1_GEN3X2_PCIE_ELBI, - .atu_base = (void *) PCIE1_GEN3X2_DWC_PCIE_DM_IATU, - .cfg_base = (void *) PCIE1_GEN3X2_PCIE_DBI + PCIE_EP_CONF_OFFSET, - .pcie_bcr = (void *) PCIE1_BCR, - .qmp_phy_bcr = (void *) GCC_PCIE_1_PHY_BCR, + .parf = (void *)PCIE1_PCIE_PARF, + .dbi_base = (void *)PCIE1_GEN3X2_PCIE_DBI, + .elbi = (void *)PCIE1_GEN3X2_PCIE_ELBI, + .atu_base = (void *)PCIE1_GEN3X2_DWC_PCIE_DM_IATU, + .cfg_base = (void *)PCIE1_GEN3X2_PCIE_DBI + PCIE_EP_CONF_OFFSET, + .pcie_bcr = (void *)PCIE1_BCR, + .qmp_phy_bcr = (void *)GCC_PCIE_1_PHY_BCR, .lanes = PCIE_3x2_NUM_LANES, .cfg_size = PCIE_EP_CONF_SIZE, .perst = GPIO(2), @@ -160,14 +160,14 @@ }; static pcie_qmp_phy_cfg_t pcie1_qmp_phy_3x2 = { - .qmp_phy_base = (void *) PCIE_1_QMP_PHY, - .serdes = (void *) PCE1_QPHY_SERDES, - .tx0 = (void *) PCE1_QPHY_TX0, - .rx0 = (void *) PCE1_QPHY_RX0, - .pcs = (void *) PCIE1_QMP_PHY_PCS_COM, - .tx1 = (void *) PCE1_QPHY_TX1, - .rx1 = (void *) PCE1_QPHY_RX1, - .pcs_misc = (void *) PCE1_QPHY_PCS_MISC, + .qmp_phy_base = (void *)PCIE_1_QMP_PHY, + .serdes = (void *)PCE1_QPHY_SERDES, + .tx0 = (void *)PCE1_QPHY_TX0, + .rx0 = (void *)PCE1_QPHY_RX0, + .pcs = (void *)PCIE1_QMP_PHY_PCS_COM, + .tx1 = (void *)PCE1_QPHY_TX1, + .rx1 = (void *)PCE1_QPHY_RX1, + .pcs_misc = (void *)PCE1_QPHY_PCS_MISC, .serdes_tbl = sc7280_qmp_pcie_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(sc7280_qmp_pcie_serdes_tbl), .tx_tbl = sc7280_qmp_pcie_tx_tbl, -- To view, visit https://review.coreboot.org/c/coreboot/+/69807 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6c711fe3fad19c24ca4c01f8d0a4bc002f14bd6 Gerrit-Change-Number: 69807 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: src/soc/intel: Remove unnecessary space after casts
by Elyes Haouas (Code Review) 18 Nov '22

18 Nov '22

Attention is currently required from: Jeff Daly, Jonathan Zhang, Arthur Heymans, Tarun Tuli, Sean Rhodes, Subrata Banik, Johnny Lin, Kapil Porwal, Christian Walter, Vanessa Eusebio, Lean Sheng Tan, Werner Zeh, Tim Chu. Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69806 ) Change subject: src/soc/intel: Remove unnecessary space after casts ...................................................................... src/soc/intel: Remove unnecessary space after casts Change-Id: I098104f32dd7c66d7bb79588ef315a242c3889ba Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/soc/intel/alderlake/bootblock/pch.c M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/pmutil.c M src/soc/intel/alderlake/systemagent.c M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/cse.c M src/soc/intel/apollolake/pmutil.c M src/soc/intel/apollolake/romstage.c M src/soc/intel/apollolake/systemagent.c M src/soc/intel/baytrail/refcode_native.c M src/soc/intel/braswell/lpe.c M src/soc/intel/broadwell/pch/me.c M src/soc/intel/broadwell/pch/pmutil.c M src/soc/intel/broadwell/pch/sata.c M src/soc/intel/broadwell/refcode.c M src/soc/intel/cannonlake/bootblock/pch.c M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/common/block/crashlog/crashlog.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/denverton_ns/pmutil.c M src/soc/intel/elkhartlake/bootblock/pch.c M src/soc/intel/elkhartlake/fsp_params.c M src/soc/intel/elkhartlake/pmutil.c M src/soc/intel/icelake/bootblock/pch.c M src/soc/intel/icelake/fsp_params.c M src/soc/intel/icelake/pmutil.c M src/soc/intel/jasperlake/bootblock/pch.c M src/soc/intel/jasperlake/fsp_params.c M src/soc/intel/jasperlake/pmutil.c M src/soc/intel/meteorlake/bootblock/soc_die.c M src/soc/intel/meteorlake/fsp_params.c M src/soc/intel/meteorlake/pmutil.c M src/soc/intel/quark/acpi.c M src/soc/intel/quark/memmap.c M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/pmutil.c M src/soc/intel/skylake/systemagent.c M src/soc/intel/tigerlake/bootblock/pch.c M src/soc/intel/tigerlake/fsp_params.c M src/soc/intel/tigerlake/pmutil.c M src/soc/intel/xeon_sp/cpx/hob_display.c M src/soc/intel/xeon_sp/nb_acpi.c M src/soc/intel/xeon_sp/pmutil.c M src/soc/intel/xeon_sp/util.c 46 files changed, 96 insertions(+), 86 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/69806/1 diff --git a/src/soc/intel/alderlake/bootblock/pch.c b/src/soc/intel/alderlake/bootblock/pch.c index 712c128..83531de 100644 --- a/src/soc/intel/alderlake/bootblock/pch.c +++ b/src/soc/intel/alderlake/bootblock/pch.c @@ -54,7 +54,7 @@ pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); /* Enable PWRM in PMC */ - setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN); + setbits32((void *)PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN); } void bootblock_pch_early_init(void) diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 26eba76..853b2f2 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -594,7 +594,7 @@ * This would avoid APs from getting hijacked by FSP while coreboot * decides to set SkipMpInit UPD. */ - s_cfg->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); + s_cfg->CpuMpPpi = (uintptr_t)mp_fill_ppi_services_data(); if (CONFIG(USE_FSP_MP_INIT)) /* diff --git a/src/soc/intel/alderlake/pmutil.c b/src/soc/intel/alderlake/pmutil.c index 9389322..e6aeed8 100644 --- a/src/soc/intel/alderlake/pmutil.c +++ b/src/soc/intel/alderlake/pmutil.c @@ -253,7 +253,7 @@ /* STM Support */ uint16_t get_pmbase(void) { - return (uint16_t) ACPI_BASE_ADDRESS; + return (uint16_t)ACPI_BASE_ADDRESS; } /* diff --git a/src/soc/intel/alderlake/systemagent.c b/src/soc/intel/alderlake/systemagent.c index 9a8532d..36fa45b 100644 --- a/src/soc/intel/alderlake/systemagent.c +++ b/src/soc/intel/alderlake/systemagent.c @@ -84,9 +84,9 @@ { msr_t msr; msr = rdmsr(MSR_PRMRR_BASE_0); - *prmrr_base = (uint64_t) msr.hi << 32 | msr.lo; + *prmrr_base = (uint64_t)msr.hi << 32 | msr.lo; msr = rdmsr(MSR_PRMRR_PHYS_MASK); - *prmrr_mask = (uint64_t) msr.hi << 32 | msr.lo; + *prmrr_mask = (uint64_t)msr.hi << 32 | msr.lo; return 0; } diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 811c762..a537b0f 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -77,7 +77,7 @@ /* Assign address of PERST_0 if GPIO is defined in devicetree */ if (cfg->prt0_gpio != GPIO_PRT0_UDEF) - gnvs->prt0 = (uintptr_t) gpio_dwx_address(cfg->prt0_gpio); + gnvs->prt0 = (uintptr_t)gpio_dwx_address(cfg->prt0_gpio); /* Get sdcard cd GPIO portid if GPIO is defined in devicetree. * Get offset of sdcard cd pin. @@ -216,7 +216,7 @@ static int acpigen_soc_get_gpio_val(unsigned int gpio_num, uint32_t mask) { assert(gpio_num < TOTAL_PADS); - uintptr_t addr = (uintptr_t) gpio_dwx_address(gpio_num); + uintptr_t addr = (uintptr_t)gpio_dwx_address(gpio_num); acpigen_soc_get_dw0_in_local5(addr); @@ -240,7 +240,7 @@ static int acpigen_soc_set_gpio_val(unsigned int gpio_num, uint32_t val) { assert(gpio_num < TOTAL_PADS); - uintptr_t addr = (uintptr_t) gpio_dwx_address(gpio_num); + uintptr_t addr = (uintptr_t)gpio_dwx_address(gpio_num); acpigen_soc_get_dw0_in_local5(addr); diff --git a/src/soc/intel/apollolake/cse.c b/src/soc/intel/apollolake/cse.c index 01c4c47..46bc8fb 100644 --- a/src/soc/intel/apollolake/cse.c +++ b/src/soc/intel/apollolake/cse.c @@ -117,7 +117,7 @@ { uint8_t buff; - write8(&buff, (uint8_t) state); + write8(&buff, (uint8_t)state); return rdev_writeat(rdev, &buff, 0, sizeof(buff)); } diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index f474553..878b2a6 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -221,7 +221,7 @@ /* STM Support */ uint16_t get_pmbase(void) { - return (uint16_t) ACPI_BASE_ADDRESS; + return (uint16_t)ACPI_BASE_ADDRESS; } void pmc_soc_set_afterg3_en(const bool on) diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 757bad3..b9ec4e2 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -294,7 +294,7 @@ parse_devicetree_setting(mupd); /* Do NOT let FSP do any GPIO pad configuration */ - mupd->FspmConfig.PreMemGpioTablePtr = (uintptr_t) NULL; + mupd->FspmConfig.PreMemGpioTablePtr = (uintptr_t)NULL; mupd->FspmConfig.SkipCseRbp = CONFIG(SKIP_CSE_RBP); diff --git a/src/soc/intel/apollolake/systemagent.c b/src/soc/intel/apollolake/systemagent.c index f352f8a..b61f5fa 100644 --- a/src/soc/intel/apollolake/systemagent.c +++ b/src/soc/intel/apollolake/systemagent.c @@ -70,7 +70,7 @@ printk(BIOS_ERR, "Incorrect PRMRR base hob size\n"); return -1; } - *prmrr_base = *(uint64_t *) hob; + *prmrr_base = *(uint64_t *)hob; hob = fsp_find_extension_hob_by_guid(prmrr_size_guid, &hob_size); @@ -82,7 +82,7 @@ printk(BIOS_ERR, "Incorrect PRMRR base hob size\n"); return -1; } - prmrr_size = *(uint64_t *) hob; + prmrr_size = *(uint64_t *)hob; phys_address_mask = (1ULL << cpu_phys_address_size()) - 1; *prmrr_mask = phys_address_mask & ~(uint64_t)(prmrr_size - 1); diff --git a/src/soc/intel/baytrail/refcode_native.c b/src/soc/intel/baytrail/refcode_native.c index c915530..bc7a87c 100644 --- a/src/soc/intel/baytrail/refcode_native.c +++ b/src/soc/intel/baytrail/refcode_native.c @@ -29,21 +29,21 @@ static void gpio_sc_sdcard_workaround(void) { - setbits32((char *) IO_BASE_ADDRESS + 0x698, (1 << 0)); - setbits32((char *) IO_BASE_ADDRESS + 0x698, (1 << 2)); - clrbits32((char *) IO_BASE_ADDRESS + 0x698, (1 << 1)); - clrbits32((char *) IO_BASE_ADDRESS + 0x690, (1 << 3)); + setbits32((char *)IO_BASE_ADDRESS + 0x698, (1 << 0)); + setbits32((char *)IO_BASE_ADDRESS + 0x698, (1 << 2)); + clrbits32((char *)IO_BASE_ADDRESS + 0x698, (1 << 1)); + clrbits32((char *)IO_BASE_ADDRESS + 0x690, (1 << 3)); udelay(100); - clrbits32((char *) IO_BASE_ADDRESS + 0x698, (1 << 0)); + clrbits32((char *)IO_BASE_ADDRESS + 0x698, (1 << 0)); udelay(100); - write32((char *) IO_BASE_ADDRESS + 0x830, 0x78480); + write32((char *)IO_BASE_ADDRESS + 0x830, 0x78480); udelay(40); - write32((char *) IO_BASE_ADDRESS + 0x830, 0x78080); - setbits32((char *) IO_BASE_ADDRESS + 0x698, (1 << 0)); + write32((char *)IO_BASE_ADDRESS + 0x830, 0x78080); + setbits32((char *)IO_BASE_ADDRESS + 0x698, (1 << 0)); udelay(100); - setbits32((char *) IO_BASE_ADDRESS + 0x698, (1 << 1)); - clrbits32((char *) IO_BASE_ADDRESS + 0x698, (1 << 2)); - clrsetbits32((char *) IO_BASE_ADDRESS + 0x690, 7, (1 << 0)); + setbits32((char *)IO_BASE_ADDRESS + 0x698, (1 << 1)); + clrbits32((char *)IO_BASE_ADDRESS + 0x698, (1 << 2)); + clrsetbits32((char *)IO_BASE_ADDRESS + 0x690, 7, (1 << 0)); } #define BUNIT_BALIMIT0 0x0b @@ -99,10 +99,10 @@ program_modphy_table(revb0_modphy_table); } - setbits32((char *) PMC_BASE_ADDRESS + R_PCH_PMC_MTPMC1, 8); + setbits32((char *)PMC_BASE_ADDRESS + R_PCH_PMC_MTPMC1, 8); for (pollcnt = 0; pollcnt < 10; ++pollcnt) { - tmp = read32((char *) PMC_BASE_ADDRESS + R_PCH_PMC_MTPMC1); + tmp = read32((char *)PMC_BASE_ADDRESS + R_PCH_PMC_MTPMC1); printk(BIOS_DEBUG, "Polling bit3 of R_PCH_PMC_MTPMC1 = %x\n", tmp); if (!(tmp & 8)) break; diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c index 27f38ea..230c6dee 100644 --- a/src/soc/intel/braswell/lpe.c +++ b/src/soc/intel/braswell/lpe.c @@ -114,7 +114,7 @@ printk(BIOS_DEBUG, "LPE Firmware memory not found.\n"); return; } - printk(BIOS_DEBUG, "LPE FW Resource: 0x%08x\n", (u32) res->base); + printk(BIOS_DEBUG, "LPE FW Resource: 0x%08x\n", (u32)res->base); /* Continue using old way of informing firmware address / size. */ pci_write_config32(dev, FIRMWARE_PCI_REG_BASE, res->base); diff --git a/src/soc/intel/broadwell/pch/me.c b/src/soc/intel/broadwell/pch/me.c index 4650a224..f1750d2 100644 --- a/src/soc/intel/broadwell/pch/me.c +++ b/src/soc/intel/broadwell/pch/me.c @@ -598,7 +598,7 @@ u16 reg16; /* S3 path will have hidden this device already */ - if (!mei_base_address || mei_base_address == (u8 *) 0xfffffff0) + if (!mei_base_address || mei_base_address == (u8 *)0xfffffff0) return; /* Make sure IO is disabled */ diff --git a/src/soc/intel/broadwell/pch/pmutil.c b/src/soc/intel/broadwell/pch/pmutil.c index 59ae72f..708fc0f 100644 --- a/src/soc/intel/broadwell/pch/pmutil.c +++ b/src/soc/intel/broadwell/pch/pmutil.c @@ -425,5 +425,5 @@ /* STM Support */ uint16_t get_pmbase(void) { - return (uint16_t) ACPI_BASE_ADDRESS; + return (uint16_t)ACPI_BASE_ADDRESS; } diff --git a/src/soc/intel/broadwell/pch/sata.c b/src/soc/intel/broadwell/pch/sata.c index 9f929a4..edb9830 100644 --- a/src/soc/intel/broadwell/pch/sata.c +++ b/src/soc/intel/broadwell/pch/sata.c @@ -82,8 +82,8 @@ /* PI (Ports implemented) */ write32(abar + 0x0c, config->sata_port_map); - (void) read32(abar + 0x0c); /* Read back 1 */ - (void) read32(abar + 0x0c); /* Read back 2 */ + (void)read32(abar + 0x0c); /* Read back 1 */ + (void)read32(abar + 0x0c); /* Read back 2 */ /* CAP2 (HBA Capabilities Extended)*/ if (config->sata_devslp_disable) { diff --git a/src/soc/intel/broadwell/refcode.c b/src/soc/intel/broadwell/refcode.c index 9d4bd2d..ee54f19 100644 --- a/src/soc/intel/broadwell/refcode.c +++ b/src/soc/intel/broadwell/refcode.c @@ -50,7 +50,7 @@ broadwell_fill_pei_data(&pei_data); pei_data.boot_mode = acpi_is_wakeup_s3() ? ACPI_S3 : 0; - pei_data.saved_data = (void *) &dummy; + pei_data.saved_data = (void *)&dummy; entry = load_reference_code(); if (entry == NULL) { diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index 7651cdf..8ec4782 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -56,7 +56,7 @@ pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); /* Enable PWRM in PMC */ - setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN); + setbits32((void *)PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN); } void bootblock_pch_early_init(void) diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index 7df8d47..480f65b 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -246,7 +246,7 @@ /* STM Support */ uint16_t get_pmbase(void) { - return (uint16_t) ACPI_BASE_ADDRESS; + return (uint16_t)ACPI_BASE_ADDRESS; } /* diff --git a/src/soc/intel/common/block/crashlog/crashlog.c b/src/soc/intel/common/block/crashlog/crashlog.c index 239c72c..2bdf2cc 100644 --- a/src/soc/intel/common/block/crashlog/crashlog.c +++ b/src/soc/intel/common/block/crashlog/crashlog.c @@ -329,7 +329,7 @@ /* allocate mem for the record to be copied */ unsigned long pmc_cl_cbmem_addr; - pmc_cl_cbmem_addr = (unsigned long) cbmem_add(CBMEM_ID_PMC_CRASHLOG, + pmc_cl_cbmem_addr = (unsigned long)cbmem_add(CBMEM_ID_PMC_CRASHLOG, pmc_crashLog_size); if (!pmc_cl_cbmem_addr) { printk(BIOS_ERR, "Unable to allocate CBMEM PMC crashLog entry.\n"); @@ -337,7 +337,7 @@ } memset((void *)pmc_cl_cbmem_addr, 0, pmc_crashLog_size); - dest = (u32 *)(uintptr_t) pmc_cl_cbmem_addr; + dest = (u32 *)(uintptr_t)pmc_cl_cbmem_addr; bool pmc_sram = true; pmc_crashlog_desc_table_t descriptor_table = cl_get_pmc_descriptor_table(); if (discovery_buf.bits.discov_mechanism == 1) { @@ -400,16 +400,16 @@ /* allocate memory buffers for CPU crashog data to be copied */ unsigned long cpu_crashlog_cbmem_addr; - cpu_crashlog_cbmem_addr = (unsigned long) cbmem_add(CBMEM_ID_CPU_CRASHLOG, + cpu_crashlog_cbmem_addr = (unsigned long)cbmem_add(CBMEM_ID_CPU_CRASHLOG, m_cpu_crashLog_size); if (!cpu_crashlog_cbmem_addr) { printk(BIOS_ERR, "Failed to add CPU main crashLog entries to CBMEM.\n"); return; } - memset((void *) cpu_crashlog_cbmem_addr, 0, m_cpu_crashLog_size); + memset((void *)cpu_crashlog_cbmem_addr, 0, m_cpu_crashLog_size); tmp_bar_addr = cl_get_cpu_bar_addr(); - dest = (u32 *)(uintptr_t) cpu_crashlog_cbmem_addr; + dest = (u32 *)(uintptr_t)cpu_crashlog_cbmem_addr; bool pmc_sram = false; for (int i = 0 ; i < cpu_cl_disc_tab.header.fields.count ; i++) { diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index ceb75e2..bdcc186 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -162,7 +162,7 @@ uint8_t wp, rp; rp = data >> CSR_RP_START; wp = data >> CSR_WP_START; - return (uint8_t) (wp - rp); + return (uint8_t)(wp - rp); } static size_t cse_filled_slots(void) @@ -570,7 +570,7 @@ } while (received && !(hdr & MEI_HDR_IS_COMPLETE) && left > 0); if ((hdr & MEI_HDR_IS_COMPLETE) && received) { - *maxlen = p - (uint8_t *) buff; + *maxlen = p - (uint8_t *)buff; return CSE_TX_RX_SUCCESS; } } diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index f051061..36867be 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -503,7 +503,7 @@ return false; printk(BIOS_DEBUG, "cse_lite: CSE RW partition: offset = 0x%x, size = 0x%x\n", - (uint32_t)start_offset, (uint32_t) size); + (uint32_t)start_offset, (uint32_t)size); return true; } @@ -907,8 +907,8 @@ struct subpart_entry *subpart_entry; struct subpart_entry_manifest_header *man_hdr; - subpart_entry = (struct subpart_entry *) (ptr + SUBPART_HEADER_SZ); - man_hdr = (struct subpart_entry_manifest_header *) (ptr + subpart_entry->offset_bytes); + subpart_entry = (struct subpart_entry *)(ptr + SUBPART_HEADER_SZ); + man_hdr = (struct subpart_entry_manifest_header *)(ptr + subpart_entry->offset_bytes); fw_ver->major = man_hdr->binary_version.major; fw_ver->minor = man_hdr->binary_version.minor; diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index ea365d0..68bde41 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -580,9 +580,9 @@ dw1 = (gpio_cfg >> GPE0_DW_SHIFT(1)) & GPE0_DWX_MASK; dw2 = (gpio_cfg >> GPE0_DW_SHIFT(2)) & GPE0_DWX_MASK; } else { - gpio_cfg |= (uint32_t) dw0 << GPE0_DW_SHIFT(0); - gpio_cfg |= (uint32_t) dw1 << GPE0_DW_SHIFT(1); - gpio_cfg |= (uint32_t) dw2 << GPE0_DW_SHIFT(2); + gpio_cfg |= (uint32_t)dw0 << GPE0_DW_SHIFT(0); + gpio_cfg |= (uint32_t)dw1 << GPE0_DW_SHIFT(1); + gpio_cfg |= (uint32_t)dw2 << GPE0_DW_SHIFT(2); } gpio_cfg_reg = read32p(pmc_bar + GPIO_GPE_CFG) & ~gpio_cfg_mask; diff --git a/src/soc/intel/denverton_ns/pmutil.c b/src/soc/intel/denverton_ns/pmutil.c index 8d670c6..2c9fc57 100644 --- a/src/soc/intel/denverton_ns/pmutil.c +++ b/src/soc/intel/denverton_ns/pmutil.c @@ -93,7 +93,7 @@ /* 4KiB alignment. */ reg32 &= ~0xfff; - return (void *)(uintptr_t) reg32; + return (void *)(uintptr_t)reg32; } void disable_smi(uint32_t mask) diff --git a/src/soc/intel/elkhartlake/bootblock/pch.c b/src/soc/intel/elkhartlake/bootblock/pch.c index 306908f..9541c4b 100644 --- a/src/soc/intel/elkhartlake/bootblock/pch.c +++ b/src/soc/intel/elkhartlake/bootblock/pch.c @@ -46,7 +46,7 @@ pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); /* Enable PWRM in PMC */ - setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN); + setbits32((void *)PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN); } void bootblock_pch_early_init(void) diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c index aacb1e6..c72d4da 100644 --- a/src/soc/intel/elkhartlake/fsp_params.c +++ b/src/soc/intel/elkhartlake/fsp_params.c @@ -269,7 +269,7 @@ /* Use coreboot MP PPI services if Kconfig is enabled */ if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) - params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); + params->CpuMpPpi = (uintptr_t)mp_fill_ppi_services_data(); /* Chipset Lockdown */ if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) { diff --git a/src/soc/intel/elkhartlake/pmutil.c b/src/soc/intel/elkhartlake/pmutil.c index 76a9cd3..072daff 100644 --- a/src/soc/intel/elkhartlake/pmutil.c +++ b/src/soc/intel/elkhartlake/pmutil.c @@ -259,7 +259,7 @@ /* STM Support */ uint16_t get_pmbase(void) { - return (uint16_t) ACPI_BASE_ADDRESS; + return (uint16_t)ACPI_BASE_ADDRESS; } /* diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index 7ab7ed9a..53df105 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -42,7 +42,7 @@ pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); /* Enable PWRM in PMC */ - setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN); + setbits32((void *)PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN); } void bootblock_pch_early_init(void) diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index fa63a3d..a247b79 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -51,7 +51,7 @@ /* Use coreboot MP PPI services if Kconfig is enabled */ if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) - params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); + params->CpuMpPpi = (uintptr_t)mp_fill_ppi_services_data(); mainboard_silicon_init_params(params); diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c index 9297ffd..306709d 100644 --- a/src/soc/intel/icelake/pmutil.c +++ b/src/soc/intel/icelake/pmutil.c @@ -259,7 +259,7 @@ /* STM Support */ uint16_t get_pmbase(void) { - return (uint16_t) ACPI_BASE_ADDRESS; + return (uint16_t)ACPI_BASE_ADDRESS; } /* diff --git a/src/soc/intel/jasperlake/bootblock/pch.c b/src/soc/intel/jasperlake/bootblock/pch.c index 4de63f2..20b09f2 100644 --- a/src/soc/intel/jasperlake/bootblock/pch.c +++ b/src/soc/intel/jasperlake/bootblock/pch.c @@ -46,7 +46,7 @@ pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); /* Enable PWRM in PMC */ - setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN); + setbits32((void *)PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN); } void bootblock_pch_early_init(void) diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index a5bcd55..09be260 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -67,7 +67,7 @@ /* Use coreboot MP PPI services if Kconfig is enabled */ if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) - params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); + params->CpuMpPpi = (uintptr_t)mp_fill_ppi_services_data(); /* Chipset Lockdown */ const bool lockdown_by_fsp = get_lockdown_config() == CHIPSET_LOCKDOWN_FSP; diff --git a/src/soc/intel/jasperlake/pmutil.c b/src/soc/intel/jasperlake/pmutil.c index f2a4c90..23d5fe7 100644 --- a/src/soc/intel/jasperlake/pmutil.c +++ b/src/soc/intel/jasperlake/pmutil.c @@ -259,7 +259,7 @@ /* STM Support */ uint16_t get_pmbase(void) { - return (uint16_t) ACPI_BASE_ADDRESS; + return (uint16_t)ACPI_BASE_ADDRESS; } /* diff --git a/src/soc/intel/meteorlake/bootblock/soc_die.c b/src/soc/intel/meteorlake/bootblock/soc_die.c index 58de3619..f5a3c91 100644 --- a/src/soc/intel/meteorlake/bootblock/soc_die.c +++ b/src/soc/intel/meteorlake/bootblock/soc_die.c @@ -50,7 +50,7 @@ pci_or_config16(PCI_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); /* Enable PWRM in PMC */ - setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN); + setbits32((void *)PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN); } static void soc_die_early_iorange_init(void) diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index 4fe2f63..0a5861f2 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -137,7 +137,7 @@ * Use FSP running MP PPI services to perform CPU feature programming * if Kconfig is enabled */ - s_cfg->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); + s_cfg->CpuMpPpi = (uintptr_t)mp_fill_ppi_services_data(); } else { /* Use coreboot native driver to perform MP init by default */ s_cfg->CpuMpPpi = (uintptr_t)NULL; diff --git a/src/soc/intel/meteorlake/pmutil.c b/src/soc/intel/meteorlake/pmutil.c index 974f966..6f35428 100644 --- a/src/soc/intel/meteorlake/pmutil.c +++ b/src/soc/intel/meteorlake/pmutil.c @@ -244,7 +244,7 @@ /* STM Support */ uint16_t get_pmbase(void) { - return (uint16_t) ACPI_BASE_ADDRESS; + return (uint16_t)ACPI_BASE_ADDRESS; } /* diff --git a/src/soc/intel/quark/acpi.c b/src/soc/intel/quark/acpi.c index 9e41b31..9cabdd6 100644 --- a/src/soc/intel/quark/acpi.c +++ b/src/soc/intel/quark/acpi.c @@ -77,5 +77,5 @@ { struct device *dev = pcidev_on_root(PCI_DEVICE_NUMBER_QNC_LPC, PCI_FUNCTION_NUMBER_QNC_LPC); - return (uint16_t) pci_read_config32(dev, R_QNC_LPC_PM1BLK) & B_QNC_LPC_PM1BLK_MASK; + return (uint16_t)pci_read_config32(dev, R_QNC_LPC_PM1BLK) & B_QNC_LPC_PM1BLK_MASK; } diff --git a/src/soc/intel/quark/memmap.c b/src/soc/intel/quark/memmap.c index 46671b2..60b7938 100644 --- a/src/soc/intel/quark/memmap.c +++ b/src/soc/intel/quark/memmap.c @@ -11,7 +11,7 @@ uintptr_t top_of_low_usable_memory; /* Locate the top of RAM */ - top_of_low_usable_memory = (uintptr_t) cbmem_top(); + top_of_low_usable_memory = (uintptr_t)cbmem_top(); top_of_ram = ALIGN_UP(top_of_low_usable_memory, 16 * MiB); /* Cache postcar and ramstage */ @@ -19,7 +19,7 @@ MTRR_TYPE_WRBACK); /* Cache RMU area */ - postcar_frame_add_mtrr(pcf, (uintptr_t) top_of_low_usable_memory, + postcar_frame_add_mtrr(pcf, (uintptr_t)top_of_low_usable_memory, 0x10000, MTRR_TYPE_WRTHROUGH); /* Cache ESRAM */ diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index d120d1e..70d12e4 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -240,7 +240,7 @@ printk(BIOS_DEBUG, "psys_pmax = %d\n", tconfig->PsysPmax); } - params->GraphicsConfigPtr = (u32) vbt_data; + params->GraphicsConfigPtr = (u32)vbt_data; for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { params->PortUsb20Enable[i] = diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index fe26ebf..d411c76 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -136,12 +136,12 @@ /* 4KiB alignment. */ reg32 &= ~0xfff; - return (void *)(uintptr_t) reg32; + return (void *)(uintptr_t)reg32; } uintptr_t soc_read_pmc_base(void) { - return (uintptr_t) (pmc_mmio_regs()); + return (uintptr_t)(pmc_mmio_regs()); } uint32_t *soc_pmc_etr_addr(void) diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c index 6186734..d203bda 100644 --- a/src/soc/intel/skylake/systemagent.c +++ b/src/soc/intel/skylake/systemagent.c @@ -84,9 +84,9 @@ { msr_t msr; msr = rdmsr(MSR_UNCORE_PRMRR_PHYS_BASE); - *prmrr_base = (uint64_t) msr.hi << 32 | msr.lo; + *prmrr_base = (uint64_t)msr.hi << 32 | msr.lo; msr = rdmsr(MSR_UNCORE_PRMRR_PHYS_MASK); - *prmrr_mask = (uint64_t) msr.hi << 32 | msr.lo; + *prmrr_mask = (uint64_t)msr.hi << 32 | msr.lo; return 0; } diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index 9758dba..fc06873 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -56,7 +56,7 @@ pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); /* Enable PWRM in PMC */ - setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN); + setbits32((void *)PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN); } void bootblock_pch_early_init(void) diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index d7c60be..13c5fc0 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -319,7 +319,7 @@ /* Use coreboot MP PPI services if Kconfig is enabled */ if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) - params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); + params->CpuMpPpi = (uintptr_t)mp_fill_ppi_services_data(); /* D3Hot and D3Cold for TCSS */ params->D3HotEnable = !config->TcssD3HotDisable; diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c index 9aca5c2..b8bf975 100644 --- a/src/soc/intel/tigerlake/pmutil.c +++ b/src/soc/intel/tigerlake/pmutil.c @@ -268,7 +268,7 @@ /* STM Support */ uint16_t get_pmbase(void) { - return (uint16_t) ACPI_BASE_ADDRESS; + return (uint16_t)ACPI_BASE_ADDRESS; } /* diff --git a/src/soc/intel/xeon_sp/cpx/hob_display.c b/src/soc/intel/xeon_sp/cpx/hob_display.c index b3ad455..961f908 100644 --- a/src/soc/intel/xeon_sp/cpx/hob_display.c +++ b/src/soc/intel/xeon_sp/cpx/hob_display.c @@ -226,7 +226,7 @@ if (hob->type != HOB_TYPE_GUID_EXTENSION) return; - guid = (uint8_t *) fsp_hob_header_to_resource(hob); + guid = (uint8_t *)fsp_hob_header_to_resource(hob); if (fsp_guid_compare(guid, fsp_hob_iio_uds_guid)) soc_display_iio_universal_data_hob((const IIO_UDS *)(guid + 16)); diff --git a/src/soc/intel/xeon_sp/nb_acpi.c b/src/soc/intel/xeon_sp/nb_acpi.c index c31fd61..284ddd6 100644 --- a/src/soc/intel/xeon_sp/nb_acpi.c +++ b/src/soc/intel/xeon_sp/nb_acpi.c @@ -49,10 +49,10 @@ for (int e = 0; e < memory_map->numberEntries; ++e) { const struct SystemMemoryMapElement *mem_element = &memory_map->Element[e]; uint64_t addr = - (uint64_t) ((uint64_t)mem_element->BaseAddress << + (uint64_t)((uint64_t)mem_element->BaseAddress << MEM_ADDR_64MB_SHIFT_BITS); uint64_t size = - (uint64_t) ((uint64_t)mem_element->ElementSize << + (uint64_t)((uint64_t)mem_element->ElementSize << MEM_ADDR_64MB_SHIFT_BITS); printk(BIOS_DEBUG, "memory_map %d addr: 0x%llx, BaseAddress: 0x%x, size: 0x%llx, " @@ -81,10 +81,10 @@ srat_mem[mmap_index].type = 1; /* Memory affinity structure */ srat_mem[mmap_index].length = sizeof(acpi_srat_mem_t); - srat_mem[mmap_index].base_address_low = (uint32_t) (addr & 0xffffffff); - srat_mem[mmap_index].base_address_high = (uint32_t) (addr >> 32); - srat_mem[mmap_index].length_low = (uint32_t) (size & 0xffffffff); - srat_mem[mmap_index].length_high = (uint32_t) (size >> 32); + srat_mem[mmap_index].base_address_low = (uint32_t)(addr & 0xffffffff); + srat_mem[mmap_index].base_address_high = (uint32_t)(addr >> 32); + srat_mem[mmap_index].length_low = (uint32_t)(size & 0xffffffff); + srat_mem[mmap_index].length_high = (uint32_t)(size >> 32); srat_mem[mmap_index].proximity_domain = mem_element->SocketId; srat_mem[mmap_index].flags = SRAT_ACPI_MEMORY_ENABLED; if ((mem_element->Type & MEMTYPE_VOLATILE_MASK) == 0) @@ -335,9 +335,9 @@ unsigned long tmp = current; printk(BIOS_DEBUG, "[Reserved Memory Region] PCI Segment Number: 0x%x, Base Address: 0x%x, " "End Address (limit): 0x%x\n", - 0, (uint32_t) ptr, (uint32_t) ((uint32_t) ptr + size - 1)); - current += acpi_create_dmar_rmrr(current, 0, (uint32_t) ptr, - (uint32_t) ((uint32_t) ptr + size - 1)); + 0, (uint32_t)ptr, (uint32_t) ((uint32_t) ptr + size - 1)); + current += acpi_create_dmar_rmrr(current, 0, (uint32_t)ptr, + (uint32_t)((uint32_t) ptr + size - 1)); printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " "PCI Path: 0x%x, 0x%x\n", @@ -416,7 +416,7 @@ /* SRAT */ current = ALIGN_UP(current, 8); printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); - srat = (acpi_srat_t *) current; + srat = (acpi_srat_t *)current; acpi_create_srat(srat, acpi_fill_srat); current += srat->header.length; acpi_add_table(rsdp, srat); @@ -424,7 +424,7 @@ /* SLIT */ current = ALIGN_UP(current, 8); printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); - slit = (acpi_slit_t *) current; + slit = (acpi_slit_t *)current; acpi_create_slit(slit, acpi_fill_slit); current += slit->header.length; acpi_add_table(rsdp, slit); diff --git a/src/soc/intel/xeon_sp/pmutil.c b/src/soc/intel/xeon_sp/pmutil.c index c63285c..3ac5d46 100644 --- a/src/soc/intel/xeon_sp/pmutil.c +++ b/src/soc/intel/xeon_sp/pmutil.c @@ -92,12 +92,12 @@ uint8_t *pmc_mmio_regs(void) { - return (void *)(uintptr_t) pci_read_config32(PCH_DEV_PMC, PWRMBASE); + return (void *)(uintptr_t)pci_read_config32(PCH_DEV_PMC, PWRMBASE); } uintptr_t soc_read_pmc_base(void) { - return (uintptr_t) (pmc_mmio_regs()); + return (uintptr_t)(pmc_mmio_regs()); } uint32_t *soc_pmc_etr_addr(void) diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c index 818dd78..0c8e63a 100644 --- a/src/soc/intel/xeon_sp/util.c +++ b/src/soc/intel/xeon_sp/util.c @@ -277,7 +277,7 @@ const pci_devfn_t dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN); uint32_t reg = pci_s_read_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG); - reg &= (uint32_t) ~rst_cpl_mask; + reg &= (uint32_t)~rst_cpl_mask; reg |= val; /* update BIOS RESET completion bit */ -- To view, visit https://review.coreboot.org/c/coreboot/+/69806 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I098104f32dd7c66d7bb79588ef315a242c3889ba Gerrit-Change-Number: 69806 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: src/southbridge: Remove unnecessary space after casts
by Elyes Haouas (Code Review) 18 Nov '22

18 Nov '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69805 ) Change subject: src/southbridge: Remove unnecessary space after casts ...................................................................... src/southbridge: Remove unnecessary space after casts Change-Id: Ib82968724696110a8d1655928db5b2a665525d20 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/southbridge/intel/bd82x6x/early_rcba.c M src/southbridge/intel/bd82x6x/sata.c M src/southbridge/intel/common/spi.c M src/southbridge/intel/i82801ix/sata.c M src/southbridge/intel/i82801jx/sata.c M src/southbridge/intel/ibexpeak/setup_heci_uma.c 6 files changed, 30 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/69805/1 diff --git a/src/southbridge/intel/bd82x6x/early_rcba.c b/src/southbridge/intel/bd82x6x/early_rcba.c index 49c137a..9daf497 100644 --- a/src/southbridge/intel/bd82x6x/early_rcba.c +++ b/src/southbridge/intel/bd82x6x/early_rcba.c @@ -76,7 +76,7 @@ /* Enable IOAPIC (generic) */ RCBA16(OIC) = 0x0100; /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); + (void)RCBA16(OIC); } void southbridge_rcba_config(void) diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index e243c97..9dc58fd 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -142,8 +142,8 @@ write32(abar + 0x00, reg32); /* PI (Ports implemented) */ write32(abar + 0x0c, config->sata_port_map); - (void) read32(abar + 0x0c); /* Read back 1 */ - (void) read32(abar + 0x0c); /* Read back 2 */ + (void)read32(abar + 0x0c); /* Read back 1 */ + (void)read32(abar + 0x0c); /* Read back 2 */ /* CAP2 (HBA Capabilities Extended)*/ reg32 = read32(abar + 0x24); reg32 &= ~0x00000002; diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 44d283c..1d274e8 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -158,7 +158,7 @@ u8 v = read8(addr); printk(BIOS_DEBUG, "read %2.2x from %4.4x\n", - v, ((unsigned int) addr & 0xffff) - 0xf020); + v, ((unsigned int)addr & 0xffff) - 0xf020); return v; } @@ -167,7 +167,7 @@ u16 v = read16(addr); printk(BIOS_DEBUG, "read %4.4x from %4.4x\n", - v, ((unsigned int) addr & 0xffff) - 0xf020); + v, ((unsigned int)addr & 0xffff) - 0xf020); return v; } @@ -176,7 +176,7 @@ u32 v = read32(addr); printk(BIOS_DEBUG, "read %8.8x from %4.4x\n", - v, ((unsigned int) addr & 0xffff) - 0xf020); + v, ((unsigned int)addr & 0xffff) - 0xf020); return v; } @@ -184,21 +184,21 @@ { write8(addr, b); printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n", - b, ((unsigned int) addr & 0xffff) - 0xf020); + b, ((unsigned int)addr & 0xffff) - 0xf020); } static void writew_(u16 b, void *addr) { write16(addr, b); printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n", - b, ((unsigned int) addr & 0xffff) - 0xf020); + b, ((unsigned int)addr & 0xffff) - 0xf020); } static void writel_(u32 b, void *addr) { write32(addr, b); printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n", - b, ((unsigned int) addr & 0xffff) - 0xf020); + b, ((unsigned int)addr & 0xffff) - 0xf020); } #else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */ @@ -787,8 +787,8 @@ if (addr + len > flash->size) { printk(BIOS_ERR, "Attempt to read %x-%x which is out of chip\n", - (unsigned int) addr, - (unsigned int) addr+(unsigned int) len); + (unsigned int)addr, + (unsigned int)addr+(unsigned int) len); return -1; } @@ -835,7 +835,7 @@ if ((i % 4) == 0) temp32 = 0; - temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8); + temp32 |= ((uint32_t)data[i]) << ((i % 4) * 8); if ((i % 4) == 3) /* 32 bits are full, write them to regs. */ writel_(temp32, cntlr.data + (i - (i % 4))); @@ -856,7 +856,7 @@ if (addr + len > flash->size) { printk(BIOS_ERR, "Attempt to write 0x%x-0x%x which is out of chip\n", - (unsigned int)addr, (unsigned int) (addr+len)); + (unsigned int)addr, (unsigned int)(addr+len)); return -1; } @@ -890,7 +890,7 @@ len -= block_len; } printk(BIOS_DEBUG, "SF: Successfully written %u bytes @ %#x\n", - (unsigned int) (addr - start), start); + (unsigned int)(addr - start), start); return 0; } diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c index 260d76a..7621a4d 100644 --- a/src/southbridge/intel/i82801ix/sata.c +++ b/src/southbridge/intel/i82801ix/sata.c @@ -46,8 +46,8 @@ /* PI (Ports implemented) */ write32(abar + 0x0c, port_map); /* PCH code reads back twice, do we need it, too? */ - (void) read32(abar + 0x0c); /* Read back 1 */ - (void) read32(abar + 0x0c); /* Read back 2 */ + (void)read32(abar + 0x0c); /* Read back 1 */ + (void)read32(abar + 0x0c); /* Read back 2 */ /* VSP (Vendor Specific Register) */ reg32 = read32(abar + 0xa0); diff --git a/src/southbridge/intel/i82801jx/sata.c b/src/southbridge/intel/i82801jx/sata.c index 4e01481..1694d3c 100644 --- a/src/southbridge/intel/i82801jx/sata.c +++ b/src/southbridge/intel/i82801jx/sata.c @@ -45,8 +45,8 @@ /* PI (Ports implemented) */ write32(abar + 0x0c, port_map); /* PCH code reads back twice, do we need it, too? */ - (void) read32(abar + 0x0c); /* Read back 1 */ - (void) read32(abar + 0x0c); /* Read back 2 */ + (void)read32(abar + 0x0c); /* Read back 1 */ + (void)read32(abar + 0x0c); /* Read back 2 */ /* VSP (Vendor Specific Register) */ reg32 = read32(abar + 0xa0); diff --git a/src/southbridge/intel/ibexpeak/setup_heci_uma.c b/src/southbridge/intel/ibexpeak/setup_heci_uma.c index e490573..572e5e7 100644 --- a/src/southbridge/intel/ibexpeak/setup_heci_uma.c +++ b/src/southbridge/intel/ibexpeak/setup_heci_uma.c @@ -97,7 +97,7 @@ csr.raw = read32(DEFAULT_HECIBAR + 0xc); } while (csr.csr.buffer_write_ptr == csr.csr.buffer_read_ptr); - *(u32 *) head = read32(DEFAULT_HECIBAR + 0x8); + *(u32 *)head = read32(DEFAULT_HECIBAR + 0x8); if (!head->length) { write32(DEFAULT_HECIBAR + 0x4, read32(DEFAULT_HECIBAR + 0x4) | 2); *packet_size = 0; @@ -188,7 +188,7 @@ }; u32 reply_size; - send_heci_message((u8 *) &msg, sizeof(msg), 0, 7); + send_heci_message((u8 *)&msg, sizeof(msg), 0, 7); reply_size = sizeof(reply); if (recv_heci_message(&reply, &reply_size) == -1) -- To view, visit https://review.coreboot.org/c/coreboot/+/69805 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib82968724696110a8d1655928db5b2a665525d20 Gerrit-Change-Number: 69805 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 0

[L] Change in coreboot[master]: src/device: Remove unnecessary space after casts
by Elyes Haouas (Code Review) 18 Nov '22

18 Nov '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69804 ) Change subject: src/device: Remove unnecessary space after casts ...................................................................... src/device: Remove unnecessary space after casts Change-Id: I11593245fedc26489e3506d773aaff1ad34188b1 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/device/oprom/realmode/x86.c M src/device/oprom/x86emu/ops.c M src/device/oprom/x86emu/ops2.c M src/device/oprom/x86emu/prim_ops.c M src/device/oprom/x86emu/sys.c M src/device/oprom/yabel/biosemu.c M src/device/oprom/yabel/compat/functions.c M src/device/oprom/yabel/compat/of.h M src/device/oprom/yabel/device.c M src/device/oprom/yabel/device.h M src/device/oprom/yabel/interrupt.c M src/device/oprom/yabel/io.c M src/device/oprom/yabel/mem.c M src/device/oprom/yabel/pmm.c M src/device/oprom/yabel/vbe.c M src/device/pci_device.c M src/device/pci_rom.c 17 files changed, 205 insertions(+), 195 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/69804/1 diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index 7972011..5bfbcaa 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -168,14 +168,14 @@ static void write_idt_stub(void *target, u8 intnum) { unsigned char *codeptr; - codeptr = (unsigned char *) target; + codeptr = (unsigned char *)target; memcpy(codeptr, &__idt_handler, __idt_handler_size); codeptr[3] = intnum; /* modify int# in the code stub. */ } static void setup_realmode_idt(void) { - struct realmode_idt *idts = (struct realmode_idt *) 0; + struct realmode_idt *idts = (struct realmode_idt *)0; int i; /* Copy IDT stub code for each interrupt. This might seem wasteful diff --git a/src/device/oprom/x86emu/ops.c b/src/device/oprom/x86emu/ops.c index eeaa203..0f19f1e 100644 --- a/src/device/oprom/x86emu/ops.c +++ b/src/device/oprom/x86emu/ops.c @@ -1589,7 +1589,7 @@ u32 destval,imm; destval = fetch_data_long(destoffset); - imm = (s8) fetch_byte_imm(); + imm = (s8)fetch_byte_imm(); DECODE_PRINTF2(",%x\n", imm); TRACE_AND_STEP(); destval = (*genop_long_operation[rh]) (destval, imm); @@ -1599,7 +1599,7 @@ u16 destval,imm; destval = fetch_data_word(destoffset); - imm = (s8) fetch_byte_imm(); + imm = (s8)fetch_byte_imm(); DECODE_PRINTF2(",%x\n", imm); TRACE_AND_STEP(); destval = (*genop_word_operation[rh]) (destval, imm); @@ -1611,7 +1611,7 @@ u32 *destreg, imm; destreg = DECODE_RM_LONG_REGISTER(rl); - imm = (s8) fetch_byte_imm(); + imm = (s8)fetch_byte_imm(); DECODE_PRINTF2(",%x\n", imm); TRACE_AND_STEP(); *destreg = (*genop_long_operation[rh]) (*destreg, imm); @@ -1619,7 +1619,7 @@ u16 *destreg, imm; destreg = DECODE_RM_WORD_REGISTER(rl); - imm = (s8) fetch_byte_imm(); + imm = (s8)fetch_byte_imm(); DECODE_PRINTF2(",%x\n", imm); TRACE_AND_STEP(); *destreg = (*genop_word_operation[rh]) (*destreg, imm); @@ -3577,7 +3577,7 @@ START_OF_INSTR(); DECODE_PRINTF("INT 3\n"); - tmp = (u16) mem_access_word(3 * 4 + 2); + tmp = (u16)mem_access_word(3 * 4 + 2); /* access the segment register */ TRACE_AND_STEP(); if (_X86EMU_intrTab[3]) { @@ -4087,8 +4087,8 @@ START_OF_INSTR(); DECODE_PRINTF("LOOPNE\t"); - ip = (s8) fetch_byte_imm(); - ip += (s16) M.x86.R_IP; + ip = (s8)fetch_byte_imm(); + ip += (s16)M.x86.R_IP; DECODE_PRINTF2("%04x\n", ip); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_ADDR) @@ -4111,8 +4111,8 @@ START_OF_INSTR(); DECODE_PRINTF("LOOPE\t"); - ip = (s8) fetch_byte_imm(); - ip += (s16) M.x86.R_IP; + ip = (s8)fetch_byte_imm(); + ip += (s16)M.x86.R_IP; DECODE_PRINTF2("%04x\n", ip); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_ADDR) @@ -4135,8 +4135,8 @@ START_OF_INSTR(); DECODE_PRINTF("LOOP\t"); - ip = (s8) fetch_byte_imm(); - ip += (s16) M.x86.R_IP; + ip = (s8)fetch_byte_imm(); + ip += (s16)M.x86.R_IP; DECODE_PRINTF2("%04x\n", ip); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_ADDR) @@ -4183,7 +4183,7 @@ START_OF_INSTR(); DECODE_PRINTF("IN\t"); - port = (u8) fetch_byte_imm(); + port = (u8)fetch_byte_imm(); DECODE_PRINTF2("%x,AL\n", port); TRACE_AND_STEP(); M.x86.R_AL = (*sys_inb)(port); @@ -4201,7 +4201,7 @@ START_OF_INSTR(); DECODE_PRINTF("IN\t"); - port = (u8) fetch_byte_imm(); + port = (u8)fetch_byte_imm(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF2("EAX,%x\n", port); } else { @@ -4227,7 +4227,7 @@ START_OF_INSTR(); DECODE_PRINTF("OUT\t"); - port = (u8) fetch_byte_imm(); + port = (u8)fetch_byte_imm(); DECODE_PRINTF2("%x,AL\n", port); TRACE_AND_STEP(); (*sys_outb)(port, M.x86.R_AL); @@ -4245,7 +4245,7 @@ START_OF_INSTR(); DECODE_PRINTF("OUT\t"); - port = (u8) fetch_byte_imm(); + port = (u8)fetch_byte_imm(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF2("%x,EAX\n", port); } else { @@ -4273,13 +4273,13 @@ START_OF_INSTR(); DECODE_PRINTF("CALL\t"); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - ip32 = (s32) fetch_long_imm(); - ip32 += (s16) M.x86.R_IP; /* CHECK SIGN */ + ip32 = (s32)fetch_long_imm(); + ip32 += (s16)M.x86.R_IP; /* CHECK SIGN */ DECODE_PRINTF2("%04x\n", (u16)ip32); CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip32, ""); } else { - ip16 = (s16) fetch_word_imm(); - ip16 += (s16) M.x86.R_IP; /* CHECK SIGN */ + ip16 = (s16)fetch_word_imm(); + ip16 += (s16)M.x86.R_IP; /* CHECK SIGN */ DECODE_PRINTF2("%04x\n", ip16); CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip16, ""); } @@ -5192,7 +5192,7 @@ destreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); - M.x86.R_IP = (u16) (*destreg); + M.x86.R_IP = (u16)(*destreg); break; case 5: /* jmp far ptr ... */ DECODE_PRINTF("OPERATION UNDEFINED 0XFF\n"); diff --git a/src/device/oprom/x86emu/ops2.c b/src/device/oprom/x86emu/ops2.c index 6089b1f..76af341 100644 --- a/src/device/oprom/x86emu/ops2.c +++ b/src/device/oprom/x86emu/ops2.c @@ -290,8 +290,8 @@ /* conditional jump to word offset. */ START_OF_INSTR(); cond = x86emu_check_jump_condition(op2 & 0xF); - target = (s16) fetch_word_imm(); - target += (s16) M.x86.R_IP; + target = (s16)fetch_word_imm(); + target += (s16)M.x86.R_IP; DECODE_PRINTF2("%04x\n", target); TRACE_AND_STEP(); if (cond) { diff --git a/src/device/oprom/x86emu/prim_ops.c b/src/device/oprom/x86emu/prim_ops.c index 2350ac1..f5d5780 100644 --- a/src/device/oprom/x86emu/prim_ops.c +++ b/src/device/oprom/x86emu/prim_ops.c @@ -1203,7 +1203,7 @@ CONDITIONAL_SET_FLAG(cf, F_CF); set_szp_flags_8((u8)res); } else { - res = (u8) d; + res = (u8)d; } if (cnt == 1) { @@ -1243,7 +1243,7 @@ CONDITIONAL_SET_FLAG(cf, F_CF); set_szp_flags_16((u16)res); } else { - res = (u16) d; + res = (u16)d; } if (cnt == 1) { @@ -1316,7 +1316,7 @@ CONDITIONAL_SET_FLAG(cf, F_CF); set_szp_flags_8((u8)res); } else { - res = (u8) d; + res = (u8)d; } if (cnt == 1) { @@ -2060,8 +2060,8 @@ x86emu_intr_raise(0); return; } - M.x86.R_AL = (s8) div; - M.x86.R_AH = (s8) mod; + M.x86.R_AL = (s8)div; + M.x86.R_AH = (s8)mod; } /**************************************************************************** diff --git a/src/device/oprom/x86emu/sys.c b/src/device/oprom/x86emu/sys.c index 2f38ce5..28dbd44 100644 --- a/src/device/oprom/x86emu/sys.c +++ b/src/device/oprom/x86emu/sys.c @@ -71,7 +71,7 @@ //printf("%x:%x updating int vector 0x%x\n", // M.x86.R_CS, M.x86.R_IP, addr >> 2); } - retaddr = (u8 *) (M.mem_base + addr); + retaddr = (u8 *)(M.mem_base + addr); return retaddr; } @@ -115,7 +115,7 @@ u8 *ptr; ptr = mem_ptr(addr, 2); - val = *(u16 *) (ptr); + val = *(u16 *)(ptr); DB(if (DEBUG_MEM_TRACE()) printf("%#08x 2 -> %#x\n", addr, val);) @@ -137,7 +137,7 @@ u8 *ptr; ptr = mem_ptr(addr, 4); - val = *(u32 *) (ptr); + val = *(u32 *)(ptr); DB(if (DEBUG_MEM_TRACE()) printf("%#08x 4 -> %#x\n", addr, val);) @@ -157,7 +157,7 @@ u8 *ptr; ptr = mem_ptr(addr, 1); - *(u8 *) (ptr) = val; + *(u8 *)(ptr) = val; DB(if (DEBUG_MEM_TRACE()) printf("%#08x 1 <- %#x\n", addr, val);) @@ -176,7 +176,7 @@ u8 *ptr; ptr = mem_ptr(addr, 2); - *(u16 *) (ptr) = val; + *(u16 *)(ptr) = val; DB(if (DEBUG_MEM_TRACE()) printf("%#08x 2 <- %#x\n", addr, val);) @@ -195,7 +195,7 @@ u8 *ptr; ptr = mem_ptr(addr, 4); - *(u32 *) (ptr) = val; + *(u32 *)(ptr) = val; DB(if (DEBUG_MEM_TRACE()) printf("%#08x 4 <- %#x\n", addr, val);) @@ -386,7 +386,7 @@ ****************************************************************************/ void X86EMU_prepareForInt(int num) { - push_word((u16) M.x86.R_FLG); + push_word((u16)M.x86.R_FLG); CLEAR_FLAG(F_IF); CLEAR_FLAG(F_TF); push_word(M.x86.R_CS); @@ -398,6 +398,6 @@ void X86EMU_setMemBase(void *base, size_t size) { - M.mem_base = (unsigned long) base; + M.mem_base = (unsigned long)base; M.mem_size = size; } diff --git a/src/device/oprom/yabel/biosemu.c b/src/device/oprom/yabel/biosemu.c index d0586c2..92add06 100644 --- a/src/device/oprom/yabel/biosemu.c +++ b/src/device/oprom/yabel/biosemu.c @@ -146,7 +146,7 @@ biosemu_add_special_memory(0, 0x500); // IVT + BDA biosemu_add_special_memory(OPTION_ROM_CODE_SEGMENT << 4, 0x10000); // option ROM - rom_image = (u8 *) bios_device.img_addr; + rom_image = (u8 *)bios_device.img_addr; DEBUG_PRINTF("executing rom_image from %p\n", rom_image); DEBUG_PRINTF("biosmem at %p\n", biosmem); @@ -163,8 +163,8 @@ X86EMU_setMemBase(biosmem, biosmem_size); - DEBUG_PRINTF("membase set: %08x, size: %08x\n", (int) M.mem_base, - (int) M.mem_size); + DEBUG_PRINTF("membase set: %08x, size: %08x\n", (int)M.mem_base, + (int)M.mem_size); // copy expansion ROM image to segment OPTION_ROM_CODE_SEGMENT // NOTE: this sometimes fails, some bytes are 0x00... so we compare diff --git a/src/device/oprom/yabel/compat/functions.c b/src/device/oprom/yabel/compat/functions.c index 5856597..f7d9d75 100644 --- a/src/device/oprom/yabel/compat/functions.c +++ b/src/device/oprom/yabel/compat/functions.c @@ -46,9 +46,9 @@ #if !CONFIG(YABEL_DIRECTHW) #if CONFIG_YABEL_VIRTMEM_LOCATION -u8* vmem = (u8 *) CONFIG_YABEL_VIRTMEM_LOCATION; +u8* vmem = (u8 *)CONFIG_YABEL_VIRTMEM_LOCATION; #else -u8* vmem = (u8 *) (16*1024*1024); /* default to 16MB */ +u8* vmem = (u8 *)(16*1024*1024); /* default to 16MB */ #endif #else u8* vmem = NULL; @@ -79,7 +79,7 @@ "rdtsc" : "=a"(eax), "=d"(edx) : /* no inputs, no clobber */); - act = ((u64) edx << 32) | eax; + act = ((u64)edx << 32) | eax; #endif return act; } diff --git a/src/device/oprom/yabel/compat/of.h b/src/device/oprom/yabel/compat/of.h index 8cec44f..c7d1aef 100644 --- a/src/device/oprom/yabel/compat/of.h +++ b/src/device/oprom/yabel/compat/of.h @@ -34,7 +34,7 @@ #ifndef OF_H #define OF_H #define p32 int -#define p32cast (int) (unsigned long) (void *) +#define p32cast (int)(unsigned long) (void *) #define phandle_t p32 #define ihandle_t p32 diff --git a/src/device/oprom/yabel/device.c b/src/device/oprom/yabel/device.c index 2c98578..17dee99 100644 --- a/src/device/oprom/yabel/device.c +++ b/src/device/oprom/yabel/device.c @@ -315,8 +315,8 @@ bios_device.devfn, 0x0); #endif bios_device.pci_device_id = - (u16) ((pci_config_0 & 0xFFFF0000) >> 16); - bios_device.pci_vendor_id = (u16) (pci_config_0 & 0x0000FFFF); + (u16)((pci_config_0 & 0xFFFF0000) >> 16); + bios_device.pci_vendor_id = (u16)(pci_config_0 & 0x0000FFFF); DEBUG_PRINTF("PCI Device ID: %04x, PCI Vendor ID: %x\n", bios_device.pci_device_id, bios_device.pci_vendor_id); } @@ -354,27 +354,27 @@ return -1; } set_ci(); - u16 rom_signature = in16le((void *) rom_base_addr); + u16 rom_signature = in16le((void *)rom_base_addr); clr_ci(); if (rom_signature != 0xaa55) { printf ("Error: invalid Expansion ROM signature: %02x!\n", - *((u16 *) rom_base_addr)); + *((u16 *)rom_base_addr)); return -1; } set_ci(); // at offset 0x18 is the (16bit little-endian) pointer to the PCI Data Structure - pci_ds_offset = in16le((void *) (rom_base_addr + 0x18)); + pci_ds_offset = in16le((void *)(rom_base_addr + 0x18)); //copy the PCI Data Structure - memcpy(&pci_ds, (void *) (rom_base_addr + pci_ds_offset), + memcpy(&pci_ds, (void *)(rom_base_addr + pci_ds_offset), sizeof(pci_ds)); clr_ci(); #if CONFIG(X86EMU_DEBUG) DEBUG_PRINTF("PCI Data Structure @%lx:\n", rom_base_addr + pci_ds_offset); - dump((void *) &pci_ds, sizeof(pci_ds)); + dump((void *)&pci_ds, sizeof(pci_ds)); #endif - if (strncmp((const char *) pci_ds.signature, "PCIR", 4) != 0) { + if (strncmp((const char *)pci_ds.signature, "PCIR", 4) != 0) { printf("Invalid PCI Data Structure found!\n"); break; } diff --git a/src/device/oprom/yabel/device.h b/src/device/oprom/yabel/device.h index 37440a8..cf0e7a5 100644 --- a/src/device/oprom/yabel/device.h +++ b/src/device/oprom/yabel/device.h @@ -151,7 +151,7 @@ out32le(void *addr, u32 val) { #if ENV_X86 || ENV_ARM || ENV_ARM64 - *((u32*) addr) = cpu_to_le32(val); + *((u32*)addr) = cpu_to_le32(val); #else asm volatile ("stwbrx %0, 0, %1"::"r" (val), "r"(addr)); #endif @@ -162,7 +162,7 @@ { u32 val; #if ENV_X86 || ENV_ARM || ENV_ARM64 - val = cpu_to_le32(*((u32 *) addr)); + val = cpu_to_le32(*((u32 *)addr)); #else asm volatile ("lwbrx %0, 0, %1":"=r" (val):"r"(addr)); #endif @@ -173,7 +173,7 @@ out16le(void *addr, u16 val) { #if ENV_X86 || ENV_ARM || ENV_ARM64 - *((u16*) addr) = cpu_to_le16(val); + *((u16*)addr) = cpu_to_le16(val); #else asm volatile ("sthbrx %0, 0, %1"::"r" (val), "r"(addr)); #endif @@ -184,7 +184,7 @@ { u16 val; #if ENV_X86 || ENV_ARM || ENV_ARM64 - val = cpu_to_le16(*((u16*) addr)); + val = cpu_to_le16(*((u16*)addr)); #else asm volatile ("lhbrx %0, 0, %1":"=r" (val):"r"(addr)); #endif diff --git a/src/device/oprom/yabel/interrupt.c b/src/device/oprom/yabel/interrupt.c index 968e471..f78538d 100644 --- a/src/device/oprom/yabel/interrupt.c +++ b/src/device/oprom/yabel/interrupt.c @@ -55,7 +55,7 @@ DEBUG_PRINTF_INTR("%s(%x): executing interrupt handler @%08x\n", __func__, intNum, my_rdl(intNum * 4)); // push current R_FLG... will be popped by IRET - push_word((u16) M.x86.R_FLG); + push_word((u16)M.x86.R_FLG); CLEAR_FLAG(F_IF); CLEAR_FLAG(F_TF); // push current CS:IP to the stack, will be popped by IRET @@ -232,7 +232,7 @@ u8 char_code = 0; if (*keycode < 256) { scan_code = keycode_table[*keycode]; - char_code = (u8) * keycode & 0xff; + char_code = (u8)* keycode & 0xff; } else { switch (*keycode) { case 0x1b50: @@ -247,7 +247,7 @@ } } //assemble scan/char code in keycode - *keycode = (u64) ((((u16) scan_code) << 8) | char_code); + *keycode = (u64)((((u16) scan_code) << 8) | char_code); } // handle int16 (Keyboard BIOS Interrupt) @@ -262,7 +262,7 @@ // we misuse the ring buffer, we use it as pointer to a u64 that stores // multi-byte keys (e.g. special keys in VT100 terminal) // and as long as a key is available (not 0) we don't read further keys - u64 *keycode = (u64 *) (M.mem_base + 0x41e); + u64 *keycode = (u64 *)(M.mem_base + 0x41e); s8 c; // function number in AH DEBUG_PRINTF_INTR("%s(): Keyboard Interrupt: function: %x.\n", @@ -273,7 +273,7 @@ case 0x00: // get keystroke if (*keycode) { - M.x86.R_AX = (u16) * keycode; + M.x86.R_AX = (u16)* keycode; // clear keycode *keycode = 0; } else { @@ -288,7 +288,7 @@ if (*keycode) { // already read, but not yet taken CLEAR_FLAG(F_ZF); - M.x86.R_AX = (u16) * keycode; + M.x86.R_AX = (u16)* keycode; } else { /* TODO: we need getchar... */ c = -1; //getchar(); @@ -318,7 +318,7 @@ SET_FLAG(F_ZF); } else { CLEAR_FLAG(F_ZF); - M.x86.R_AX = (u16) * keycode; + M.x86.R_AX = (u16)* keycode; //X86EMU_trace_on(); //M.x86.debug &= ~DEBUG_DECODE_NOPRINT_F; } @@ -430,7 +430,7 @@ #if CONFIG(PCI_OPTION_ROM_RUN_YABEL) pci_read_config8(dev, offs); #else - (u8) rtas_pci_config_read(bios_device.puid, 1, + (u8)rtas_pci_config_read(bios_device.puid, 1, bus, devfn, offs); #endif @@ -444,7 +444,7 @@ #if CONFIG(PCI_OPTION_ROM_RUN_YABEL) pci_read_config16(dev, offs); #else - (u16) rtas_pci_config_read(bios_device.puid, 2, + (u16)rtas_pci_config_read(bios_device.puid, 2, bus, devfn, offs); #endif @@ -458,7 +458,7 @@ #if CONFIG(PCI_OPTION_ROM_RUN_YABEL) pci_read_config32(dev, offs); #else - (u32) rtas_pci_config_read(bios_device.puid, 4, + (u32)rtas_pci_config_read(bios_device.puid, 4, bus, devfn, offs); #endif diff --git a/src/device/oprom/yabel/io.c b/src/device/oprom/yabel/io.c index 2a4e6f8..6577ee0 100644 --- a/src/device/oprom/yabel/io.c +++ b/src/device/oprom/yabel/io.c @@ -103,7 +103,7 @@ { unsigned int ret; /* since we are using inb instructions, we need the port number as 16bit value */ - u16 port = (u16)(uintptr_t) addr; + u16 port = (u16)(uintptr_t)addr; switch (sz) { case 1: @@ -125,7 +125,7 @@ static int write_io(void *addr, unsigned int value, size_t sz) { - u16 port = (u16)(uintptr_t) addr; + u16 port = (u16)(uintptr_t)addr; switch (sz) { /* since we are using inb instructions, we need the port number as 16bit value */ case 1: @@ -177,7 +177,7 @@ case 0xCFE: case 0xCFF: // PCI Config Mechanism 1 Ports - return (u8) pci_cfg_read(addr, 1); + return (u8)pci_cfg_read(addr, 1); break; case 0x0a: CHECK_DBG(DEBUG_INTR) { @@ -189,7 +189,7 @@ DEBUG_PRINTF_IO ("%s(%04x) reading from bios_device.io_buffer\n", __func__, addr); - rval = *((u8 *) (bios_device.io_buffer + addr)); + rval = *((u8 *)(bios_device.io_buffer + addr)); DEBUG_PRINTF_IO("%s(%04x) I/O Buffer --> %02x\n", __func__, addr, rval); return rval; @@ -209,11 +209,11 @@ addr); //DEBUG_PRINTF_IO("%s(%04x): translated_addr: %llx\n", __func__, addr, translated_addr); u16 rval; - if ((translated_addr & (u64) 0x1) == 0) { + if ((translated_addr & (u64)0x1) == 0) { // 16 bit aligned access... u16 tempval = read_io((void *)translated_addr, 2); //little endian conversion - rval = in16le((void *) &tempval); + rval = in16le((void *)&tempval); } else { // unaligned access, read single bytes, little-endian rval = (read_io((void *)translated_addr, 1) << 8) @@ -227,14 +227,14 @@ case 0xCFC: case 0xCFE: //PCI Config Mechanism 1 - return (u16) pci_cfg_read(addr, 2); + return (u16)pci_cfg_read(addr, 2); break; default: DEBUG_PRINTF_IO ("%s(%04x) reading from bios_device.io_buffer\n", __func__, addr); u16 rval = - in16le((void *) bios_device.io_buffer + addr); + in16le((void *)bios_device.io_buffer + addr); DEBUG_PRINTF_IO("%s(%04x) I/O Buffer --> %04x\n", __func__, addr, rval); return rval; @@ -254,11 +254,11 @@ addr); //DEBUG_PRINTF_IO("%s(%04x): translated_addr: %llx\n", __func__, addr, translated_addr); u32 rval; - if ((translated_addr & (u64) 0x3) == 0) { + if ((translated_addr & (u64)0x3) == 0) { // 32 bit aligned access... - u32 tempval = read_io((void *) translated_addr, 4); + u32 tempval = read_io((void *)translated_addr, 4); //little endian conversion - rval = in32le((void *) &tempval); + rval = in32le((void *)&tempval); } else { // unaligned access, read single bytes, little-endian rval = (read_io((void *)(translated_addr), 1) << 24) @@ -280,7 +280,7 @@ ("%s(%04x) reading from bios_device.io_buffer\n", __func__, addr); u32 rval = - in32le((void *) bios_device.io_buffer + addr); + in32le((void *)bios_device.io_buffer + addr); DEBUG_PRINTF_IO("%s(%04x) I/O Buffer --> %08x\n", __func__, addr, rval); return rval; @@ -299,7 +299,7 @@ DEBUG_PRINTF_IO("%s(%x, %x): access to Device I/O\n", __func__, addr, val); //DEBUG_PRINTF_IO("%s(%04x): translated_addr: %llx\n", __func__, addr, translated_addr); - write_io((void *) translated_addr, val, 1); + write_io((void *)translated_addr, val, 1); DEBUG_PRINTF_IO("%s(%04x) Device I/O <-- %02x\n", __func__, addr, val); } else { @@ -315,7 +315,7 @@ DEBUG_PRINTF_IO ("%s(%04x,%02x) writing to bios_device.io_buffer\n", __func__, addr, val); - *((u8 *) (bios_device.io_buffer + addr)) = val; + *((u8 *)(bios_device.io_buffer + addr)) = val; break; } } @@ -331,17 +331,17 @@ DEBUG_PRINTF_IO("%s(%x, %x): access to Device I/O\n", __func__, addr, val); //DEBUG_PRINTF_IO("%s(%04x): translated_addr: %llx\n", __func__, addr, translated_addr); - if ((translated_addr & (u64) 0x1) == 0) { + if ((translated_addr & (u64)0x1) == 0) { // little-endian conversion - u16 tempval = in16le((void *) &val); + u16 tempval = in16le((void *)&val); // 16 bit aligned access... - write_io((void *) translated_addr, tempval, 2); + write_io((void *)translated_addr, tempval, 2); } else { // unaligned access, write single bytes, little-endian - write_io(((void *) (translated_addr + 1)), - (u8) ((val & 0xFF00) >> 8), 1); - write_io(((void *) translated_addr), - (u8) (val & 0x00FF), 1); + write_io(((void *)(translated_addr + 1)), + (u8)((val & 0xFF00) >> 8), 1); + write_io(((void *)translated_addr), + (u8)(val & 0x00FF), 1); } DEBUG_PRINTF_IO("%s(%04x) Device I/O <-- %04x\n", __func__, addr, val); @@ -356,7 +356,7 @@ DEBUG_PRINTF_IO ("%s(%04x,%04x) writing to bios_device.io_buffer\n", __func__, addr, val); - out16le((void *) bios_device.io_buffer + addr, val); + out16le((void *)bios_device.io_buffer + addr, val); break; } } @@ -372,21 +372,21 @@ DEBUG_PRINTF_IO("%s(%x, %x): access to Device I/O\n", __func__, addr, val); //DEBUG_PRINTF_IO("%s(%04x): translated_addr: %llx\n", __func__, addr, translated_addr); - if ((translated_addr & (u64) 0x3) == 0) { + if ((translated_addr & (u64)0x3) == 0) { // little-endian conversion - u32 tempval = in32le((void *) &val); + u32 tempval = in32le((void *)&val); // 32 bit aligned access... - write_io((void *) translated_addr, tempval, 4); + write_io((void *)translated_addr, tempval, 4); } else { // unaligned access, write single bytes, little-endian - write_io(((void *) translated_addr + 3), - (u8) ((val & 0xFF000000) >> 24), 1); - write_io(((void *) translated_addr + 2), - (u8) ((val & 0x00FF0000) >> 16), 1); - write_io(((void *) translated_addr + 1), - (u8) ((val & 0x0000FF00) >> 8), 1); - write_io(((void *) translated_addr), - (u8) (val & 0x000000FF), 1); + write_io(((void *)translated_addr + 3), + (u8)((val & 0xFF000000) >> 24), 1); + write_io(((void *)translated_addr + 2), + (u8)((val & 0x00FF0000) >> 16), 1); + write_io(((void *)translated_addr + 1), + (u8)((val & 0x0000FF00) >> 8), 1); + write_io(((void *)translated_addr), + (u8)(val & 0x000000FF), 1); } DEBUG_PRINTF_IO("%s(%04x) Device I/O <-- %08x\n", __func__, addr, val); @@ -400,7 +400,7 @@ DEBUG_PRINTF_IO ("%s(%04x,%08x) writing to bios_device.io_buffer\n", __func__, addr, val); - out32le((void *) bios_device.io_buffer + addr, val); + out32le((void *)bios_device.io_buffer + addr, val); break; } } @@ -462,7 +462,7 @@ break; } } else { - rval = (u32) rtas_pci_config_read(bios_device.puid, size, bus, devfn, offs); + rval = (u32)rtas_pci_config_read(bios_device.puid, size, bus, devfn, offs); } DEBUG_PRINTF_IO @@ -545,9 +545,9 @@ nr_periods = time_diff / period_ticks; // if the number if ticks passed since last call is odd, we toggle bit 4 if ((nr_periods % 2) != 0) { - *((u8 *) (bios_device.io_buffer + 0x61)) ^= 0x10; + *((u8 *)(bios_device.io_buffer + 0x61)) ^= 0x10; } //finally read the value from the io_buffer - return *((u8 *) (bios_device.io_buffer + 0x61)); + return *((u8 *)(bios_device.io_buffer + 0x61)); } #endif diff --git a/src/device/oprom/yabel/mem.c b/src/device/oprom/yabel/mem.c index fa6959e..ae9f165 100644 --- a/src/device/oprom/yabel/mem.c +++ b/src/device/oprom/yabel/mem.c @@ -225,7 +225,7 @@ __func__, addr); //DEBUG_PRINTF_MEM("%s(%08x): translated_addr: %llx\n", __func__, addr, translated_addr); set_ci(); - rval = *((u8 *) translated_addr); + rval = *((u8 *)translated_addr); clr_ci(); DEBUG_PRINTF_MEM("%s(%08x) VGA --> %02x\n", __func__, addr, rval); @@ -237,7 +237,7 @@ HALT_SYS(); } else { /* read from virtual memory */ - rval = *((u8 *) (M.mem_base + addr)); + rval = *((u8 *)(M.mem_base + addr)); DEBUG_CHECK_VMEM_READ(addr, rval); return rval; } @@ -262,19 +262,19 @@ //read bytes a using my_rdb, because of the remapping to BARs //words may not be contiguous in memory, so we need to translate //every address... - rval = ((u8) my_rdb(addr)) | - (((u8) my_rdb(addr + 1)) << 8); + rval = ((u8)my_rdb(addr)) | + (((u8)my_rdb(addr + 1)) << 8); } else { - if ((translated_addr & (u64) 0x1) == 0) { + if ((translated_addr & (u64)0x1) == 0) { // 16 bit aligned access... set_ci(); - rval = in16le((void *) translated_addr); + rval = in16le((void *)translated_addr); clr_ci(); } else { // unaligned access, read single bytes set_ci(); - rval = (*((u8 *) translated_addr)) | - (*((u8 *) translated_addr + 1) << 8); + rval = (*((u8 *)translated_addr)) | + (*((u8 *)translated_addr + 1) << 8); clr_ci(); } } @@ -288,7 +288,7 @@ HALT_SYS(); } else { /* read from virtual memory */ - rval = in16le((void *) (M.mem_base + addr)); + rval = in16le((void *)(M.mem_base + addr)); DEBUG_CHECK_VMEM_READ(addr, rval); return rval; } @@ -313,23 +313,23 @@ //read bytes a using my_rdb, because of the remapping to BARs //dwords may not be contiguous in memory, so we need to translate //every address... - rval = ((u8) my_rdb(addr)) | - (((u8) my_rdb(addr + 1)) << 8) | - (((u8) my_rdb(addr + 2)) << 16) | - (((u8) my_rdb(addr + 3)) << 24); + rval = ((u8)my_rdb(addr)) | + (((u8)my_rdb(addr + 1)) << 8) | + (((u8)my_rdb(addr + 2)) << 16) | + (((u8)my_rdb(addr + 3)) << 24); } else { - if ((translated_addr & (u64) 0x3) == 0) { + if ((translated_addr & (u64)0x3) == 0) { // 32 bit aligned access... set_ci(); - rval = in32le((void *) translated_addr); + rval = in32le((void *)translated_addr); clr_ci(); } else { // unaligned access, read single bytes set_ci(); - rval = (*((u8 *) translated_addr)) | - (*((u8 *) translated_addr + 1) << 8) | - (*((u8 *) translated_addr + 2) << 16) | - (*((u8 *) translated_addr + 3) << 24); + rval = (*((u8 *)translated_addr)) | + (*((u8 *)translated_addr + 1) << 8) | + (*((u8 *)translated_addr + 2) << 16) | + (*((u8 *)translated_addr + 3) << 24); clr_ci(); } } @@ -344,12 +344,12 @@ HALT_SYS(); } else { /* read from virtual memory */ - rval = in32le((void *) (M.mem_base + addr)); + rval = in32le((void *)(M.mem_base + addr)); switch (addr) { case 0x46c: //BDA Time Data, update it, before reading update_time(rval); - rval = in32le((void *) (M.mem_base + addr)); + rval = in32le((void *)(M.mem_base + addr)); break; } DEBUG_CHECK_VMEM_READ(addr, rval); @@ -370,7 +370,7 @@ __func__, addr, val); //DEBUG_PRINTF_MEM("%s(%08x): translated_addr: %llx\n", __func__, addr, translated_addr); set_ci(); - *((u8 *) translated_addr) = val; + *((u8 *)translated_addr) = val; clr_ci(); } else if (addr > M.mem_size) { DEBUG_PRINTF("%s(%08x): Memory Access out of range!\n", @@ -380,7 +380,7 @@ } else { /* write to virtual memory */ DEBUG_CHECK_VMEM_WRITE(addr, val); - *((u8 *) (M.mem_base + addr)) = val; + *((u8 *)(M.mem_base + addr)) = val; } } @@ -400,21 +400,21 @@ //read bytes a using my_rdb, because of the remapping to BARs //words may not be contiguous in memory, so we need to translate //every address... - my_wrb(addr, (u8) (val & 0x00FF)); - my_wrb(addr + 1, (u8) ((val & 0xFF00) >> 8)); + my_wrb(addr, (u8)(val & 0x00FF)); + my_wrb(addr + 1, (u8)((val & 0xFF00) >> 8)); } else { - if ((translated_addr & (u64) 0x1) == 0) { + if ((translated_addr & (u64)0x1) == 0) { // 16 bit aligned access... set_ci(); - out16le((void *) translated_addr, val); + out16le((void *)translated_addr, val); clr_ci(); } else { // unaligned access, write single bytes set_ci(); - *((u8 *) translated_addr) = - (u8) (val & 0x00FF); - *((u8 *) translated_addr + 1) = - (u8) ((val & 0xFF00) >> 8); + *((u8 *)translated_addr) = + (u8)(val & 0x00FF); + *((u8 *)translated_addr + 1) = + (u8)((val & 0xFF00) >> 8); clr_ci(); } } @@ -426,7 +426,7 @@ } else { /* write to virtual memory */ DEBUG_CHECK_VMEM_WRITE(addr, val); - out16le((void *) (M.mem_base + addr), val); + out16le((void *)(M.mem_base + addr), val); } } void @@ -445,27 +445,27 @@ //read bytes a using my_rdb, because of the remapping to BARs //words may not be contiguous in memory, so we need to translate //every address... - my_wrb(addr, (u8) (val & 0x000000FF)); - my_wrb(addr + 1, (u8) ((val & 0x0000FF00) >> 8)); - my_wrb(addr + 2, (u8) ((val & 0x00FF0000) >> 16)); - my_wrb(addr + 3, (u8) ((val & 0xFF000000) >> 24)); + my_wrb(addr, (u8)(val & 0x000000FF)); + my_wrb(addr + 1, (u8)((val & 0x0000FF00) >> 8)); + my_wrb(addr + 2, (u8)((val & 0x00FF0000) >> 16)); + my_wrb(addr + 3, (u8)((val & 0xFF000000) >> 24)); } else { - if ((translated_addr & (u64) 0x3) == 0) { + if ((translated_addr & (u64)0x3) == 0) { // 32 bit aligned access... set_ci(); - out32le((void *) translated_addr, val); + out32le((void *)translated_addr, val); clr_ci(); } else { // unaligned access, write single bytes set_ci(); - *((u8 *) translated_addr) = - (u8) (val & 0x000000FF); - *((u8 *) translated_addr + 1) = - (u8) ((val & 0x0000FF00) >> 8); - *((u8 *) translated_addr + 2) = - (u8) ((val & 0x00FF0000) >> 16); - *((u8 *) translated_addr + 3) = - (u8) ((val & 0xFF000000) >> 24); + *((u8 *)translated_addr) = + (u8)(val & 0x000000FF); + *((u8 *)translated_addr + 1) = + (u8)((val & 0x0000FF00) >> 8); + *((u8 *)translated_addr + 2) = + (u8)((val & 0x00FF0000) >> 16); + *((u8 *)translated_addr + 3) = + (u8)((val & 0xFF000000) >> 24); clr_ci(); } } @@ -477,7 +477,7 @@ } else { /* write to virtual memory */ DEBUG_CHECK_VMEM_WRITE(addr, val); - out32le((void *) (M.mem_base + addr), val); + out32le((void *)(M.mem_base + addr), val); } } #else diff --git a/src/device/oprom/yabel/pmm.c b/src/device/oprom/yabel/pmm.c index e30a86b..b24d4bc 100644 --- a/src/device/oprom/yabel/pmm.c +++ b/src/device/oprom/yabel/pmm.c @@ -65,7 +65,7 @@ { /* setup the PMM structure */ pmm_information_t *pis = - (pmm_information_t *) (M.mem_base + (((u32) segment) << 4) + + (pmm_information_t *)(M.mem_base + (((u32) segment) << 4) + offset); memset(pis, 0, sizeof(pmm_information_t)); /* set signature to $PMM */ @@ -86,14 +86,14 @@ * points to the code... it's that simple ;-) */ out32le(&(pis->entry_point_offset), - (u32) segment << 16 | (u32) (offset + pis->length)); + (u32)segment << 16 | (u32) (offset + pis->length)); /* checksum calculation */ u8 i; u8 checksum = 0; for (i = 0; i < pis->length; i++) { - checksum += *(((u8 *) pis) + i); + checksum += *(((u8 *)pis) + i); } - pis->checksum = ((u8) 0) - checksum; + pis->checksum = ((u8)0) - checksum; CHECK_DBG(DEBUG_PMM) { DEBUG_PRINTF_PMM("PMM Structure:\n"); dump((void *)pis, sizeof(pmm_information_t)); @@ -200,7 +200,7 @@ pmm_alloc->offset = next_offset; pmm_alloc->length = length; /* return the 32bit "physical" address, i.e. combination of segment and offset */ - rval = ((u32) (PMM_CONV_SEGMENT << 16)) | next_offset; + rval = ((u32)(PMM_CONV_SEGMENT << 16)) | next_offset; DEBUG_PRINTF_PMM ("%s: pmmAllocate: allocated memory at %x\n", __func__, rval); @@ -224,7 +224,7 @@ __func__, rval); /* return the 32bit "physical" address, i.e. combination of segment and offset */ rval = - ((u32) (PMM_CONV_SEGMENT << 16)) | + ((u32)(PMM_CONV_SEGMENT << 16)) | pmm_allocation_array[i].offset; } } @@ -240,7 +240,7 @@ /* since argument is the address of the PMM block (including the segment, * we need to remove the segment to get the offset */ - buffer = buffer ^ ((u32) PMM_CONV_SEGMENT << 16); + buffer = buffer ^ ((u32)PMM_CONV_SEGMENT << 16); DEBUG_PRINTF_PMM("%s: pmmDeallocate: PMM segment offset: %x\n", __func__, buffer); i = 0; @@ -292,8 +292,8 @@ exit: /* exit handler of this function, restore registers, put return value in DX:AX */ M.x86 = backup_regs; - M.x86.R_DX = (u16) ((rval >> 16) & 0xFFFF); - M.x86.R_AX = (u16) (rval & 0xFFFF); + M.x86.R_DX = (u16)((rval >> 16) & 0xFFFF); + M.x86.R_AX = (u16)(rval & 0xFFFF); CHECK_DBG(DEBUG_PMM) { DEBUG_PRINTF_PMM("%s: dump of pmm_allocation_array:\n", __func__); @@ -325,7 +325,7 @@ push_word(function); push_long(0); /* This is the return address for the ABI, unused in this implementation */ pmm_handleInt(); - addr = ((u32) M.x86.R_DX << 16) | M.x86.R_AX; + addr = ((u32)M.x86.R_DX << 16) | M.x86.R_AX; DEBUG_PRINTF_PMM("%s: allocated memory at: %04x:%04x\n", __func__, M.x86.R_DX, M.x86.R_AX); function = 1; /* pmmFind */ @@ -355,7 +355,7 @@ push_word(function); push_long(0); /* This is the return address for the ABI, unused in this implementation */ pmm_handleInt(); - addr = ((u32) M.x86.R_DX << 16) | M.x86.R_AX; + addr = ((u32)M.x86.R_DX << 16) | M.x86.R_AX; DEBUG_PRINTF_PMM("%s: allocated memory at: %04x:%04x\n", __func__, M.x86.R_DX, M.x86.R_AX); function = 0; /* pmmAllocate */ @@ -370,7 +370,7 @@ push_long(0); /* This is the return address for the ABI, unused in this implementation */ pmm_handleInt(); /* the address should be aligned to 0x800, so probably it is at offset 0x1800... */ - addr = ((u32) M.x86.R_DX << 16) | M.x86.R_AX; + addr = ((u32)M.x86.R_DX << 16) | M.x86.R_AX; DEBUG_PRINTF_PMM("%s: allocated memory at: %04x:%04x\n", __func__, M.x86.R_DX, M.x86.R_AX); function = 1; /* pmmFind */ @@ -378,7 +378,7 @@ push_word(function); push_long(0); /* This is the return address for the ABI, unused in this implementation */ pmm_handleInt(); - addr = ((u32) M.x86.R_DX << 16) | M.x86.R_AX; + addr = ((u32)M.x86.R_DX << 16) | M.x86.R_AX; function = 2; /* pmmDeallocate */ push_long(addr); push_word(function); @@ -393,7 +393,7 @@ push_word(function); push_long(0); /* This is the return address for the ABI, unused in this implementation */ pmm_handleInt(); - addr = ((u32) M.x86.R_DX << 16) | M.x86.R_AX; + addr = ((u32)M.x86.R_DX << 16) | M.x86.R_AX; function = 2; /* pmmDeallocate */ push_long(addr); push_word(function); @@ -414,7 +414,7 @@ push_word(function); push_long(0); /* This is the return address for the ABI, unused in this implementation */ pmm_handleInt(); - length = ((u32) M.x86.R_DX << 16) | M.x86.R_AX; + length = ((u32)M.x86.R_DX << 16) | M.x86.R_AX; length /= 16; /* length in paragraphs */ DEBUG_PRINTF_PMM("%s: largest possible length: %08x\n", __func__, length); @@ -427,7 +427,7 @@ push_word(function); push_long(0); /* This is the return address for the ABI, unused in this implementation */ pmm_handleInt(); - addr = ((u32) M.x86.R_DX << 16) | M.x86.R_AX; + addr = ((u32)M.x86.R_DX << 16) | M.x86.R_AX; DEBUG_PRINTF_PMM("%s: allocated memory at: %04x:%04x\n", __func__, M.x86.R_DX, M.x86.R_AX); function = 0; /* pmmAllocate */ @@ -442,7 +442,7 @@ push_long(0); /* This is the return address for the ABI, unused in this implementation */ pmm_handleInt(); /* this should fail, so 0x0 should be returned */ - addr = ((u32) M.x86.R_DX << 16) | M.x86.R_AX; + addr = ((u32)M.x86.R_DX << 16) | M.x86.R_AX; DEBUG_PRINTF_PMM ("%s: allocated memory at: %04x:%04x expected: 0000:0000\n", __func__, M.x86.R_DX, M.x86.R_AX); @@ -452,7 +452,7 @@ push_word(function); push_long(0); /* This is the return address for the ABI, unused in this implementation */ pmm_handleInt(); - addr = ((u32) M.x86.R_DX << 16) | M.x86.R_AX; + addr = ((u32)M.x86.R_DX << 16) | M.x86.R_AX; function = 2; /* pmmDeallocate */ push_long(addr); push_word(function); diff --git a/src/device/oprom/yabel/vbe.c b/src/device/oprom/yabel/vbe.c index 5f03e19..9ce284e 100644 --- a/src/device/oprom/yabel/vbe.c +++ b/src/device/oprom/yabel/vbe.c @@ -143,7 +143,7 @@ // offset 14: 32 bit le containing segment:offset of supported video mode table u16 *video_mode_ptr; video_mode_ptr = - (u16 *) (biosmem + + (u16 *)(biosmem + ((in16le(vbe_info_buffer + 16) << 4) + in16le(vbe_info_buffer + 14))); u32 i = 0; @@ -486,7 +486,7 @@ // byte[6] = monitor port number for DDC requests ("only" one byte... so lets hope we never have more than 255 monitors... // byte[7:8] = max. screen width (OF may want to limit this) // byte[9] = required color depth in bpp - if (strncmp((char *) input.signature, "DDC", 4) != 0) { + if (strncmp((char *)input.signature, "DDC", 4) != 0) { printf ("%s: Invalid input signature! expected: %s, is: %s\n", __func__, "DDC", input.signature); @@ -495,7 +495,7 @@ if (input.size_reserved != sizeof(screen_info_t)) { printf ("%s: Size of return struct is wrong, required: %d, available: %d\n", - __func__, (int) sizeof(screen_info_t), + __func__, (int)sizeof(screen_info_t), input.size_reserved); return -1; } @@ -648,9 +648,9 @@ (r * mc_size * mc_size) + (g * mc_size) + b; curr_color = 0; - curr_color |= ((u32) mixed_color_values[r]) << 16; //red value - curr_color |= ((u32) mixed_color_values[g]) << 8; //green value - curr_color |= (u32) mixed_color_values[b]; //blue value + curr_color |= ((u32)mixed_color_values[r]) << 16; //red value + curr_color |= ((u32)mixed_color_values[g]) << 8; //green value + curr_color |= (u32)mixed_color_values[b]; //blue value vbe_set_color(curr_color_index, curr_color); } @@ -661,21 +661,21 @@ // red for (r = 0; r < prim_size; r++) { curr_color_index = mc_size * mc_size * mc_size + r; - curr_color = ((u32) primary_color_values[r]) << 16; + curr_color = ((u32)primary_color_values[r]) << 16; vbe_set_color(curr_color_index, curr_color); } //green for (g = 0; g < prim_size; g++) { curr_color_index = mc_size * mc_size * mc_size + prim_size + g; - curr_color = ((u32) primary_color_values[g]) << 8; + curr_color = ((u32)primary_color_values[g]) << 8; vbe_set_color(curr_color_index, curr_color); } //blue for (b = 0; b < prim_size; b++) { curr_color_index = mc_size * mc_size * mc_size + prim_size * 2 + b; - curr_color = (u32) primary_color_values[b]; + curr_color = (u32)primary_color_values[b]; vbe_set_color(curr_color_index, curr_color); } // 10 shades of grey @@ -683,9 +683,9 @@ curr_color_index = mc_size * mc_size * mc_size + prim_size * 3 + i; curr_color = 0; - curr_color |= ((u32) primary_color_values[i]) << 16; //red - curr_color |= ((u32) primary_color_values[i]) << 8; //green - curr_color |= ((u32) primary_color_values[i]); //blue + curr_color |= ((u32)primary_color_values[i]) << 16; //red + curr_color |= ((u32)primary_color_values[i]) << 8; //green + curr_color |= ((u32)primary_color_values[i]); //blue vbe_set_color(curr_color_index, curr_color); } diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 8651586..9de2946 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -108,7 +108,7 @@ PCI_BASE_ADDRESS_MEM_LIMIT_64)) { /* Find the high bits that move. */ moving |= - ((resource_t) pci_moving_config32(dev, index + 4)) << 32; + ((resource_t)pci_moving_config32(dev, index + 4)) << 32; } /* Find the resource constraints. @@ -496,13 +496,13 @@ resource_t moving_base, moving_limit, moving; /* See if the bridge I/O resources are implemented. */ - moving_base = ((u32) pci_moving_config8(dev, PCI_IO_BASE)) << 8; + moving_base = ((u32)pci_moving_config8(dev, PCI_IO_BASE)) << 8; moving_base |= - ((u32) pci_moving_config16(dev, PCI_IO_BASE_UPPER16)) << 16; + ((u32)pci_moving_config16(dev, PCI_IO_BASE_UPPER16)) << 16; - moving_limit = ((u32) pci_moving_config8(dev, PCI_IO_LIMIT)) << 8; + moving_limit = ((u32)pci_moving_config8(dev, PCI_IO_LIMIT)) << 8; moving_limit |= - ((u32) pci_moving_config16(dev, PCI_IO_LIMIT_UPPER16)) << 16; + ((u32)pci_moving_config16(dev, PCI_IO_LIMIT_UPPER16)) << 16; moving = moving_base & moving_limit; @@ -511,14 +511,14 @@ /* See if the bridge prefmem resources are implemented. */ moving_base = - ((resource_t) pci_moving_config16(dev, PCI_PREF_MEMORY_BASE)) << 16; + ((resource_t)pci_moving_config16(dev, PCI_PREF_MEMORY_BASE)) << 16; moving_base |= - ((resource_t) pci_moving_config32(dev, PCI_PREF_BASE_UPPER32)) << 32; + ((resource_t)pci_moving_config32(dev, PCI_PREF_BASE_UPPER32)) << 32; moving_limit = - ((resource_t) pci_moving_config16(dev, PCI_PREF_MEMORY_LIMIT)) << 16; + ((resource_t)pci_moving_config16(dev, PCI_PREF_MEMORY_LIMIT)) << 16; moving_limit |= - ((resource_t) pci_moving_config32(dev, PCI_PREF_LIMIT_UPPER32)) << 32; + ((resource_t)pci_moving_config32(dev, PCI_PREF_LIMIT_UPPER32)) << 32; moving = moving_base & moving_limit; /* Initialize the prefetchable memory constraints on the current bus. */ @@ -526,8 +526,8 @@ IORESOURCE_MEM | IORESOURCE_PREFETCH); /* See if the bridge mem resources are implemented. */ - moving_base = ((u32) pci_moving_config16(dev, PCI_MEMORY_BASE)) << 16; - moving_limit = ((u32) pci_moving_config16(dev, PCI_MEMORY_LIMIT)) << 16; + moving_base = ((u32)pci_moving_config16(dev, PCI_MEMORY_BASE)) << 16; + moving_limit = ((u32)pci_moving_config16(dev, PCI_MEMORY_LIMIT)) << 16; moving = moving_base & moving_limit; diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index b8dafd1..8480626 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -159,10 +159,10 @@ do { /* Get next image. */ - rom_header = (struct rom_header *)((void *) rom_header + rom_header = (struct rom_header *)((void *)rom_header + image_size); - rom_data = (struct pci_data *)((void *) rom_header + rom_data = (struct pci_data *)((void *)rom_header + le32_to_cpu(rom_header->data)); image_size = le32_to_cpu(rom_data->ilen) * 512; @@ -190,7 +190,7 @@ memcpy((void *)PCI_VGA_RAM_IMAGE_START, rom_header, rom_size); } - return (struct rom_header *) (PCI_VGA_RAM_IMAGE_START); + return (struct rom_header *)(PCI_VGA_RAM_IMAGE_START); } printk(BIOS_DEBUG, "Copying non-VGA ROM image from %p to %p, 0x%x bytes\n", @@ -198,7 +198,7 @@ memcpy(pci_ram_image_start, rom_header, rom_size); pci_ram_image_start += rom_size; - return (struct rom_header *) (pci_ram_image_start-rom_size); + return (struct rom_header *)(pci_ram_image_start-rom_size); } /* ACPI */ -- To view, visit https://review.coreboot.org/c/coreboot/+/69804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11593245fedc26489e3506d773aaff1ad34188b1 Gerrit-Change-Number: 69804 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: src/drivers: Remove unnecessary space after casts
by Elyes Haouas (Code Review) 18 Nov '22

18 Nov '22

Attention is currently required from: Christian Walter, Andrey Petrov. Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69803 ) Change subject: src/drivers: Remove unnecessary space after casts ...................................................................... src/drivers: Remove unnecessary space after casts Change-Id: I16689da893b5a0c3254364759d435281cb3e1caf Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/drivers/amd/agesa/heapmanager.c M src/drivers/aspeed/common/ast_post.c M src/drivers/i2c/ptn3460/ptn3460.c M src/drivers/i2c/tpm/tis.c M src/drivers/intel/fsp2_0/hand_off_block.c M src/drivers/intel/fsp2_0/silicon_init.c M src/drivers/ipmi/ipmi_fru.c M src/drivers/ipmi/ipmi_ops.c M src/drivers/ipmi/ocp/ipmi_ocp.c M src/drivers/ipmi/ocp/ipmi_ocp_romstage.c M src/drivers/ipmi/supermicro_oem.c M src/drivers/net/ne2k.c M src/drivers/pc80/vga/vga.c M src/drivers/pc80/vga/vga_io.c 14 files changed, 55 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/69803/1 diff --git a/src/drivers/amd/agesa/heapmanager.c b/src/drivers/amd/agesa/heapmanager.c index 26947f1..8a82efe 100644 --- a/src/drivers/amd/agesa/heapmanager.c +++ b/src/drivers/amd/agesa/heapmanager.c @@ -42,7 +42,7 @@ memset(base, 0, BIOS_HEAP_SIZE); printk(BIOS_DEBUG, "Wiped HEAP at [%08x - %08x]\n", - (unsigned int)(uintptr_t)base, (unsigned int)(uintptr_t) base + BIOS_HEAP_SIZE - 1); + (unsigned int)(uintptr_t)base, (unsigned int)(uintptr_t)base + BIOS_HEAP_SIZE - 1); } #if defined(HEAP_CALLOUT_RUNTIME) && ENV_RAMSTAGE @@ -345,7 +345,7 @@ } } - AllocParams->BufferPointer = (UINT8 *)((UINT8 *) AllocNodePtr + sizeof(BIOS_BUFFER_NODE)); + AllocParams->BufferPointer = (UINT8 *)((UINT8 *)AllocNodePtr + sizeof(BIOS_BUFFER_NODE)); AllocParams->BufferLength = AllocNodePtr->BufferSize; return AGESA_SUCCESS; diff --git a/src/drivers/aspeed/common/ast_post.c b/src/drivers/aspeed/common/ast_post.c index 08bc42c..856e4e5 100644 --- a/src/drivers/aspeed/common/ast_post.c +++ b/src/drivers/aspeed/common/ast_post.c @@ -740,9 +740,9 @@ passcnt[dqsip]++; tag[dqsip][dlli] = 'P'; if (dlli < pass[dqidly][dqsip][0]) - pass[dqidly][dqsip][0] = (u16) dlli; + pass[dqidly][dqsip][0] = (u16)dlli; if (dlli > pass[dqidly][dqsip][1]) - pass[dqidly][dqsip][1] = (u16) dlli; + pass[dqidly][dqsip][1] = (u16)dlli; } else if (passcnt[dqsip] >= 5) break; else { diff --git a/src/drivers/i2c/ptn3460/ptn3460.c b/src/drivers/i2c/ptn3460/ptn3460.c index 25ed98a..46719dc 100644 --- a/src/drivers/i2c/ptn3460/ptn3460.c +++ b/src/drivers/i2c/ptn3460/ptn3460.c @@ -63,7 +63,7 @@ static void ptn3460_init(struct device *dev) { struct ptn_3460_config cfg; - uint8_t edid_data[PTN_EDID_LEN], edid_tab, *ptr = (uint8_t *) &cfg; + uint8_t edid_data[PTN_EDID_LEN], edid_tab, *ptr = (uint8_t *)&cfg; int i, val; /* Guard against re-initialization of the device */ @@ -108,7 +108,7 @@ /* Mainboard can modify the configuration data. Write back configuration data to PTN3460 if modified by mainboard */ if (mb_adjust_cfg(&cfg) == PTN_CFG_MODIFIED) { - ptr = (uint8_t *) &cfg; + ptr = (uint8_t *)&cfg; for (i = 0; i < sizeof(struct ptn_3460_config); i++) { val = i2c_dev_writeb_at(dev, PTN_CONFIG_OFF + i, *ptr++); if (val < 0) { diff --git a/src/drivers/i2c/tpm/tis.c b/src/drivers/i2c/tpm/tis.c index 80de2df..ea8cf3d 100644 --- a/src/drivers/i2c/tpm/tis.c +++ b/src/drivers/i2c/tpm/tis.c @@ -78,7 +78,7 @@ } ASSERT(chip.vendor.send); - rc = chip.vendor.send(&chip, (uint8_t *) sbuf, count); + rc = chip.vendor.send(&chip, (uint8_t *)sbuf, count); if (rc < 0) { printk(BIOS_DEBUG, "%s: tpm_send error\n", __func__); goto out; @@ -111,7 +111,7 @@ out_recv: - rc = chip.vendor.recv(&chip, (uint8_t *) rbuf, rbufsiz); + rc = chip.vendor.recv(&chip, (uint8_t *)rbuf, rbufsiz); if (rc < 0) printk(BIOS_DEBUG, "%s: tpm_recv: error %d\n", __func__, rc); out: diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index 2ded33699..40f6336 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -261,14 +261,14 @@ tcount = fvih->Count; #elif CONFIG(DISPLAY_FSP_VERSION_INFO_2) - uint8_t *hobstart = (uint8_t *) hob; + uint8_t *hobstart = (uint8_t *)hob; hobstart += sizeof(EFI_HOB_GUID_TYPE); const SMBIOS_TABLE_TYPE_OEM_INTEL_FVI *stfvi = (SMBIOS_TABLE_TYPE_OEM_INTEL_FVI *)hobstart; const INTEL_FIRMWARE_VERSION_INFO *fvi; - str_ptr = ((char *) &(stfvi->Fvi[0])) + + str_ptr = ((char *)&(stfvi->Fvi[0])) + (stfvi->Count * sizeof(INTEL_FIRMWARE_VERSION_INFO)); tcount = stfvi->Count; fvi = &stfvi->Fvi[0]; diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 87f77a2..678892a 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -96,7 +96,7 @@ struct fsp_multi_phase_params multi_phase_params; struct fsp_multi_phase_get_number_of_phases_params multi_phase_get_number; - supd = (FSPS_UPD *) (uintptr_t)(hdr->cfg_region_offset + hdr->image_base); + supd = (FSPS_UPD *)(uintptr_t)(hdr->cfg_region_offset + hdr->image_base); fsp_verify_upd_header_signature(supd->FspUpdHeader.Signature, FSPS_UPD_SIGNATURE); @@ -127,7 +127,7 @@ soc_load_logo(upd); /* Call SiliconInit */ - silicon_init = (void *) (uintptr_t)(hdr->image_base + + silicon_init = (void *)(uintptr_t)(hdr->image_base + hdr->fsp_silicon_init_entry_offset); fsp_debug_before_silicon_init(silicon_init, supd, upd); @@ -165,7 +165,7 @@ return; /* Call MultiPhaseSiInit */ - multi_phase_si_init = (void *) (uintptr_t)(hdr->image_base + + multi_phase_si_init = (void *)(uintptr_t)(hdr->image_base + hdr->fsp_multi_phase_si_init_entry_offset); /* Implementing multi_phase_si_init() is optional as per FSP 2.2 spec */ diff --git a/src/drivers/ipmi/ipmi_fru.c b/src/drivers/ipmi/ipmi_fru.c index f165307..844eb8e 100644 --- a/src/drivers/ipmi/ipmi_fru.c +++ b/src/drivers/ipmi/ipmi_fru.c @@ -36,8 +36,8 @@ while (retry_count <= MAX_FRU_BUSY_RETRY) { ret = ipmi_message(port, IPMI_NETFN_STORAGE, 0x0, - IPMI_READ_FRU_DATA, (const unsigned char *) req, - sizeof(*req), (unsigned char *) &rsp, sizeof(rsp)); + IPMI_READ_FRU_DATA, (const unsigned char *)req, + sizeof(*req), (unsigned char *)&rsp, sizeof(rsp)); if (rsp.resp.completion_code == 0x81) { /* Device is busy */ if (retry_count == MAX_FRU_BUSY_RETRY) { diff --git a/src/drivers/ipmi/ipmi_ops.c b/src/drivers/ipmi/ipmi_ops.c index d9b3256..18547c5 100644 --- a/src/drivers/ipmi/ipmi_ops.c +++ b/src/drivers/ipmi/ipmi_ops.c @@ -21,8 +21,8 @@ req.initial_countdown_val = countdown; ret = ipmi_message(port, IPMI_NETFN_APPLICATION, 0x0, IPMI_BMC_SET_WDG_TIMER, - (const unsigned char *) &req, sizeof(req), - (unsigned char *) &rsp, sizeof(rsp)); + (const unsigned char *)&req, sizeof(req), + (unsigned char *)&rsp, sizeof(rsp)); if (ret < sizeof(struct ipmi_rsp) || rsp.completion_code) { printk(BIOS_ERR, "IPMI: %s set wdt command failed " @@ -35,7 +35,7 @@ /* Reset command to start timer */ ret = ipmi_message(port, IPMI_NETFN_APPLICATION, 0x0, IPMI_BMC_RESET_WDG_TIMER, NULL, 0, - (unsigned char *) &rsp, sizeof(rsp)); + (unsigned char *)&rsp, sizeof(rsp)); if (ret < sizeof(struct ipmi_rsp) || rsp.completion_code) { printk(BIOS_ERR, "IPMI: %s reset wdt command failed " @@ -59,7 +59,7 @@ /* Get current timer first */ ret = ipmi_message(port, IPMI_NETFN_APPLICATION, 0x0, IPMI_BMC_GET_WDG_TIMER, NULL, 0, - (unsigned char *) &rsp, sizeof(rsp)); + (unsigned char *)&rsp, sizeof(rsp)); if (ret < sizeof(struct ipmi_rsp) || rsp.resp.completion_code) { printk(BIOS_ERR, "IPMI: %s get wdt command failed " @@ -79,8 +79,8 @@ req = rsp.data; ret = ipmi_message(port, IPMI_NETFN_APPLICATION, 0x0, IPMI_BMC_SET_WDG_TIMER, - (const unsigned char *) &req, sizeof(req), - (unsigned char *) &resp, sizeof(resp)); + (const unsigned char *)&req, sizeof(req), + (unsigned char *)&resp, sizeof(resp)); if (ret < sizeof(struct ipmi_rsp) || resp.completion_code) { printk(BIOS_ERR, "IPMI: %s set wdt command stop timer failed " @@ -107,7 +107,7 @@ ret = ipmi_message(port, IPMI_NETFN_APPLICATION, 0x0, IPMI_BMC_GET_SYSTEM_GUID, NULL, 0, - (unsigned char *) &rsp, sizeof(rsp)); + (unsigned char *)&rsp, sizeof(rsp)); if (ret < sizeof(struct ipmi_rsp) || rsp.resp.completion_code) { printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n", @@ -130,8 +130,8 @@ } ret = ipmi_message(port, IPMI_NETFN_STORAGE, 0x0, - IPMI_ADD_SEL_ENTRY, (const unsigned char *) sel, - 16, (unsigned char *) &rsp, sizeof(rsp)); + IPMI_ADD_SEL_ENTRY, (const unsigned char *)sel, + 16, (unsigned char *)&rsp, sizeof(rsp)); if (ret < sizeof(struct ipmi_rsp) || rsp.resp.completion_code) { printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n", diff --git a/src/drivers/ipmi/ocp/ipmi_ocp.c b/src/drivers/ipmi/ocp/ipmi_ocp.c index 9f583be..e75edca 100644 --- a/src/drivers/ipmi/ocp/ipmi_ocp.c +++ b/src/drivers/ipmi/ocp/ipmi_ocp.c @@ -29,8 +29,8 @@ req.cpu1_hi = xeon_sp_ppin[1].hi; } ret = ipmi_message(dev->path.pnp.port, IPMI_NETFN_OEM, 0x0, IPMI_OEM_SET_PPIN, - (const unsigned char *) &req, sizeof(req), - (unsigned char *) &rsp, sizeof(rsp)); + (const unsigned char *)&req, sizeof(req), + (unsigned char *)&rsp, sizeof(rsp)); if (ret < sizeof(struct ipmi_rsp) || rsp.completion_code) { printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n", diff --git a/src/drivers/ipmi/ocp/ipmi_ocp_romstage.c b/src/drivers/ipmi/ocp/ipmi_ocp_romstage.c index 7b0b9ea..8ef379e 100644 --- a/src/drivers/ipmi/ocp/ipmi_ocp_romstage.c +++ b/src/drivers/ipmi/ocp/ipmi_ocp_romstage.c @@ -11,7 +11,7 @@ struct ipmi_rsp rsp; ret = ipmi_message(port, IPMI_NETFN_OEM, 0x0, - IPMI_BMC_SET_POST_START, NULL, 0, (u8 *) &rsp, + IPMI_BMC_SET_POST_START, NULL, 0, (u8 *)&rsp, sizeof(rsp)); if (ret < sizeof(struct ipmi_rsp) || rsp.completion_code) { @@ -45,7 +45,7 @@ ret = ipmi_message(CONFIG_BMC_KCS_BASE, IPMI_NETFN_OEM, 0x0, IPMI_OEM_GET_BIOS_BOOT_ORDER, NULL, 0, - (unsigned char *) &rsp, sizeof(rsp)); + (unsigned char *)&rsp, sizeof(rsp)); if (ret < sizeof(struct ipmi_rsp) || rsp.resp.completion_code) { printk(BIOS_ERR, "IPMI: %s command failed (read ret=%d resp=0x%x)\n", @@ -58,8 +58,8 @@ SET_CMOS_AND_VALID_BIT(req.boot_mode); ret = ipmi_message(CONFIG_BMC_KCS_BASE, IPMI_NETFN_OEM, 0x0, IPMI_OEM_SET_BIOS_BOOT_ORDER, - (const unsigned char *) &req, sizeof(req), - (unsigned char *) &rsp, sizeof(rsp)); + (const unsigned char *)&req, sizeof(req), + (unsigned char *)&rsp, sizeof(rsp)); if (ret < sizeof(struct ipmi_rsp) || rsp.resp.completion_code) { printk(BIOS_ERR, "IPMI: %s command failed (sent ret=%d resp=0x%x)\n", diff --git a/src/drivers/ipmi/supermicro_oem.c b/src/drivers/ipmi/supermicro_oem.c index 7af4e3b..c63da5f 100644 --- a/src/drivers/ipmi/supermicro_oem.c +++ b/src/drivers/ipmi/supermicro_oem.c @@ -36,8 +36,8 @@ bios_ver.ver = IPMI_LUN0_AC_SET_BIOS_VER; ret = ipmi_message(kcs_port, IPMI_NETFN_OEM, 0, IPMI_LUN0_SET_BIOS_STRING, - (const unsigned char *) &bios_ver, sizeof(bios_ver), - (unsigned char *) &rsp, sizeof(rsp)); + (const unsigned char *)&bios_ver, sizeof(bios_ver), + (unsigned char *)&rsp, sizeof(rsp)); if (ret < sizeof(rsp) || rsp.completion_code) { printk(BIOS_ERR, "BMC_IPMI: %s command failed (ret=%d resp=0x%x)\n", __func__, ret, rsp.completion_code); @@ -55,8 +55,8 @@ bios_ver.ver = IPMI_LUN0_AC_SET_BIOS_DATE; ret = ipmi_message(kcs_port, IPMI_NETFN_OEM, 0, IPMI_LUN0_SET_BIOS_STRING, - (const unsigned char *) &bios_ver, sizeof(bios_ver), - (unsigned char *) &rsp, sizeof(rsp)); + (const unsigned char *)&bios_ver, sizeof(bios_ver), + (unsigned char *)&rsp, sizeof(rsp)); if (ret < sizeof(rsp) || rsp.completion_code) { printk(BIOS_ERR, "BMC_IPMI: %s command failed (ret=%d resp=0x%x)\n", __func__, ret, rsp.completion_code); diff --git a/src/drivers/net/ne2k.c b/src/drivers/net/ne2k.c index 235c909..e0dc58b 100644 --- a/src/drivers/net/ne2k.c +++ b/src/drivers/net/ne2k.c @@ -281,7 +281,7 @@ c = inb(eth_nic_base + NE_ASIC_OFFSET + NE_RESET); outb(c, eth_nic_base + NE_ASIC_OFFSET + NE_RESET); - (void) inb(0x84); + (void)inb(0x84); outb(D8390_COMMAND_STP | D8390_COMMAND_RD2, eth_nic_base + D8390_P0_COMMAND); outb(D8390_RCR_MON, eth_nic_base + D8390_P0_RCR); diff --git a/src/drivers/pc80/vga/vga.c b/src/drivers/pc80/vga/vga.c index dde0355..d970fea 100644 --- a/src/drivers/pc80/vga/vga.c +++ b/src/drivers/pc80/vga/vga.c @@ -186,7 +186,7 @@ /* plane 2 */ vga_sr_write(0x02, 0x04); - p = (unsigned char *) VGA_FB; + p = (unsigned char *)VGA_FB; for (i = 0; i < count; i++) { for (j = 0; j < 32; j++) { if (j < height) @@ -262,7 +262,7 @@ void vga_line_write(unsigned int line, const char *string) { - unsigned short *p = (unsigned short *) VGA_FB + (80 * line); + unsigned short *p = (unsigned short *)VGA_FB + (80 * line); int i, len = strlen(string); for (i = 0; i < 80; i++) { diff --git a/src/drivers/pc80/vga/vga_io.c b/src/drivers/pc80/vga/vga_io.c index e4b1eb9..2bf2af4 100644 --- a/src/drivers/pc80/vga/vga_io.c +++ b/src/drivers/pc80/vga/vga_io.c @@ -147,10 +147,10 @@ { unsigned char ret; - (void) inb(VGA_STAT1); + (void)inb(VGA_STAT1); outb(index, VGA_AR_INDEX); ret = inb(VGA_AR_VALUE_READ); - (void) inb(VGA_STAT1); + (void)inb(VGA_STAT1); return ret; } @@ -158,10 +158,10 @@ void vga_ar_write(unsigned char index, unsigned char value) { - (void) inb(VGA_STAT1); + (void)inb(VGA_STAT1); outb(index, VGA_AR_INDEX); outb(value, VGA_AR_VALUE_WRITE); - (void) inb(VGA_STAT1); + (void)inb(VGA_STAT1); } void @@ -209,17 +209,17 @@ void vga_palette_enable(void) { - (void) inb(VGA_STAT1); + (void)inb(VGA_STAT1); outb(0x00, VGA_AR_INDEX); - (void) inb(VGA_STAT1); + (void)inb(VGA_STAT1); } void vga_palette_disable(void) { - (void) inb(VGA_STAT1); + (void)inb(VGA_STAT1); outb(0x20, VGA_AR_INDEX); - (void) inb(VGA_STAT1); + (void)inb(VGA_STAT1); } unsigned char -- To view, visit https://review.coreboot.org/c/coreboot/+/69803 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16689da893b5a0c3254364759d435281cb3e1caf Gerrit-Change-Number: 69803 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: src/include: Remove unnecessary space after casts
by Elyes Haouas (Code Review) 18 Nov '22

18 Nov '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69802 ) Change subject: src/include: Remove unnecessary space after casts ...................................................................... src/include: Remove unnecessary space after casts Change-Id: Ie6def0dab9ac37c0938b73d27148a49531c6b17f Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/include/device/pci_rom.h 1 file changed, 11 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/69802/1 diff --git a/src/include/device/pci_rom.h b/src/include/device/pci_rom.h index efda282..83015a1 100644 --- a/src/include/device/pci_rom.h +++ b/src/include/device/pci_rom.h @@ -8,7 +8,7 @@ #include <stdint.h> #define PCI_ROM_HDR 0xAA55 -#define PCI_DATA_HDR ((uint32_t) (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) +#define PCI_DATA_HDR ((uint32_t)(('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) #define PCI_RAM_IMAGE_START 0xD0000 #define PCI_VGA_RAM_IMAGE_START 0xC0000 -- To view, visit https://review.coreboot.org/c/coreboot/+/69802 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6def0dab9ac37c0938b73d27148a49531c6b17f Gerrit-Change-Number: 69802 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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