coreboot-gerrit November 2022

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[S] Change in coreboot[master]: security: Remove unnecessary space after casts
by Yu-Ping Wu (Code Review) 18 Nov '22

18 Nov '22

Attention is currently required from: Christian Walter, Julius Werner, Elyes Haouas. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69800 ) Change subject: security: Remove unnecessary space after casts ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69800 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd41382d0e0ef58498ac925dc9e10b54a76a798a Gerrit-Change-Number: 69800 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 18 Nov 2022 14:36:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: payloads/external/edk2: Add option to clone edk2-platforms repo
by Michał Żygowski (Code Review) 18 Nov '22

18 Nov '22

Attention is currently required from: Martin L Roth, Paul Menzel, Stefan Reinauer. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68872 ) Change subject: payloads/external/edk2: Add option to clone edk2-platforms repo ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/68872/comment/53b095bd_054971ff PS1, Line 12: > Added Done -- To view, visit https://review.coreboot.org/c/coreboot/+/68872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabd0793dfdcb95260046dc992ff30ef581159db9 Gerrit-Change-Number: 68872 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Fri, 18 Nov 2022 14:28:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: src/arch: Remove unnecessary space after casts
by build bot (Jenkins) (Code Review) 18 Nov '22

18 Nov '22

Attention is currently required from: Philipp Hug, Julius Werner, ron minnich. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69816 ) Change subject: src/arch: Remove unnecessary space after casts ...................................................................... Patch Set 1: (2 comments) File src/arch/riscv/trap_handler.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164044): https://review.coreboot.org/c/coreboot/+/69816/comment/da357945_ea8dc0eb PS1, Line 67: printk(BIOS_DEBUG, "Stored ra: %p\n", (void*)tf->gpr[1]); "(foo*)" should be "(foo *)" Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164044): https://review.coreboot.org/c/coreboot/+/69816/comment/93ebb155_5c77bd2e PS1, Line 68: printk(BIOS_DEBUG, "Stored sp: %p\n", (void*)tf->gpr[2]); "(foo*)" should be "(foo *)" -- To view, visit https://review.coreboot.org/c/coreboot/+/69816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00551dfd963d47a58284bc31f21b0fa12130fe78 Gerrit-Change-Number: 69816 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Fri, 18 Nov 2022 14:23:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: src/acpi: Remove unnecessary space after casts
by Elyes Haouas (Code Review) 18 Nov '22

18 Nov '22

Attention is currently required from: Lance Zhao, Tim Wawrzynczak. Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69818 ) Change subject: src/acpi: Remove unnecessary space after casts ...................................................................... src/acpi: Remove unnecessary space after casts Change-Id: I3c077dee1c14e4aa45f837361daf799f02d32a29 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/acpi/acpi.c M src/acpi/acpigen.c 2 files changed, 38 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/69818/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index e1d4088..33152e9 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -361,7 +361,7 @@ tcpa->platform_class = 0; tcpa->laml = tcpa_log_len; - tcpa->lasa = (uintptr_t) lasa; + tcpa->lasa = (uintptr_t)lasa; /* Calculate checksum. */ header->checksum = acpi_checksum((void *)tcpa, header->length); @@ -436,7 +436,7 @@ /* Fill the log area size and start address fields. */ tpm2->laml = tpm2_log_len; - tpm2->lasa = (uintptr_t) lasa; + tpm2->lasa = (uintptr_t)lasa; /* Calculate checksum. */ header->checksum = acpi_checksum((void *)tpm2, header->length); @@ -480,7 +480,7 @@ ssdt->asl_compiler_revision = asl_revision; ssdt->length = sizeof(acpi_header_t); - acpigen_set_current((char *) current); + acpigen_set_current((char *)current); /* Write object to declare coreboot tables */ acpi_ssdt_write_cbtable(); @@ -490,7 +490,7 @@ for (dev = all_devices; dev; dev = dev->next) if (dev->enabled && dev->ops && dev->ops->acpi_fill_ssdt) dev->ops->acpi_fill_ssdt(dev); - current = (unsigned long) acpigen_get_current(); + current = (unsigned long)acpigen_get_current(); } /* (Re)calculate length and checksum. */ @@ -986,7 +986,7 @@ }; einj_smi->err_inj_cap = ACPI_EINJ_DEFAULT_CAP; - einj_smi->trigger_action_table = (u64) (uintptr_t)tat; + einj_smi->trigger_action_table = (u64)(uintptr_t)tat; for (i = 0; i < ACTION_COUNT; i++) printk(BIOS_DEBUG, "default_actions[%d].reg.addr is %llx\n", i, @@ -1164,7 +1164,7 @@ */ printk(BIOS_DEBUG, "ACPI: * HPET\n"); - hpet = (acpi_hpet_t *) current; + hpet = (acpi_hpet_t *)current; current += sizeof(acpi_hpet_t); current = ALIGN_UP(current, 16); acpi_create_hpet(hpet); @@ -1410,7 +1410,7 @@ case 0: /* MCE */ break; case 1: /* CMC */ - hen = (acpi_hest_hen_t *) (pos); + hen = (acpi_hest_hen_t *)(pos); memset(pos, 0, sizeof(acpi_hest_hen_t)); hen->type = 3; /* SCI? */ hen->length = sizeof(acpi_hest_hen_t); @@ -1503,7 +1503,7 @@ { acpi_header_t *header = &(fadt->header); - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memset((void *)fadt, 0, sizeof(acpi_fadt_t)); if (!header) return; @@ -1517,11 +1517,11 @@ header->asl_compiler_revision = asl_revision; fadt->FADT_MinorVersion = get_acpi_fadt_minor_version(); - fadt->firmware_ctrl = (unsigned long) facs; + fadt->firmware_ctrl = (unsigned long)facs; fadt->x_firmware_ctl_l = (unsigned long)facs; fadt->x_firmware_ctl_h = 0; - fadt->dsdt = (unsigned long) dsdt; + fadt->dsdt = (unsigned long)dsdt; fadt->x_dsdt_l = (unsigned long)dsdt; fadt->x_dsdt_h = 0; @@ -1541,7 +1541,7 @@ mainboard_fill_fadt(fadt); header->checksum = - acpi_checksum((void *) fadt, header->length); + acpi_checksum((void *)fadt, header->length); } void acpi_create_lpit(acpi_lpit_t *lpit) @@ -1662,7 +1662,7 @@ ssdt->asl_compiler_revision = asl_revision; ssdt->length = sizeof(acpi_header_t); - acpigen_set_current((char *) current); + acpigen_set_current((char *)current); /* Write object to declare coreboot tables */ acpi_ssdt_write_cbtable(); @@ -1711,19 +1711,19 @@ printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; + rsdp = (acpi_rsdp_t *)current; coreboot_rsdp = (uintptr_t)rsdp; current += sizeof(acpi_rsdp_t); current = acpi_align_current(current); - rsdt = (acpi_rsdt_t *) current; + rsdt = (acpi_rsdt_t *)current; current += sizeof(acpi_rsdt_t); current = acpi_align_current(current); - xsdt = (acpi_xsdt_t *) current; + xsdt = (acpi_xsdt_t *)current; current += sizeof(acpi_xsdt_t); current = acpi_align_current(current); /* clear all table memory */ - memset((void *) start, 0, current - start); + memset((void *)start, 0, current - start); acpi_write_rsdp(rsdp, rsdt, xsdt, oem_id); acpi_write_rsdt(rsdt, oem_id, oem_table_id); @@ -1731,18 +1731,18 @@ printk(BIOS_DEBUG, "ACPI: * FACS\n"); current = ALIGN_UP(current, 64); - facs = (acpi_facs_t *) current; + facs = (acpi_facs_t *)current; current += sizeof(acpi_facs_t); current = acpi_align_current(current); acpi_create_facs(facs); printk(BIOS_DEBUG, "ACPI: * DSDT\n"); - dsdt = (acpi_header_t *) current; + dsdt = (acpi_header_t *)current; memcpy(dsdt, dsdt_file, sizeof(acpi_header_t)); if (dsdt->length >= sizeof(acpi_header_t)) { current += sizeof(acpi_header_t); - acpigen_set_current((char *) current); + acpigen_set_current((char *)current); if (CONFIG(ACPI_SOC_NVS)) acpi_fill_gnvs(); @@ -1752,7 +1752,7 @@ for (dev = all_devices; dev; dev = dev->next) if (dev->ops && dev->ops->acpi_inject_dsdt) dev->ops->acpi_inject_dsdt(dev); - current = (unsigned long) acpigen_get_current(); + current = (unsigned long)acpigen_get_current(); memcpy((char *)current, (char *)dsdt_file + sizeof(acpi_header_t), dsdt->length - sizeof(acpi_header_t)); @@ -1767,7 +1767,7 @@ current = acpi_align_current(current); printk(BIOS_DEBUG, "ACPI: * FADT\n"); - fadt = (acpi_fadt_t *) current; + fadt = (acpi_fadt_t *)current; current += sizeof(acpi_fadt_t); current = acpi_align_current(current); @@ -1793,7 +1793,7 @@ } printk(BIOS_DEBUG, "ACPI: * MCFG\n"); - mcfg = (acpi_mcfg_t *) current; + mcfg = (acpi_mcfg_t *)current; acpi_create_mcfg(mcfg); if (mcfg->header.length > sizeof(acpi_mcfg_t)) { current += mcfg->header.length; @@ -1803,7 +1803,7 @@ if (CONFIG(TPM1)) { printk(BIOS_DEBUG, "ACPI: * TCPA\n"); - tcpa = (acpi_tcpa_t *) current; + tcpa = (acpi_tcpa_t *)current; acpi_create_tcpa(tcpa); if (tcpa->header.length >= sizeof(acpi_tcpa_t)) { current += tcpa->header.length; @@ -1814,7 +1814,7 @@ if (CONFIG(TPM2)) { printk(BIOS_DEBUG, "ACPI: * TPM2\n"); - tpm2 = (acpi_tpm2_t *) current; + tpm2 = (acpi_tpm2_t *)current; acpi_create_tpm2(tpm2); if (tpm2->header.length >= sizeof(acpi_tpm2_t)) { current += tpm2->header.length; @@ -1837,7 +1837,7 @@ printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; + madt = (acpi_madt_t *)current; acpi_create_madt(madt); if (madt->header.length > sizeof(acpi_madt_t)) { current += madt->header.length; @@ -1849,7 +1849,7 @@ if (CONFIG(ACPI_BERT)) { void *region; size_t size; - bert = (acpi_bert_t *) current; + bert = (acpi_bert_t *)current; if (acpi_soc_get_bert_region(&region, &size) == CB_SUCCESS) { printk(BIOS_DEBUG, "ACPI: * BERT\n"); acpi_write_bert(bert, (uintptr_t)region, size); diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index 85b49b2..7afb839 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -256,7 +256,7 @@ unsigned char *pathlen; acpigen_emit_byte(MULTI_NAME_PREFIX); acpigen_emit_byte(ZERO_OP); - pathlen = ((unsigned char *) acpigen_get_current()) - 1; + pathlen = ((unsigned char *)acpigen_get_current()) - 1; while (name[0] != '\0') { acpigen_emit_simple_namestring(name); @@ -399,7 +399,7 @@ acpigen_write_len_f(); snprintf(pscope, sizeof(pscope), - CONFIG_ACPI_CPU_STRING, (unsigned int) cpuindex); + CONFIG_ACPI_CPU_STRING, (unsigned int)cpuindex); acpigen_emit_namestring(pscope); acpigen_emit_byte(cpuindex); acpigen_emit_dword(pblock_addr); -- To view, visit https://review.coreboot.org/c/coreboot/+/69818 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c077dee1c14e4aa45f837361daf799f02d32a29 Gerrit-Change-Number: 69818 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Lance Zhao Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: src/commonlib: Remove unnecessary space after casts
by Elyes Haouas (Code Review) 18 Nov '22

18 Nov '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69817 ) Change subject: src/commonlib: Remove unnecessary space after casts ...................................................................... src/commonlib: Remove unnecessary space after casts Change-Id: Ib20f02cc9e5be0efea8bc29fce6bd148adf28ead Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/commonlib/fsp_relocate.c M src/commonlib/storage/bouncebuf.h M src/commonlib/storage/sdhci_adma.c M src/commonlib/storage/storage.h 4 files changed, 16 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/69817/1 diff --git a/src/commonlib/fsp_relocate.c b/src/commonlib/fsp_relocate.c index 55295ca..ad24ca7 100644 --- a/src/commonlib/fsp_relocate.c +++ b/src/commonlib/fsp_relocate.c @@ -233,13 +233,13 @@ uint32_t i; EFI_IMAGE_DATA_DIRECTORY *relocd; - relocd = (void *) &pe_base[offset]; + relocd = (void *)&pe_base[offset]; offset += sizeof(*relocd); // Read relocation type, offset pairs rlen = read_le32(&relocd->Size) - sizeof(*relocd); rnum = rlen / sizeof(uint16_t); vaddr = read_le32(&relocd->VirtualAddress); - rdata = (uint16_t *) &pe_base[offset]; + rdata = (uint16_t *)&pe_base[offset]; printk(FSP_DBG_LVL, "\t%d Relocs for RVA %x\n", rnum, vaddr); for (i = 0; i < rnum; i++) { diff --git a/src/commonlib/storage/bouncebuf.h b/src/commonlib/storage/bouncebuf.h index 9e3ab74..fce3fbd 100644 --- a/src/commonlib/storage/bouncebuf.h +++ b/src/commonlib/storage/bouncebuf.h @@ -76,7 +76,7 @@ #define ALLOC_CACHE_ALIGN_BUFFER(type, name, size) \ char __##name[ROUND(size * sizeof(type), DMA_MINALIGN) + \ DMA_MINALIGN - 1]; \ - type *name = (type *) ALIGN_UP((uintptr_t)__##name, DMA_MINALIGN) + type *name = (type *)ALIGN_UP((uintptr_t)__##name, DMA_MINALIGN) #ifndef ARCH_DMA_MINALIGN #define ARCH_DMA_MINALIGN (DMA_MINALIGN) #endif diff --git a/src/commonlib/storage/sdhci_adma.c b/src/commonlib/storage/sdhci_adma.c index 92f938f..9ad949e 100644 --- a/src/commonlib/storage/sdhci_adma.c +++ b/src/commonlib/storage/sdhci_adma.c @@ -120,10 +120,10 @@ } if (dma64) - sdhci_writel(sdhci_ctrlr, (uintptr_t) sdhci_ctrlr->adma64_descs, + sdhci_writel(sdhci_ctrlr, (uintptr_t)sdhci_ctrlr->adma64_descs, SDHCI_ADMA_ADDRESS); else - sdhci_writel(sdhci_ctrlr, (uintptr_t) sdhci_ctrlr->adma_descs, + sdhci_writel(sdhci_ctrlr, (uintptr_t)sdhci_ctrlr->adma_descs, SDHCI_ADMA_ADDRESS); return 0; diff --git a/src/commonlib/storage/storage.h b/src/commonlib/storage/storage.h index cdd5e6c..5f51ba9 100644 --- a/src/commonlib/storage/storage.h +++ b/src/commonlib/storage/storage.h @@ -11,7 +11,7 @@ #define ALLOC_CACHE_ALIGN_BUFFER(type, name, size) \ char __##name[ROUND(size * sizeof(type), DMA_MINALIGN) + \ DMA_MINALIGN - 1]; \ - type *name = (type *) ALIGN_UP((uintptr_t)__##name, DMA_MINALIGN) + type *name = (type *)ALIGN_UP((uintptr_t)__##name, DMA_MINALIGN) /* NOOPs mirroring ARM's cache API, since x86 devices usually cache snoop */ #define dcache_invalidate_by_mva(addr, len) -- To view, visit https://review.coreboot.org/c/coreboot/+/69817 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib20f02cc9e5be0efea8bc29fce6bd148adf28ead Gerrit-Change-Number: 69817 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: src/arch: Remove unnecessary space after casts
by Elyes Haouas (Code Review) 18 Nov '22

18 Nov '22

Attention is currently required from: Philipp Hug, Julius Werner, ron minnich. Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69816 ) Change subject: src/arch: Remove unnecessary space after casts ...................................................................... src/arch: Remove unnecessary space after casts Change-Id: I00551dfd963d47a58284bc31f21b0fa12130fe78 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/arch/arm/eabi_compat.c M src/arch/arm/libgcc/umoddi3.c M src/arch/riscv/trap_handler.c M src/arch/x86/cpu.c M src/arch/x86/memset.c M src/arch/x86/pirq_routing.c 6 files changed, 19 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/69816/1 diff --git a/src/arch/arm/eabi_compat.c b/src/arch/arm/eabi_compat.c index cbc285c..2a110d5 100644 --- a/src/arch/arm/eabi_compat.c +++ b/src/arch/arm/eabi_compat.c @@ -26,11 +26,11 @@ void __aeabi_memcpy(void *dest, const void *src, size_t n); void __aeabi_memcpy(void *dest, const void *src, size_t n) { - (void) memcpy(dest, src, n); + (void)memcpy(dest, src, n); } void __aeabi_memset(void *dest, size_t n, int c); void __aeabi_memset(void *dest, size_t n, int c) { - (void) memset(dest, c, n); + (void)memset(dest, c, n); } diff --git a/src/arch/arm/libgcc/umoddi3.c b/src/arch/arm/libgcc/umoddi3.c index 5d2ede7..c84e9e4 100644 --- a/src/arch/arm/libgcc/umoddi3.c +++ b/src/arch/arm/libgcc/umoddi3.c @@ -4,6 +4,6 @@ uint64_t __umoddi3(uint64_t num, uint64_t den) { uint64_t v; - (void) __udivmoddi4(num, den, &v); + (void)__udivmoddi4(num, den, &v); return v; } diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index f940f63..53049fd 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -64,8 +64,8 @@ previous_mode, mprv? " (MPRV)":""); printk(BIOS_DEBUG, "Bad instruction pc: %p\n", (void *)tf->epc); printk(BIOS_DEBUG, "Bad address: %p\n", (void *)tf->badvaddr); - printk(BIOS_DEBUG, "Stored ra: %p\n", (void*) tf->gpr[1]); - printk(BIOS_DEBUG, "Stored sp: %p\n", (void*) tf->gpr[2]); + printk(BIOS_DEBUG, "Stored ra: %p\n", (void*)tf->gpr[1]); + printk(BIOS_DEBUG, "Stored sp: %p\n", (void*)tf->gpr[2]); } static void interrupt_handler(trapframe *tf) diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index 6a8ddef..9fc5233 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -59,7 +59,7 @@ : "cc"); /* AH is 0x02 on Cyrix after the divide.. */ - return (unsigned char) (test >> 8) == 0x02; + return (unsigned char)(test >> 8) == 0x02; } /* diff --git a/src/arch/x86/memset.c b/src/arch/x86/memset.c index fc09a9b..8a0165b 100644 --- a/src/arch/x86/memset.c +++ b/src/arch/x86/memset.c @@ -12,7 +12,7 @@ void *memset(void *dstpp, int c, size_t len) { int d0; - unsigned long int dstp = (unsigned long int) dstpp; + unsigned long int dstp = (unsigned long int)dstpp; #if (ENV_ROMSTAGE && CONFIG(ASAN_IN_ROMSTAGE)) || \ (ENV_RAMSTAGE && CONFIG(ASAN_IN_RAMSTAGE)) @@ -22,7 +22,7 @@ /* This explicit register allocation improves code very much indeed. */ register op_t x asm("ax"); - x = (unsigned char) c; + x = (unsigned char)c; /* Clear the direction flag, so filling will move forward. */ asm volatile("cld"); diff --git a/src/arch/x86/pirq_routing.c b/src/arch/x86/pirq_routing.c index 362650d..0da057f 100644 --- a/src/arch/x86/pirq_routing.c +++ b/src/arch/x86/pirq_routing.c @@ -17,7 +17,7 @@ if (sizeof(struct irq_routing_table) != rt->size) { printk(BIOS_WARNING, "Inconsistent Interrupt Routing Table size (0x%x/0x%x).\n", - (unsigned int) sizeof(struct irq_routing_table), + (unsigned int)sizeof(struct irq_routing_table), rt->size); rt->size = sizeof(struct irq_routing_table); } -- To view, visit https://review.coreboot.org/c/coreboot/+/69816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00551dfd963d47a58284bc31f21b0fa12130fe78 Gerrit-Change-Number: 69816 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: src/mainboard: Remove unnecessary space after casts
by Elyes Haouas (Code Review) 18 Nov '22

18 Nov '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69815 ) Change subject: src/mainboard: Remove unnecessary space after casts ...................................................................... src/mainboard: Remove unnecessary space after casts Change-Id: Id8e1a52279e6a606441eefe30e24bcd44e006aad Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/mainboard/51nb/x210/romstage.c M src/mainboard/acer/aspire_vn7_572g/ec.c M src/mainboard/acer/aspire_vn7_572g/mainboard.c M src/mainboard/acer/aspire_vn7_572g/romstage.c M src/mainboard/emulation/qemu-armv7/mainboard.c M src/mainboard/emulation/qemu-i440fx/memmap.c M src/mainboard/emulation/qemu-power8/uart.c M src/mainboard/emulation/qemu-riscv/uart.c M src/mainboard/emulation/spike-riscv/uart.c M src/mainboard/getac/p470/acpi_tables.c M src/mainboard/google/brya/variants/moli/ramstage.c M src/mainboard/google/storm/cdp.c M src/mainboard/ocp/deltalake/ipmi.c M src/mainboard/ocp/deltalake/romstage.c M src/mainboard/ocp/tiogapass/romstage.c M src/mainboard/pcengines/apu2/irq_tables.c M src/mainboard/protectli/vault_bsw/romstage.c M src/mainboard/purism/librem_skl/romstage.c M src/mainboard/scaleway/tagada/bmcinfo.c M src/mainboard/siemens/mc_apl1/mainboard.c M src/mainboard/siemens/mc_ehl/mainboard.c 21 files changed, 44 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/69815/1 diff --git a/src/mainboard/51nb/x210/romstage.c b/src/mainboard/51nb/x210/romstage.c index 8a8fa4f..4a776ad 100644 --- a/src/mainboard/51nb/x210/romstage.c +++ b/src/mainboard/51nb/x210/romstage.c @@ -38,6 +38,6 @@ mem_cfg->DqPinsInterleaved = TRUE; mem_cfg->CaVrefConfig = 2; mem_cfg->MemorySpdDataLen = blk.len; - mem_cfg->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0]; - mem_cfg->MemorySpdPtr10 = (uintptr_t) blk.spd_array[1]; + mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; } diff --git a/src/mainboard/acer/aspire_vn7_572g/ec.c b/src/mainboard/acer/aspire_vn7_572g/ec.c index 570e282..72f2768 100644 --- a/src/mainboard/acer/aspire_vn7_572g/ec.c +++ b/src/mainboard/acer/aspire_vn7_572g/ec.c @@ -53,15 +53,15 @@ uint8_t ec_idx_read(uint16_t addr) { - outb((uint8_t) (addr >> 8), EC_INDEX_IO_HIGH_ADDR_PORT); - outb((uint8_t) addr, EC_INDEX_IO_LOW_ADDR_PORT); + outb((uint8_t)(addr >> 8), EC_INDEX_IO_HIGH_ADDR_PORT); + outb((uint8_t)addr, EC_INDEX_IO_LOW_ADDR_PORT); return inb(EC_INDEX_IO_DATA_PORT); } void ec_idx_write(uint16_t addr, uint8_t data) { - outb((uint8_t) (addr >> 8), EC_INDEX_IO_HIGH_ADDR_PORT); - outb((uint8_t) addr, EC_INDEX_IO_LOW_ADDR_PORT); + outb((uint8_t)(addr >> 8), EC_INDEX_IO_HIGH_ADDR_PORT); + outb((uint8_t)addr, EC_INDEX_IO_LOW_ADDR_PORT); outb(data, EC_INDEX_IO_DATA_PORT); } diff --git a/src/mainboard/acer/aspire_vn7_572g/mainboard.c b/src/mainboard/acer/aspire_vn7_572g/mainboard.c index eba9e98..2f222dc 100644 --- a/src/mainboard/acer/aspire_vn7_572g/mainboard.c +++ b/src/mainboard/acer/aspire_vn7_572g/mainboard.c @@ -81,7 +81,7 @@ send_ec_command(0xE0); for (int i = 0; i < 4; i++) { /* Shift bytes */ - ec_time_byte = (uint8_t) (ec_time >> (i * 8)); + ec_time_byte = (uint8_t)(ec_time >> (i * 8)); printk(BIOS_DEBUG, "EC: Sending 0x%x (iteration %d)\n", ec_time_byte, i); send_ec_data(ec_time_byte); } diff --git a/src/mainboard/acer/aspire_vn7_572g/romstage.c b/src/mainboard/acer/aspire_vn7_572g/romstage.c index 74e1438..1b5e250 100644 --- a/src/mainboard/acer/aspire_vn7_572g/romstage.c +++ b/src/mainboard/acer/aspire_vn7_572g/romstage.c @@ -30,8 +30,8 @@ mem_cfg->CaVrefConfig = 2; mem_cfg->DqPinsInterleaved = 1; mem_cfg->MemorySpdDataLen = blk.len; - mem_cfg->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0]; - mem_cfg->MemorySpdPtr10 = (uintptr_t) blk.spd_array[1]; + mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; mem_cfg->PchSataHsioRxGen3EqBoostMagEnable[1] = 1; mem_cfg->PchSataHsioRxGen3EqBoostMag[1] = 1; diff --git a/src/mainboard/emulation/qemu-armv7/mainboard.c b/src/mainboard/emulation/qemu-armv7/mainboard.c index 441086f..a5e9183 100644 --- a/src/mainboard/emulation/qemu-armv7/mainboard.c +++ b/src/mainboard/emulation/qemu-armv7/mainboard.c @@ -15,7 +15,7 @@ /* height is at most 1024 */ int width = 800, height = 600; uint32_t framebuffer = 0x4c000000; - pl111 = (uint32_t *) 0x10020000; + pl111 = (uint32_t *)0x10020000; write32(pl111, (width / 4) - 4); write32(pl111 + 1, height - 1); /* registers 2, 3 and 5 are ignored by qemu. Set them correctly if diff --git a/src/mainboard/emulation/qemu-i440fx/memmap.c b/src/mainboard/emulation/qemu-i440fx/memmap.c index efe83c3..be730b7 100644 --- a/src/mainboard/emulation/qemu-i440fx/memmap.c +++ b/src/mainboard/emulation/qemu-i440fx/memmap.c @@ -22,11 +22,11 @@ { unsigned long high; outb(HIGH_HIGHRAM_ADDR, CMOS_ADDR_PORT); - high = ((unsigned long) inb(CMOS_DATA_PORT)) << 22; + high = ((unsigned long)inb(CMOS_DATA_PORT)) << 22; outb(MID_HIGHRAM_ADDR, CMOS_ADDR_PORT); - high |= ((unsigned long) inb(CMOS_DATA_PORT)) << 14; + high |= ((unsigned long)inb(CMOS_DATA_PORT)) << 14; outb(LOW_HIGHRAM_ADDR, CMOS_ADDR_PORT); - high |= ((unsigned long) inb(CMOS_DATA_PORT)) << 6; + high |= ((unsigned long)inb(CMOS_DATA_PORT)) << 6; return high; } @@ -34,9 +34,9 @@ { unsigned long tomk; outb(HIGH_RAM_ADDR, CMOS_ADDR_PORT); - tomk = ((unsigned long) inb(CMOS_DATA_PORT)) << 14; + tomk = ((unsigned long)inb(CMOS_DATA_PORT)) << 14; outb(LOW_RAM_ADDR, CMOS_ADDR_PORT); - tomk |= ((unsigned long) inb(CMOS_DATA_PORT)) << 6; + tomk |= ((unsigned long)inb(CMOS_DATA_PORT)) << 6; tomk += 16 * 1024; return tomk; } diff --git a/src/mainboard/emulation/qemu-power8/uart.c b/src/mainboard/emulation/qemu-power8/uart.c index a369e62..c9113b4 100644 --- a/src/mainboard/emulation/qemu-power8/uart.c +++ b/src/mainboard/emulation/qemu-power8/uart.c @@ -7,7 +7,7 @@ static uint8_t *buf = (void *)0; uintptr_t uart_platform_base(unsigned int idx) { - return (uintptr_t) buf; + return (uintptr_t)buf; } void uart_init(unsigned int idx) diff --git a/src/mainboard/emulation/qemu-riscv/uart.c b/src/mainboard/emulation/qemu-riscv/uart.c index 19a2b00..8f8a3a3 100644 --- a/src/mainboard/emulation/qemu-riscv/uart.c +++ b/src/mainboard/emulation/qemu-riscv/uart.c @@ -6,5 +6,5 @@ uintptr_t uart_platform_base(unsigned int idx) { - return (uintptr_t) QEMU_VIRT_UART0; + return (uintptr_t)QEMU_VIRT_UART0; } diff --git a/src/mainboard/emulation/spike-riscv/uart.c b/src/mainboard/emulation/spike-riscv/uart.c index efefc52..4ea2466 100644 --- a/src/mainboard/emulation/spike-riscv/uart.c +++ b/src/mainboard/emulation/spike-riscv/uart.c @@ -5,5 +5,5 @@ uintptr_t uart_platform_base(unsigned int idx) { - return (uintptr_t) 0x02100000; + return (uintptr_t)0x02100000; } diff --git a/src/mainboard/getac/p470/acpi_tables.c b/src/mainboard/getac/p470/acpi_tables.c index 2de388a..1429b59 100644 --- a/src/mainboard/getac/p470/acpi_tables.c +++ b/src/mainboard/getac/p470/acpi_tables.c @@ -17,7 +17,7 @@ acpi_header_t *header = &(ecdt->header); - memset((void *) ecdt, 0, ecdt_len); + memset((void *)ecdt, 0, ecdt_len); /* fill out header fields */ memcpy(header->signature, "ECDT", 4); @@ -48,7 +48,7 @@ memcpy(ecdt->ec_id, ec_id, sizeof(ec_id)); header->checksum = - acpi_checksum((void *) ecdt, ecdt_len); + acpi_checksum((void *)ecdt, ecdt_len); return header->length; } diff --git a/src/mainboard/google/brya/variants/moli/ramstage.c b/src/mainboard/google/brya/variants/moli/ramstage.c index 89ccf6b..2be75e4 100644 --- a/src/mainboard/google/brya/variants/moli/ramstage.c +++ b/src/mainboard/google/brya/variants/moli/ramstage.c @@ -23,7 +23,7 @@ if (board_ver <= 1) return; - config->enable_gpio = (struct acpi_gpio) ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A21); + config->enable_gpio = (struct acpi_gpio)ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A21); } const struct cpu_power_limits limits[] = { diff --git a/src/mainboard/google/storm/cdp.c b/src/mainboard/google/storm/cdp.c index 39afc1a..9dd184e 100644 --- a/src/mainboard/google/storm/cdp.c +++ b/src/mainboard/google/storm/cdp.c @@ -49,7 +49,7 @@ if (board_id() != BOARD_ID_PROTO_0_2_NAND) return; - ebi2_regs = (struct ebi2cr_regs *) EBI2CR_BASE; + ebi2_regs = (struct ebi2cr_regs *)EBI2CR_BASE; nand_clock_config(); configure_nand_gpio(); diff --git a/src/mainboard/ocp/deltalake/ipmi.c b/src/mainboard/ocp/deltalake/ipmi.c index 1e553c0..c3ba354 100644 --- a/src/mainboard/ocp/deltalake/ipmi.c +++ b/src/mainboard/ocp/deltalake/ipmi.c @@ -20,7 +20,7 @@ struct ipmi_config_rsp rsp; ret = ipmi_message(CONFIG_BMC_KCS_BASE, IPMI_NETFN_OEM, 0x0, - IPMI_OEM_GET_PCIE_CONFIG, NULL, 0, (unsigned char *) &rsp, + IPMI_OEM_GET_PCIE_CONFIG, NULL, 0, (unsigned char *)&rsp, sizeof(rsp)); if (ret < sizeof(struct ipmi_rsp) || rsp.resp.completion_code) { @@ -46,7 +46,7 @@ struct ipmi_config_rsp rsp; ret = ipmi_message(CONFIG_BMC_KCS_BASE, IPMI_NETFN_OEM, 0x0, IPMI_OEM_GET_BOARD_ID, - NULL, 0, (unsigned char *) &rsp, sizeof(rsp)); + NULL, 0, (unsigned char *)&rsp, sizeof(rsp)); if (ret < sizeof(struct ipmi_rsp) || rsp.resp.completion_code) { printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n", diff --git a/src/mainboard/ocp/deltalake/romstage.c b/src/mainboard/ocp/deltalake/romstage.c index 23bbffe..d20c54c 100644 --- a/src/mainboard/ocp/deltalake/romstage.c +++ b/src/mainboard/ocp/deltalake/romstage.c @@ -105,7 +105,7 @@ } /* Select DDR Frequency Limit */ - if (vpd_get_int(FSP_DIMM_FREQ, VPD_RW_THEN_RO, (int *const) &val_int)) { + if (vpd_get_int(FSP_DIMM_FREQ, VPD_RW_THEN_RO, (int *const)&val_int)) { printk(BIOS_INFO, "Setting DdrFreqLimit %d from VPD\n", val_int); mupd->FspmConfig.DdrFreqLimit = ddr_freq_limit(val_int); } else { diff --git a/src/mainboard/ocp/tiogapass/romstage.c b/src/mainboard/ocp/tiogapass/romstage.c index 842e977..a188ab1 100644 --- a/src/mainboard/ocp/tiogapass/romstage.c +++ b/src/mainboard/ocp/tiogapass/romstage.c @@ -32,17 +32,17 @@ { memcpy(iio_table_buf, tp_iio_bifur_table, sizeof(tp_iio_bifur_table)); mupd->FspmConfig.IioBifurcationConfig.IIoBifurcationTable = - (UPD_IIO_BIFURCATION_DATA_ENTRY *) iio_table_buf; + (UPD_IIO_BIFURCATION_DATA_ENTRY *)iio_table_buf; mupd->FspmConfig.IioBifurcationConfig.NumberOfEntries = ARRAY_SIZE(tp_iio_bifur_table); mupd->FspmConfig.IioPciConfig.ConfigurationTable = - (UPD_PCI_PORT_CONFIG *) tp_iio_pci_port_skt0; + (UPD_PCI_PORT_CONFIG *)tp_iio_pci_port_skt0; mupd->FspmConfig.IioPciConfig.NumberOfEntries = ARRAY_SIZE(tp_iio_pci_port_skt0); mupd->FspmConfig.PchPciConfig.PciPortConfig = - (UPD_PCH_PCIE_PORT *) tp_pch_pci_port_skt0; + (UPD_PCH_PCIE_PORT *)tp_pch_pci_port_skt0; mupd->FspmConfig.PchPciConfig.NumberOfEntries = ARRAY_SIZE(tp_pch_pci_port_skt0); diff --git a/src/mainboard/pcengines/apu2/irq_tables.c b/src/mainboard/pcengines/apu2/irq_tables.c index fcd4772..4d56145 100644 --- a/src/mainboard/pcengines/apu2/irq_tables.c +++ b/src/mainboard/pcengines/apu2/irq_tables.c @@ -43,7 +43,7 @@ printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); pirq = (void *)(addr); - v = (u8 *) (addr); + v = (u8 *)(addr); pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; diff --git a/src/mainboard/protectli/vault_bsw/romstage.c b/src/mainboard/protectli/vault_bsw/romstage.c index 33519b9..745cb82 100644 --- a/src/mainboard/protectli/vault_bsw/romstage.c +++ b/src/mainboard/protectli/vault_bsw/romstage.c @@ -15,7 +15,7 @@ * FSP enables internal UART. Disable it and re-enable Super I/O UART to * prevent loss of debug information on serial. */ - pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, (u32) 0); + pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, (u32)0); ite_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/purism/librem_skl/romstage.c b/src/mainboard/purism/librem_skl/romstage.c index 604db60..2b35fc2 100644 --- a/src/mainboard/purism/librem_skl/romstage.c +++ b/src/mainboard/purism/librem_skl/romstage.c @@ -31,7 +31,7 @@ mem_cfg->DqPinsInterleaved = TRUE; mem_cfg->CaVrefConfig = 2; mem_cfg->MemorySpdDataLen = blk.len; - mem_cfg->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0]; + mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; /* Enable and set SATA HSIO adjustments for ports 0 and 2 */ mem_cfg->PchSataHsioRxGen3EqBoostMagEnable[0] = 1; diff --git a/src/mainboard/scaleway/tagada/bmcinfo.c b/src/mainboard/scaleway/tagada/bmcinfo.c index e015837..2de2f2e 100644 --- a/src/mainboard/scaleway/tagada/bmcinfo.c +++ b/src/mainboard/scaleway/tagada/bmcinfo.c @@ -94,7 +94,7 @@ char *bmcinfo_serial(void) { if (IS_BMC_INFO_FIELD_VALID(bmcSerial)) - return (char *) BMC_INFO->bmcSerial; + return (char *)BMC_INFO->bmcSerial; return NULL; } diff --git a/src/mainboard/siemens/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/mainboard.c index dc188b3..0593797 100644 --- a/src/mainboard/siemens/mc_apl1/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/mainboard.c @@ -264,7 +264,7 @@ return; /* Get legacy delay parameter from hwinfo. */ - if (hwilib_get_field(LegacyDelay, (uint8_t *) &legacy_delay, + if (hwilib_get_field(LegacyDelay, (uint8_t *)&legacy_delay, sizeof(legacy_delay)) != sizeof(legacy_delay)) return; diff --git a/src/mainboard/siemens/mc_ehl/mainboard.c b/src/mainboard/siemens/mc_ehl/mainboard.c index 9436244..7aa0d86 100644 --- a/src/mainboard/siemens/mc_ehl/mainboard.c +++ b/src/mainboard/siemens/mc_ehl/mainboard.c @@ -100,7 +100,7 @@ return; /* Get legacy delay parameter from hwinfo. */ - if (hwilib_get_field(LegacyDelay, (uint8_t *) &legacy_delay, + if (hwilib_get_field(LegacyDelay, (uint8_t *)&legacy_delay, sizeof(legacy_delay)) != sizeof(legacy_delay)) return; -- To view, visit https://review.coreboot.org/c/coreboot/+/69815 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8e1a52279e6a606441eefe30e24bcd44e006aad Gerrit-Change-Number: 69815 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: intelblocks/cse: Add functions to check and change PTT state
by build bot (Jenkins) (Code Review) 18 Nov '22

18 Nov '22

Attention is currently required from: Michał Kopeć. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68919 ) Change subject: intelblocks/cse: Add functions to check and change PTT state ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/include/intelblocks/cse.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164042): https://review.coreboot.org/c/coreboot/+/68919/comment/6fc997df_038aed2a PS2, Line 34: #define MKHI_GEN_FW_FEATURE_SHIPMENT_OVER 0x14 please, no space before tabs -- To view, visit https://review.coreboot.org/c/coreboot/+/68919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8426c46eada2d503d6ee72324c5d0025da3f2028 Gerrit-Change-Number: 68919 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Fri, 18 Nov 2022 14:20:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: [WIP] mb/prodrive/atlas: Populate smbios table with VPD from ECs EMI
by David Milosevic (Code Review) 18 Nov '22

18 Nov '22

Attention is currently required from: Maximilian Brune, Angel Pons, Arthur Heymans, Lean Sheng Tan. David Milosevic has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68137 ) Change subject: [WIP] mb/prodrive/atlas: Populate smbios table with VPD from ECs EMI ...................................................................... Patch Set 11: (1 comment) File src/mainboard/prodrive/atlas/emi.c: https://review.coreboot.org/c/coreboot/+/68137/comment/6830cd9d_ca138722 PS11, Line 68: if (idx == n) : return; : : buff[idx++] > I could do that but then we would need the same branch right after the for-loop in order to determin […] Even if we put this condition into the outer loop, we would have one branch/check more than actually needed while(idx != n) { // check idx != n [...] for(u8 i = 0; i < 4 && idx != n; i++) // check idx != n buff[idx++] = bytes[i]; } -- To view, visit https://review.coreboot.org/c/coreboot/+/68137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47bb4883c43ff344a9bda92c3106dd025533b391 Gerrit-Change-Number: 68137 Gerrit-PatchSet: 11 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Fri, 18 Nov 2022 14:20:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: intelblocks/cse: Add functions to check and change PTT state
by Michał Żygowski (Code Review) 18 Nov '22

18 Nov '22

Attention is currently required from: Michał Kopeć. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68919 ) Change subject: intelblocks/cse: Add functions to check and change PTT state ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/68919/comment/9414afce_60898dc5 PS1, Line 1223: printk(BIOS_DEBUG, "HECI: FW FEATURE SHIPMENT TIME STATE OVERRIDE success\n"); > Shouldn't this be before the `do_global_reset()`? Ohh yeah, for sure. Fixed. -- To view, visit https://review.coreboot.org/c/coreboot/+/68919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8426c46eada2d503d6ee72324c5d0025da3f2028 Gerrit-Change-Number: 68919 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Fri, 18 Nov 2022 14:20:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-MessageType: comment

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