coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

1 participants
7286 discussions

[S] Change in coreboot[master]: soc/intel/common/block/pcie: Allow selectable Common Clock and ASPM
by Michał Żygowski (Code Review) 18 Nov '22

18 Nov '22

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69824 ) Change subject: soc/intel/common/block/pcie: Allow selectable Common Clock and ASPM ...................................................................... soc/intel/common/block/pcie: Allow selectable Common Clock and ASPM There is no need to enforce enabled ASPM and Common Clock on PCIe Root Ports. ASPM can additionally introduce indeterministic latencies and lower performance of PCIe devices. For mobile devices it may be desirable to enable ASPM for power saving so keep the setting enabled by default, but on desktops power is less of a concern. Desktop boards that do not wish to enable ASPM, now will be able to disable it. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I06d7fe8e3274800e59decb9d24fd4a4208bb2b44 --- M src/soc/intel/common/block/pcie/Kconfig 1 file changed, 23 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/69824/1 diff --git a/src/soc/intel/common/block/pcie/Kconfig b/src/soc/intel/common/block/pcie/Kconfig index 25cde37..d9d1548 100644 --- a/src/soc/intel/common/block/pcie/Kconfig +++ b/src/soc/intel/common/block/pcie/Kconfig @@ -1,7 +1,5 @@ config SOC_INTEL_COMMON_BLOCK_PCIE bool - select PCIEXP_ASPM - select PCIEXP_COMMON_CLOCK help Intel Processor common PCIE support @@ -9,6 +7,12 @@ source "src/soc/intel/common/block/pcie/*/Kconfig" +config PCIEXP_ASPM + default y + +config PCIEXP_COMMON_CLOCK + default y + config PCIEXP_CLK_PM default y -- To view, visit https://review.coreboot.org/c/coreboot/+/69824 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06d7fe8e3274800e59decb9d24fd4a4208bb2b44 Gerrit-Change-Number: 69824 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: mb/msi/ms7d25: Re-enable GpioOverride
by Michał Żygowski (Code Review) 18 Nov '22

18 Nov '22

Attention is currently required from: Michał Kopeć. Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69823 ) Change subject: mb/msi/ms7d25: Re-enable GpioOverride ...................................................................... mb/msi/ms7d25: Re-enable GpioOverride Set all GPIOs to their target functions and do not depend on FSP to configure them. The board support has stabilized nad was tested with many PCIe devices. There is no need to detect CLKREQ signals so we may hardcode them. TEST=Boot MSI PRO Z690-A DDR4 to Linux and check if all ASPM and Clock PM features' state on PCIe root ports are the same before and after the change. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I01dc83ce23ca27525b8905665da942510f249824 --- M src/mainboard/msi/ms7d25/devicetree.cb M src/mainboard/msi/ms7d25/gpio.h M src/mainboard/msi/ms7d25/romstage_fsp_params.c 3 files changed, 123 insertions(+), 93 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/69823/1 diff --git a/src/mainboard/msi/ms7d25/devicetree.cb b/src/mainboard/msi/ms7d25/devicetree.cb index 49e06de..f7a7ccf 100644 --- a/src/mainboard/msi/ms7d25/devicetree.cb +++ b/src/mainboard/msi/ms7d25/devicetree.cb @@ -109,7 +109,7 @@ register "cpu_pcie_rp[CPU_RP(1)]" = "{ .clk_src = 9, .clk_req = 9, - .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT, + .flags = PCIE_RP_LTR | PCIE_RP_AER, .PcieRpL1Substates = L1_SS_L1_2, .pcie_rp_aspm = ASPM_L0S_L1, }" @@ -139,7 +139,7 @@ register "pch_pcie_rp[PCH_RP(1)]" = "{ .clk_src = 10, .clk_req = 10, - .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT, + .flags = PCIE_RP_LTR | PCIE_RP_AER, .PcieRpL1Substates = L1_SS_L1_2, .pcie_rp_aspm = ASPM_L0S_L1, }" @@ -150,7 +150,7 @@ register "pch_pcie_rp[PCH_RP(2)]" = "{ .clk_src = 17, .clk_req = 17, - .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT, + .flags = PCIE_RP_LTR | PCIE_RP_AER, .PcieRpL1Substates = L1_SS_L1_2, .pcie_rp_aspm = ASPM_L0S_L1, }" @@ -172,7 +172,7 @@ register "pch_pcie_rp[PCH_RP(5)]" = "{ .clk_src = 15, .clk_req = 15, - .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT, + .flags = PCIE_RP_LTR | PCIE_RP_AER, .PcieRpL1Substates = L1_SS_L1_2, .pcie_rp_aspm = ASPM_L0S_L1, }" @@ -184,7 +184,7 @@ register "pch_pcie_rp[PCH_RP(9)]" = "{ .clk_src = 13, .clk_req = 13, - .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT, + .flags = PCIE_RP_LTR | PCIE_RP_AER, .PcieRpL1Substates = L1_SS_L1_2, .pcie_rp_aspm = ASPM_L0S_L1, }" @@ -208,7 +208,7 @@ register "pch_pcie_rp[PCH_RP(21)]" = "{ .clk_src = 14, .clk_req = 14, - .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT, + .flags = PCIE_RP_LTR | PCIE_RP_AER, .PcieRpL1Substates = L1_SS_L1_2, .pcie_rp_aspm = ASPM_L0S_L1, }" @@ -220,7 +220,7 @@ register "pch_pcie_rp[PCH_RP(25)]" = "{ .clk_src = 8, .clk_req = 8, - .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT, + .flags = PCIE_RP_LTR | PCIE_RP_AER, .PcieRpL1Substates = L1_SS_L1_2, .pcie_rp_aspm = ASPM_L0S_L1, }" diff --git a/src/mainboard/msi/ms7d25/gpio.h b/src/mainboard/msi/ms7d25/gpio.h index bf81138..c388262 100644 --- a/src/mainboard/msi/ms7d25/gpio.h +++ b/src/mainboard/msi/ms7d25/gpio.h @@ -2,22 +2,6 @@ #include <soc/gpio.h> -/* - * Do not program the CLKREQ signals in coreboot to let FSP detect and - * configure CLKREQ pads for PCIe ports. Otherwise the CLKREQ pads are - * reprogrammed by FSP despite having GpioOverride=1 in the following manner: - * - * GPIO (reset) -> (CLKREQ (coreboot, configure pads) -> - * GPIO input (FSP, detect) -> CLKREQ (FSP). - * - * Also if GpioOverride=1 the NAF_VME bit is not set for virtual wire GPIOs - * that require it, e.g. the CPU PCIe CLKREQ bus. The pads that should not be - * touched by coreboot are left commented in this file for reference. CLKREQ - * reprogramming caused undefined behavior when ASPM and Clock PM was being - * enabled by coreboot on PCIe endpoints of CPU PCIe x4 slot (coreboot printed - * a lot of exceptions and simply halted). - */ - /* Pad configuration was generated automatically using intelp2m utility */ static const struct pad_config gpio_table[] = { @@ -137,11 +121,10 @@ PAD_CFG_GPI_TRIG_OWN(GPP_J6, NONE, PLTRST, OFF, ACPI), /* GPP_J7 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_J7, NONE, PLTRST, OFF, ACPI), - /* Let FSP enable the respective CLKREQ pins, see comment at the top of file */ - /* GPP_J8 - SRCCLKREQ16# */ - // PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), + /* GPP_J8 - GPIO */ + PAD_NC(GPP_J8, NONE), /* GPP_J9 - SRCCLKREQ17# */ - // PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1), /* GPP_J10 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_J10, NONE, PLTRST, OFF, ACPI), /* GPP_J11 - GPIO */ @@ -270,24 +253,22 @@ PAD_CFG_GPI_TRIG_OWN(GPP_H0, NONE, PLTRST, OFF, ACPI), /* GPP_H1 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_H1, NONE, PLTRST, OFF, ACPI), - /* Let FSP enable the respective CLKREQ pins, see comment at the top of file */ /* GPP_H2 - SRCCLKREQ8# */ - // PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), /* GPP_H3 - SRCCLKREQ9# */ - // PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), /* GPP_H4 - SRCCLKREQ10# */ - // PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), - /* GPP_H5 - SRCCLKREQ11# */ - // PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* GPP_H5 - GPIO */ + PAD_NC(GPP_H5, NONE), /* GPP_H6 - SRCCLKREQ12# */ - // PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), /* GPP_H7 - SRCCLKREQ13# */ - // PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), /* GPP_H8 - SRCCLKREQ14# */ - // PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* GPP_H9 - SRCCLKREQ15# */ - // PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), - + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* GPP_H10 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_H10, NONE, PLTRST, OFF, ACPI), /* GPP_H11 - GPIO */ @@ -434,51 +415,90 @@ /* GPP_C23 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_C23, NONE, PLTRST, OFF, ACPI), - /* TODO: move VW programming to soc directory and make it dependent on FSP settings? */ - /* Let FSP enable the respective CLKREQ pins, see comment at the top of file */ - /* CPU PCIe 6.0 CLKREQ virtual wire message bus */ - // _PAD_CFG_STRUCT(VGPIO_PCIE_0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), - // _PAD_CFG_STRUCT(VGPIO_PCIE_1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), - // _PAD_CFG_STRUCT(VGPIO_PCIE_2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), - // _PAD_CFG_STRUCT(VGPIO_PCIE_3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), - // _PAD_CFG_STRUCT(VGPIO_PCIE_4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), - // _PAD_CFG_STRUCT(VGPIO_PCIE_5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), - // _PAD_CFG_STRUCT(VGPIO_PCIE_6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), - // _PAD_CFG_STRUCT(VGPIO_PCIE_7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), - // _PAD_CFG_STRUCT(VGPIO_PCIE_8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), - // _PAD_CFG_STRUCT(VGPIO_PCIE_9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), - // _PAD_CFG_STRUCT(VGPIO_PCIE_10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), - // _PAD_CFG_STRUCT(VGPIO_PCIE_11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), - // _PAD_CFG_STRUCT(VGPIO_PCIE_12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), - // _PAD_CFG_STRUCT(VGPIO_PCIE_13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), - // _PAD_CFG_STRUCT(VGPIO_PCIE_14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), - // _PAD_CFG_STRUCT(VGPIO_PCIE_15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), - // _PAD_CFG_STRUCT(VGPIO_PCIE_64, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), - // _PAD_CFG_STRUCT(VGPIO_PCIE_65, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), - // _PAD_CFG_STRUCT(VGPIO_PCIE_66, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), - // _PAD_CFG_STRUCT(VGPIO_PCIE_67, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + /* CPU PCIe CLKREQ virtual wire message buses */ + _PAD_CFG_STRUCT(VGPIO_PCIE_0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_64, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_65, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_66, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_67, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), - /* CPU PCIe 1.0 CLKREQ virtual wire message bus */ - // _PAD_CFG_STRUCT(VGPIO_PCIE_16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), - // _PAD_CFG_STRUCT(VGPIO_PCIE_17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), - // _PAD_CFG_STRUCT(VGPIO_PCIE_18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), - // _PAD_CFG_STRUCT(VGPIO_PCIE_19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), - // _PAD_CFG_STRUCT(VGPIO_PCIE_20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), - // _PAD_CFG_STRUCT(VGPIO_PCIE_21, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), - // _PAD_CFG_STRUCT(VGPIO_PCIE_22, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), - // _PAD_CFG_STRUCT(VGPIO_PCIE_23, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), - // _PAD_CFG_STRUCT(VGPIO_PCIE_24, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), - // _PAD_CFG_STRUCT(VGPIO_PCIE_25, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), - // _PAD_CFG_STRUCT(VGPIO_PCIE_26, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), - // _PAD_CFG_STRUCT(VGPIO_PCIE_27, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), - // _PAD_CFG_STRUCT(VGPIO_PCIE_28, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), - // _PAD_CFG_STRUCT(VGPIO_PCIE_29, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), - // _PAD_CFG_STRUCT(VGPIO_PCIE_30, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), - // _PAD_CFG_STRUCT(VGPIO_PCIE_31, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), - // _PAD_CFG_STRUCT(VGPIO_PCIE_68, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), - // _PAD_CFG_STRUCT(VGPIO_PCIE_69, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), - // _PAD_CFG_STRUCT(VGPIO_PCIE_70, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), - // _PAD_CFG_STRUCT(VGPIO_PCIE_71, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_21, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_22, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_23, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_24, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_25, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_26, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_27, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_28, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_29, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_30, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_31, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_68, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_69, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_70, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_71, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + + _PAD_CFG_STRUCT(VGPIO_PCIE_32, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_33, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_34, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_35, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_36, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_37, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_38, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_39, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_40, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_41, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_42, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_43, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_44, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_45, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_46, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_47, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_72, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_73, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_74, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_75, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + + _PAD_CFG_STRUCT(VGPIO_PCIE_48, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_49, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_50, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_51, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_52, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_53, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_54, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_55, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_56, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_57, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_58, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_59, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_60, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_61, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_62, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_63, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_76, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_77, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_78, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_79, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), /* ------- GPIO Community 4 ------- */ @@ -630,9 +650,8 @@ /* ------- GPIO Group GPP_D ------- */ - /* Let FSP enable the respective CLKREQ pins, see comment at the top of file */ - /* GPP_D0 - CLKREQ0# */ - // PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), + /* GPP_D0 - SRCCLKREQ0# */ + PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), /* GPP_D1 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D1, NONE, PLTRST, OFF, ACPI), /* GPP_D2 - GPIO */ diff --git a/src/mainboard/msi/ms7d25/romstage_fsp_params.c b/src/mainboard/msi/ms7d25/romstage_fsp_params.c index 9199a81..5d535ed 100644 --- a/src/mainboard/msi/ms7d25/romstage_fsp_params.c +++ b/src/mainboard/msi/ms7d25/romstage_fsp_params.c @@ -46,14 +46,6 @@ memupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1; memupd->FspmConfig.PchHdaSdiEnable[0] = 1; - /* - * Let FSP configure virtual wires, CLKREQs, etc. - * Otherwise undefined behaviour occurs when coreboot enables ASPM on - * CPU PCIe root ports. This is caused by FSP reprogramming certain - * pads including CLKREQ pins, despite GpioOverride = 1. - */ - memupd->FspmConfig.GpioOverride = 0; - memcfg_init(memupd, &ddr4_mem_config, &dimm_module_spd_info, false); gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); -- To view, visit https://review.coreboot.org/c/coreboot/+/69823 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01dc83ce23ca27525b8905665da942510f249824 Gerrit-Change-Number: 69823 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: mb/msi/ms7d25: Disable PCIe hotplug
by Michał Żygowski (Code Review) 18 Nov '22

18 Nov '22

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69822 ) Change subject: mb/msi/ms7d25: Disable PCIe hotplug ...................................................................... mb/msi/ms7d25: Disable PCIe hotplug The support for the board has stabilized and PCIe ports have been tested with many devices. Although hotplug is not commonly used and it seems pointless to keep it enabled, so disable it. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I338c55cb57d971badd08235b71626a710fafb829 --- M src/mainboard/msi/ms7d25/devicetree.cb 1 file changed, 18 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/69822/1 diff --git a/src/mainboard/msi/ms7d25/devicetree.cb b/src/mainboard/msi/ms7d25/devicetree.cb index 189faf6..49e06de 100644 --- a/src/mainboard/msi/ms7d25/devicetree.cb +++ b/src/mainboard/msi/ms7d25/devicetree.cb @@ -96,7 +96,7 @@ register "cpu_pcie_rp[CPU_RP(2)]" = "{ .clk_src = 0, .clk_req = 0, - .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_HOTPLUG, + .flags = PCIE_RP_LTR | PCIE_RP_AER, .PcieRpL1Substates = L1_SS_L1_2, .pcie_rp_aspm = ASPM_L0S_L1, }" @@ -139,7 +139,7 @@ register "pch_pcie_rp[PCH_RP(1)]" = "{ .clk_src = 10, .clk_req = 10, - .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_HOTPLUG | PCIE_RP_CLK_REQ_DETECT, + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT, .PcieRpL1Substates = L1_SS_L1_2, .pcie_rp_aspm = ASPM_L0S_L1, }" @@ -150,7 +150,7 @@ register "pch_pcie_rp[PCH_RP(2)]" = "{ .clk_src = 17, .clk_req = 17, - .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_HOTPLUG | PCIE_RP_CLK_REQ_DETECT, + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT, .PcieRpL1Substates = L1_SS_L1_2, .pcie_rp_aspm = ASPM_L0S_L1, }" @@ -172,7 +172,7 @@ register "pch_pcie_rp[PCH_RP(5)]" = "{ .clk_src = 15, .clk_req = 15, - .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_HOTPLUG | PCIE_RP_CLK_REQ_DETECT, + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT, .PcieRpL1Substates = L1_SS_L1_2, .pcie_rp_aspm = ASPM_L0S_L1, }" -- To view, visit https://review.coreboot.org/c/coreboot/+/69822 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I338c55cb57d971badd08235b71626a710fafb829 Gerrit-Change-Number: 69822 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: security/tpm/tspi/log.c: fix strncpy() usage
by Sergii Dmytruk (Code Review) 18 Nov '22

18 Nov '22

Attention is currently required from: Michał Żygowski, Christian Walter. Sergii Dmytruk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69708 ) Change subject: security/tpm/tspi/log.c: fix strncpy() usage ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > This is still custom coreboot format right? Yes. > It is up to the parser to respect the format and be aware that the fields do not necessarily have to be NULL-terminated. I don't think that was the original intent. If it was, the whole field would be used, but the code explicitly doesn't write last byte as if assuming it to be zero to guarantee string termination. -- To view, visit https://review.coreboot.org/c/coreboot/+/69708 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib24129829bef3764a8ba1e2c0d92bc42c5cfbc8d Gerrit-Change-Number: 69708 Gerrit-PatchSet: 1 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Comment-Date: Fri, 18 Nov 2022 16:18:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/zork: Select VBOOT by default
by Felix Held (Code Review) 18 Nov '22

18 Nov '22

Attention is currently required from: Jason Nien, Matt DeVillier, Martin Roth. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69763 ) Change subject: mb/google/zork: Select VBOOT by default ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/zork/Kconfig: https://review.coreboot.org/c/coreboot/+/69763/comment/77efa234_9658b8b9 PS2, Line 108: would be good to add a comment that points out that this is done due to psp verstage being mandatory on chrome silicon -- To view, visit https://review.coreboot.org/c/coreboot/+/69763 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2447bf69baefd5560a0153dcd3d9b87b0a91a3f9 Gerrit-Change-Number: 69763 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Fri, 18 Nov 2022 16:10:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: drivers/i2c/rx6110sa/rx6110sa.c: Make log messages consistent
by Felix Held (Code Review) 18 Nov '22

18 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69718 ) Change subject: drivers/i2c/rx6110sa/rx6110sa.c: Make log messages consistent ...................................................................... drivers/i2c/rx6110sa/rx6110sa.c: Make log messages consistent Set the logging message prefix to the device name instead of the device path in order to make the output consistent with other logging messages in this and other drivers. Change-Id: Ib63b93d52aad220d17f1f4ee0d47a949933ec26d Signed-off-by: Jan Samek <jan.samek(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69718 Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/drivers/i2c/rx6110sa/rx6110sa.c 1 file changed, 19 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved Mario Scheithauer: Looks good to me, but someone else must approve diff --git a/src/drivers/i2c/rx6110sa/rx6110sa.c b/src/drivers/i2c/rx6110sa/rx6110sa.c index d30963c..02b3d9f 100644 --- a/src/drivers/i2c/rx6110sa/rx6110sa.c +++ b/src/drivers/i2c/rx6110sa/rx6110sa.c @@ -183,7 +183,7 @@ break; default: printk(BIOS_INFO, "%s: Bus speed unsupported, fall back to %d kHz!\n", - dev_path(dev), I2C_SPEED_STANDARD / 1000); + dev->chip_ops->name, I2C_SPEED_STANDARD / 1000); bus_speed = I2C_SPEED_STANDARD; break; } -- To view, visit https://review.coreboot.org/c/coreboot/+/69718 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib63b93d52aad220d17f1f4ee0d47a949933ec26d Gerrit-Change-Number: 69718 Gerrit-PatchSet: 2 Gerrit-Owner: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: mb/siemens/mc_ehl2/devicetree.cb: Use RV3028 bus_speed instead of dum...
by Felix Held (Code Review) 18 Nov '22

18 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69544 ) Change subject: mb/siemens/mc_ehl2/devicetree.cb: Use RV3028 bus_speed instead of dummy i2c device ...................................................................... mb/siemens/mc_ehl2/devicetree.cb: Use RV3028 bus_speed instead of dummy i2c device Instead of creating a dummy I2C device in order to force Linux to decrease the I2C bus speed, use the own 'bus_speed' field of RV3028 device config structure. Linux should always set the bus speed to the speed of the slowest device sitting on the bus. Hence the dummy device is not needed here anymore. BUG=none TEST=See if the RV3028 RTC is visible and working (date/time can be set/read) in Linux. At the time, a driver modification is needed to add a match table for the "MCRY3028" ACPI HID. A proper kernel patch is pending. Change-Id: I6e269dc67d1fe2a6747fcf3bee224def7b553f08 Signed-off-by: Jan Samek <jan.samek(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69544 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb 1 file changed, 29 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Mario Scheithauer: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index 3b54f24..4dd062c 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -147,6 +147,7 @@ device pci 15.1 on # I2C1 # Enable external RTC chip chip drivers/i2c/rv3028c7 + register "bus_speed" = "I2C_SPEED_STANDARD" register "set_user_date" = "1" register "user_year" = "04" register "user_month" = "07" @@ -156,12 +157,6 @@ register "cap_charge" = "CHARGE_OFF" device i2c 0x52 on end # RTC RV3028-C7 end - # Add dummy I2C device to limit BUS speed to 100 kHz in OS - chip drivers/i2c/generic - register "hid" = ""PRP0001"" - register "speed" = "I2C_SPEED_STANDARD" - device i2c 0x7f on end - end end device pci 15.2 on # I2C2 # Add dummy I2C device to limit BUS speed to 100 kHz in OS -- To view, visit https://review.coreboot.org/c/coreboot/+/69544 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e269dc67d1fe2a6747fcf3bee224def7b553f08 Gerrit-Change-Number: 69544 Gerrit-PatchSet: 6 Gerrit-Owner: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: drivers/i2c/rv3028c7: Add ACPI generation callbacks
by Felix Held (Code Review) 18 Nov '22

18 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69543 ) Change subject: drivers/i2c/rv3028c7: Add ACPI generation callbacks ...................................................................... drivers/i2c/rv3028c7: Add ACPI generation callbacks Add ACPI generation callback to the driver after obtaining the ACPI HID "MCRY3028" for this device from Microcrystal AG (VID: "MCRY"). Also add I2C bus speed field to the device config structure, which is a required ACPI entry. BUG=none TEST=Disassemble the SSDT table and see whether the device entry "MC28" is generated correctly. Also check whether the RV3028 driver in Linux (drivers/rtc/rtc-rv-3028.c) is bound correctly after adding an ACPI match table to it containing the HID. A proper kernel patch is pending. Change-Id: I3b8cf5c8dc551439755992ff05b6693e91cc3f21 Signed-off-by: Jan Samek <jan.samek(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69543 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/drivers/i2c/rv3028c7/chip.h M src/drivers/i2c/rv3028c7/rv3028c7.c M src/drivers/i2c/rv3028c7/rv3028c7.h 3 files changed, 93 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/drivers/i2c/rv3028c7/chip.h b/src/drivers/i2c/rv3028c7/chip.h index 0ac4005..0ed86ff 100644 --- a/src/drivers/i2c/rv3028c7/chip.h +++ b/src/drivers/i2c/rv3028c7/chip.h @@ -35,6 +35,7 @@ }; struct drivers_i2c_rv3028c7_config { + unsigned int bus_speed; /* Bus clock in Hz */ unsigned char user_weekday; /* User day of the week to set */ unsigned char user_day; /* User day to set */ unsigned char user_month; /* User month to set */ diff --git a/src/drivers/i2c/rv3028c7/rv3028c7.c b/src/drivers/i2c/rv3028c7/rv3028c7.c index e7e3b47..87cbc24 100644 --- a/src/drivers/i2c/rv3028c7/rv3028c7.c +++ b/src/drivers/i2c/rv3028c7/rv3028c7.c @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_device.h> +#include <acpi/acpigen.h> #include <commonlib/bsd/bcd.h> #include <console/console.h> #include <delay.h> @@ -176,11 +178,71 @@ } } +#if CONFIG(HAVE_ACPI_TABLES) +static void rv3028c7_fill_ssdt(const struct device *dev) +{ + const char *scope = acpi_device_scope(dev); + struct drivers_i2c_rv3028c7_config *config = dev->chip_info; + enum i2c_speed bus_speed; + + if (!scope) + return; + + switch (config->bus_speed) { + case I2C_SPEED_STANDARD: + case I2C_SPEED_FAST: + bus_speed = config->bus_speed; + break; + default: + bus_speed = I2C_SPEED_STANDARD; + printk(BIOS_INFO, "%s: Bus speed unsupported, fall back to %d kHz!\n", + dev->chip_ops->name, bus_speed / 1000); + break; + } + + struct acpi_i2c i2c = { + .address = dev->path.i2c.device, + .mode_10bit = dev->path.i2c.mode_10bit, + .speed = bus_speed, + .resource = scope, + }; + + /* Device */ + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_string("_HID", RV3028C7_HID_NAME); + acpigen_write_name_string("_DDN", RV3028C7_HID_DESC); + acpigen_write_STA(acpi_device_status(dev)); + + /* Resources */ + acpigen_write_name("_CRS"); + + acpigen_write_resourcetemplate_header(); + acpi_device_write_i2c(&i2c); + acpigen_write_resourcetemplate_footer(); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), dev->chip_ops->name, + dev_path(dev)); +} + +static const char *rv3028c7_acpi_name(const struct device *dev) +{ + return RV3028C7_ACPI_NAME; +} +#endif + static struct device_operations rv3028c7_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, .init = rtc_init, .final = rtc_final, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_name = rv3028c7_acpi_name, + .acpi_fill_ssdt = rv3028c7_fill_ssdt, +#endif }; static void rtc_enable(struct device *dev) diff --git a/src/drivers/i2c/rv3028c7/rv3028c7.h b/src/drivers/i2c/rv3028c7/rv3028c7.h index 55617a7..b1f9971 100644 --- a/src/drivers/i2c/rv3028c7/rv3028c7.h +++ b/src/drivers/i2c/rv3028c7/rv3028c7.h @@ -3,6 +3,10 @@ #ifndef _I2C_RV3028C7_H_ #define _I2C_RV3028C7_H_ +#define RV3028C7_ACPI_NAME "MC28" +#define RV3028C7_HID_NAME "MCRY3028" +#define RV3028C7_HID_DESC "Real Time Clock" + /* Register layout */ #define SECOND_REG 0x00 #define MINUTE_REG 0x01 -- To view, visit https://review.coreboot.org/c/coreboot/+/69543 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b8cf5c8dc551439755992ff05b6693e91cc3f21 Gerrit-Change-Number: 69543 Gerrit-PatchSet: 5 Gerrit-Owner: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: lib/malloc.c: Fix log messages
by Felix Held (Code Review) 18 Nov '22

18 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69624 ) Change subject: lib/malloc.c: Fix log messages ...................................................................... lib/malloc.c: Fix log messages It is no longer necessary to explicitly add "Warning" in front of BIOS_WARNING message. Change-Id: I6e4341555a3b03a531bd94ba5e36cbcadda9c663 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69624 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/lib/malloc.c 1 file changed, 18 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/lib/malloc.c b/src/lib/malloc.c index 8ad038a..2c73219 100644 --- a/src/lib/malloc.c +++ b/src/lib/malloc.c @@ -72,7 +72,7 @@ return; if (ptr < (void *)&_heap || ptr >= free_mem_end_ptr) { - printk(BIOS_WARNING, "Warning - Pointer passed to %s is not " + printk(BIOS_WARNING, "Pointer passed to %s is not " "pointing to the heap\n", __func__); return; } -- To view, visit https://review.coreboot.org/c/coreboot/+/69624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e4341555a3b03a531bd94ba5e36cbcadda9c663 Gerrit-Change-Number: 69624 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: lib/malloc.c: Fix log messages
by Felix Held (Code Review) 18 Nov '22

18 Nov '22

Attention is currently required from: Elyes Haouas. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69624 ) Change subject: lib/malloc.c: Fix log messages ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e4341555a3b03a531bd94ba5e36cbcadda9c663 Gerrit-Change-Number: 69624 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 18 Nov 2022 16:02:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2022