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Change subject: device/pciexp: add pcie_find_dsn()
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Patch Set 14: Code-Review+2
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Change subject: acpi: Add initial support for CEDT
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Patch Set 9: Code-Review+2
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Change subject: soc/amd/common/acpi: Implement DTTS Proposal
......................................................................
Patch Set 57:
(3 comments)
Patchset:
PS30:
> I found that I will get 3 body detection events continuously during boot without body status change. […]
Done
File src/mainboard/google/skyrim/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/68471/comment/23b31ac6_18d2830c
PS30, Line 18: variants/winterhold/DTTS.asl
> I move DTTS. […]
Done
File src/soc/amd/common/acpi/dptc.asl:
https://review.coreboot.org/c/coreboot/+/68471/comment/381bf476_2237303b
PS21, Line 46: // AMB sensor trigger point
> I update the commit description with table translation rule and new code change following these rule […]
Done
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Change subject: cpu/intel/socket_*: Clean up Kconfig files
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/69447/comment/8bc3fcf8_dcede6eb
PS3, Line 10: Move MAX_CPUS to mainboards.
> The problem with having the defaults for `MAX_CPUS` in `cpu/intel/model_*/Kconfig` is that sockets that support multiple CPU models (e.g. LGA775) could end up using an incorrect default depending on the order in which the CPU models' Kconfig files are included. This happens because of the way Kconfig handles defaults (it uses the first applicable value it finds).
>
> It's true that the status quo for `MAX_CPUS` defaults in pre-SoC Intel platforms isn't very consistent. There's some defaults in CPU-model Kconfig (model_2065x, model_206ax, haswell: the corresponding socket Kconfigs got dropped for the sake of simplicity), others in CPU-socket Kconfig (socket_BGA956, socket_FCBGA559, socket_p) and others in northbridge Kconfig (i945, x4x).
>
> If you'd like to clean some things up, you can start with moving `MAX_CPUS` defaults from the northbridges to the corresponding CPU sockets. i945 is paired with LGA775 and socket_441 (both sockets support up to 4 CPUs), and x4x is only paired with LGA775 in coreboot.
>
Not true. i945 only supports dual core CPUs. Quad cores fail to boot regardless of them actually fitting in the socket and this is a hardware limitation afaik. Putting that limitation in the northbridge code is appropriate.
> Note: Boards that pair x4x with socket_p exist (e.g. Dell Precision M6400), but they're rare and none of them has coreboot support yet. While both socket_p and x4x provide the same default for `MAX_CPUS` (4), moving the values to sockets would remove the redundancy.
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Change subject: cpu/intel/socket_*: Clean up Kconfig files
......................................................................
Patch Set 4:
(1 comment)
File src/cpu/intel/socket_BGA956/Kconfig:
https://review.coreboot.org/c/coreboot/+/69447/comment/166c44f1_47277841
PS4, Line 9: select MMX
> It's not even used. You can remove CONFIG_MMX, and we can probably assume all x86 CPUs have MMX.
Ignore, MMX is used by the top-level Makefile. If anything, making it enabled by default and disabling it from Quark (seems to be the only x86 that doesn't support MMX) would be tidier.
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Change subject: Documentation/measured_boot.md: document new TPM options
......................................................................
Patch Set 10:
(2 comments)
File Documentation/security/vboot/measured_boot.md:
https://review.coreboot.org/c/coreboot/+/68752/comment/fa7142bb_5817854a
PS9, Line 84: [TPM12]: https://trustedcomputinggroup.org/wp-content/uploads/TCG_PCClientImplementa…
: [TPM20]: https://trustedcomputinggroup.org/wp-content/uploads/TCG_PCClient_PFP_r1p05…
:
> Please move links to the bottom of the file
Done
https://review.coreboot.org/c/coreboot/+/68752/comment/e7bd845d_d87f2529
PS9, Line 254:
> So what will be the PCR0 usage here?
Specified explicitly that it's unused in this case.
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Change subject: util/cbmem: add parsing of TPM logs per standard
......................................................................
Patch Set 9:
(1 comment)
File src/lib/coreboot_table.c:
https://review.coreboot.org/c/coreboot/+/68749/comment/709466e7_800bac5b
PS8, Line 298: const struct tpm_log_ref *range = cbmem_find(CBMEM_ID_TPM_LOG_REF);
> I don't get it why do we need to define yet another CBMEM ID. […]
Thanks for noticing this, it was necessary at some point, but not anymore.
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Change subject: security/tpm: add TPM log format as per 1.2 spec
......................................................................
Patch Set 8:
(6 comments)
File src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h:
https://review.coreboot.org/c/coreboot/+/68747/comment/f685f234_d2c41e7c
PS7, Line 143: { CBMEM_ID_TPM_LOG, "TPM STD LOG" }, \
> Why do we create a new cbmem ID? We already have IDs TPM logs: […]
Because existing code makes assumptions about format of data based on cbmem IDs. Reusing the ID will break the code, it's not always possible to determine the log format based on data and existing code isn't even trying to. E.g. `CBMEM_ID_TPM2_TCG_LOG` is used by `src/acpi/acpi.c` and is not compatible with a regular TPM log.
File src/security/tpm/Kconfig:
https://review.coreboot.org/c/coreboot/+/68747/comment/be947940_5b53f672
PS5, Line 108: bool "TPM 1.2 format"
> Exactly, TPM2 should have different format. […]
Done
File src/security/tpm/Kconfig:
https://review.coreboot.org/c/coreboot/+/68747/comment/9292b49c_2c554eaf
PS7, Line 100: default TPM_LOG_TPM1 if TPM1
Well, https://ticket.coreboot.org/issues/422 says:
> New entries should default to one of TCG formats, depending on selected TPM family. Choice of other format shouldn't be restricted.
I thought it means log version should be chosen by the user.
File src/security/tpm/tpm1_log_serialized.h:
https://review.coreboot.org/c/coreboot/+/68747/comment/dac58786_b324878e
PS7, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */
> This file could be commonlib with BSD license isn't it? […]
`commonlib/tpm_log_serialized.h` is licensed as `GPL-2.0-only`.
I did try having a single header, it's a bit messy, but the much bigger problem is that it can't work for TPM2 log because it uses `CONFIG()` macro to which `cbmem` has no access.
https://review.coreboot.org/c/coreboot/+/68747/comment/ba692641_9be9d19f
PS7, Line 13: #define TPM_1_LOG_VI_MAGIC 0x31544243 /* "CBT1" in LE */
> For ACPI table we use "COREv4" as OEM ID and "CORE" as ASL compiler. […]
And use the same ID for TPM1 and TPM2 logs?
File src/security/tpm/tspi/log-tpm1.c:
https://review.coreboot.org/c/coreboot/+/68747/comment/49f6b205_70e6aada
PS7, Line 16: void *tpm_log_cbmem_init(void)
> If it is source file for TPM1. […]
These functions are called from shared code which doesn't know what log format is used. I can change names only by adding one more function to pick the implementation based on `CONFIG()` options, which can also be done later.
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