coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

1 participants
7286 discussions

[M] Change in coreboot[master]: build: List all Kconfigs in CBFS `config` file, compress it
by Martin Roth (Code Review) 18 Nov '22

18 Nov '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69710 ) Change subject: build: List all Kconfigs in CBFS `config` file, compress it ...................................................................... build: List all Kconfigs in CBFS `config` file, compress it The coreboot build system automatically adds a `config` file to CBFS that lists the exact Kconfig configuration that this image was built with. This is useful to reproduce a build after the fact or to check whether support for a specific feature is enabled in the image. However, the file is currently generated using the `savedefconfig` command to Kconfig, which generates the minimal .config file that is needed to produce the required config in a coreboot build. This is fine for reproduction, but bad when you want to check if a certain config was enabled, since many configs get enabled by default or pulled in through another config's `select` statement and thus don't show up in the defconfig. This patch tries to fix that second use case by instead including the full .config instead. In order to save some space, we can remove all comments (e.g. `# CONFIG_XXX is not set`) from the file, which still makes it easy to test for a specific config (if it's in the file you can extract the right value, if not you can assume it was set to `n`). We can also LZMA compress it since this file is never read by firmware itself and only intended for later re-extraction via cbfstool, which always has LZMA support included. On a sample Trogdor device the existing (uncompressed) `config` file takes up 519 bytes in CBFS, whereas the new (compressed) file after this patch will take up 1832 bytes -- still a small amount that should hopefully not break the bank for anyone. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I5259ec6f932cdc5780b8843f46dd476da9d19728 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69710 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Jakub Czapiga <jacz(a)semihalf.com> Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> --- M Makefile.inc M src/Kconfig 2 files changed, 50 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Jakub Czapiga: Looks good to me, but someone else must approve Martin Roth: Looks good to me, approved diff --git a/Makefile.inc b/Makefile.inc index b4c2cdf..ef565c2 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -305,17 +305,15 @@ mv $(2).tmp $(2)) ####################################################################### -# Reduce a .config file to its minimal representation +# Reduce a .config file by removing lines about unset booleans # arg1: input # arg2: output -define cbfs-files-processor-defconfig - $(eval $(2): $(1) $(obj)/build.h $(objutil)/kconfig/conf; \ +define cbfs-files-processor-config + $(eval $(2): $(1) $(obj)/build.h; \ +printf " CREATE $(2) (from $(1))\n"; \ printf "# This image was built using coreboot " > $(2).tmp && \ grep "\<COREBOOT_VERSION\>" $(obj)/build.h |cut -d\" -f2 >> $(2).tmp && \ - $(MAKE) DOTCONFIG=$(1) DEFCONFIG=$(2).tmp2 savedefconfig && \ - cat $(2).tmp2 >> $(2).tmp && \ - rm -f $(2).tmp2 && \ + sed -e '/^CONFIG/!d' $(1) >> $(2).tmp && \ \mv -f $(2).tmp $(2)) endef @@ -1212,8 +1210,9 @@ vgaroms/seavgabios.bin-type := raw cbfs-files-$(CONFIG_INCLUDE_CONFIG_FILE) += config -config-file := $(DOTCONFIG):defconfig +config-file := $(DOTCONFIG):config config-type := raw +config-compression := LZMA cbfs-files-$(CONFIG_INCLUDE_CONFIG_FILE) += revision revision-file := $(obj)/build.h diff --git a/src/Kconfig b/src/Kconfig index f30a1bb..f16b53c 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -211,9 +211,9 @@ Saying Y here will increase the image size by 2-3KB. - You can use the following command to easily list the options: + You can then use cbfstool to extract the config from a final image: - grep -a CONFIG_ coreboot.rom + cbfstool coreboot.rom extract -n config -f <output file path> Alternatively, you can also use cbfstool to print the image contents (including the raw 'config' item we're looking for). -- To view, visit https://review.coreboot.org/c/coreboot/+/69710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5259ec6f932cdc5780b8843f46dd476da9d19728 Gerrit-Change-Number: 69710 Gerrit-PatchSet: 3 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: acpi/Kconfig: Remove unused ACPI_EINJ config option
by Nico Huber (Code Review) 18 Nov '22

18 Nov '22

Attention is currently required from: Lance Zhao, David Hendricks, Tim Wawrzynczak, Eric Lai, Elyes Haouas. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68593 ) Change subject: acpi/Kconfig: Remove unused ACPI_EINJ config option ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > If this were entirely SOC-specific then I would agree that it should be kept with non-public downstr […] Just to make sure we're on the same page: Did anyone see a `CONFIG_ACPI_EINJ`, `CONFIG(ACPI_EINJ)` or any other reference in a Kconfig file to `ACPI_EINJ` downstream? IOW did anybody look into if this change affects the downstream code at all? -- To view, visit https://review.coreboot.org/c/coreboot/+/68593 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I222478572a9e5efadd6719a164558833298e4c99 Gerrit-Change-Number: 68593 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Hendricks <david.hendricks(a)gmail.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-CC: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Lance Zhao Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 18 Nov 2022 17:08:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: David Hendricks <david.hendricks(a)gmail.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: libpayload: Fix compiler warning
by Nico Huber (Code Review) 18 Nov '22

18 Nov '22

Attention is currently required from: Thomas Heijligen. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69764 ) Change subject: libpayload: Fix compiler warning ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69764/comment/7bd9b655_4edae86c PS1, Line 7: warning warning*s* -- To view, visit https://review.coreboot.org/c/coreboot/+/69764 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id285c24cba790f181fa203f3117e5df35bed27c4 Gerrit-Change-Number: 69764 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Comment-Date: Fri, 18 Nov 2022 17:03:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[L] Change in coreboot[master]: [WIP] mb/prodrive/atlas: Populate smbios table with VPD from ECs EMI
by David Milosevic (Code Review) 18 Nov '22

18 Nov '22

Attention is currently required from: Maximilian Brune, Angel Pons, Arthur Heymans, Lean Sheng Tan. David Milosevic has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68137 ) Change subject: [WIP] mb/prodrive/atlas: Populate smbios table with VPD from ECs EMI ...................................................................... Patch Set 12: (1 comment) File src/mainboard/prodrive/atlas/vpd.h: https://review.coreboot.org/c/coreboot/+/68137/comment/34cfba15_0fea86be PS11, Line 13: __packed > Yep, I can remove that. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/68137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47bb4883c43ff344a9bda92c3106dd025533b391 Gerrit-Change-Number: 68137 Gerrit-PatchSet: 12 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Fri, 18 Nov 2022 17:02:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-MessageType: comment

1 0

[L] Change in coreboot[master]: [WIP] mb/prodrive/atlas: Populate smbios table with VPD from ECs EMI
by David Milosevic (Code Review) 18 Nov '22

18 Nov '22

Attention is currently required from: Maximilian Brune, Angel Pons, Arthur Heymans, Lean Sheng Tan. Hello build bot (Jenkins), Christian Walter, Angel Pons, Lean Sheng Tan, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68137 to look at the new patch set (#12). Change subject: [WIP] mb/prodrive/atlas: Populate smbios table with VPD from ECs EMI ...................................................................... [WIP] mb/prodrive/atlas: Populate smbios table with VPD from ECs EMI The embedded controller stores serial-number and part-number within an EEPROM which is unreachable to the Host CPU. Therefore, on the EC side, we set up a shared memory region with the help of EMI and copy the VPDs to it. On the coreboot side, we can read those back and populate the SMBios table type 1 with the serial-number and type 11 with the part-number. emi.*: small interface to access the EMI regions vpd.*: uses the emi interface in order to read the VPDs smbios.c: populates smbios type 1 with the serial-number by using vpd.h mainboard.c: uses vpd.h to add a string to smbios type 11 ld_config.*: offers functionality to configure logical devices devicetree.cb: enables address range 0xc00-0xcff for the EMI runtime registers Makefile.inc: adds emi.c, vpd.c, smbios.c, ld_config.c to the ramstage compilation TODO: ld_config.* is redundant. We can replace this with pnp_device.h or pnp_ops.h Signed-off-by: David Milosevic <David.Milosevic(a)9elements.com> Change-Id: I47bb4883c43ff344a9bda92c3106dd025533b391 --- M src/mainboard/prodrive/atlas/Makefile.inc M src/mainboard/prodrive/atlas/devicetree.cb A src/mainboard/prodrive/atlas/emi.c A src/mainboard/prodrive/atlas/emi.h A src/mainboard/prodrive/atlas/ld_config.c A src/mainboard/prodrive/atlas/ld_config.h M src/mainboard/prodrive/atlas/mainboard.c A src/mainboard/prodrive/atlas/smbios.c A src/mainboard/prodrive/atlas/vpd.c A src/mainboard/prodrive/atlas/vpd.h 10 files changed, 377 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/68137/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/68137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47bb4883c43ff344a9bda92c3106dd025533b391 Gerrit-Change-Number: 68137 Gerrit-PatchSet: 12 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[master]: util/kconfig: Add patch to move Kconfig deps to build/config
by Nico Huber (Code Review) 18 Nov '22

18 Nov '22

Attention is currently required from: Martin L Roth. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69535 ) Change subject: util/kconfig: Add patch to move Kconfig deps to build/config ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: Duplicate of CB:69450? -- To view, visit https://review.coreboot.org/c/coreboot/+/69535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4b48831705c3206e7c2e09f01d072d1cde9c9c4 Gerrit-Change-Number: 69535 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Fri, 18 Nov 2022 16:58:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: soc/amd/common/acpi: Implement DTTS Proposal
by build bot (Jenkins) (Code Review) 18 Nov '22

18 Nov '22

Attention is currently required from: Raul Rangel, Jason Nien, EricKY Cheng, Matt DeVillier, Paul Menzel, Eric Lai, Martin Roth, Tim Van Patten, Eric Peers, LeilaCY Lin, Jason Glenesk, Dtrain Hsu, Caveh Jalali, Tim Wawrzynczak, Fred Reitberger, Karthikeyan Ramasubramanian, Boris Mittelberg, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68471 ) Change subject: soc/amd/common/acpi: Implement DTTS Proposal ...................................................................... Patch Set 57: (3 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164060): https://review.coreboot.org/c/coreboot/+/68471/comment/ad01306f_74910fb4 PS57, Line 14: mode. Possible unwrapped commit description (prefer a maximum 72 chars per line) File src/soc/amd/common/acpi/dptc.asl: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164060): https://review.coreboot.org/c/coreboot/+/68471/comment/9553975b_39087b5e PS57, Line 21: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164060): https://review.coreboot.org/c/coreboot/+/68471/comment/5b2096d7_7adb7a94 PS57, Line 28: trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/68471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I866e5e497e2936984e713029b5f0b6d54cbc9622 Gerrit-Change-Number: 68471 Gerrit-PatchSet: 57 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: LeilaCY Lin <leilacy_lin(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: LeilaCY Lin <leilacy_lin(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 18 Nov 2022 16:38:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/amd/mendocino: Increase CBFS_MCACHE size
by Karthik Ramasubramanian (Code Review) 18 Nov '22

18 Nov '22

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69827 ) Change subject: soc/amd/mendocino: Increase CBFS_MCACHE size ...................................................................... soc/amd/mendocino: Increase CBFS_MCACHE size CBFS_MCACHE is currently experiencing overflow with CBFS verification enabled. Reduce the pre-x86 cbmem console size from ~5.5 KiB to 4 KiB. This reduction along with the available free space in PSP shared buffer (32 KiB) helps to increase the CBFS_MCACHE size from 8 KiB to required 14 KiB. BUG=b:259342909 TEST=Build and boot to OS in Skyrim. Ensure that there are no CBFS mcache overflows. FMAP: area COREBOOT found @ 80a000 (8347648 bytes) VB2:vb2_digest_init() 0 bytes, hash algo 2, HW acceleration unsupported CBFS: mcache @0x00019a40 built for 67 files, used 0x19a0 of 0x1c00 bytes CBFS: Found 'apu/amdfw_a' @0x0 size 0x3ff80 in mcache @0x0001b640 VB2:vb2_digest_init() 262016 bytes, hash algo 2, HW acceleration enabled Ensure that firmware_CbfsMcache FAFT test is successful. Change-Id: I35e1a8c6d73e0870b6a43aac604f83a0b6c3aabe Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/amd/mendocino/Kconfig 1 file changed, 28 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/69827/1 diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig index 05c349f..5dd2164 100644 --- a/src/soc/amd/mendocino/Kconfig +++ b/src/soc/amd/mendocino/Kconfig @@ -155,7 +155,7 @@ config PRE_X86_CBMEM_CONSOLE_SIZE hex - default 0x1600 + default 0x1000 help Size of the CBMEM console used in PSP verstage. @@ -167,7 +167,7 @@ config CBFS_MCACHE_SIZE hex - default 0x2000 if VBOOT_STARTS_BEFORE_BOOTBLOCK + default 0x3800 if VBOOT_STARTS_BEFORE_BOOTBLOCK config C_ENV_BOOTBLOCK_SIZE hex -- To view, visit https://review.coreboot.org/c/coreboot/+/69827 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35e1a8c6d73e0870b6a43aac604f83a0b6c3aabe Gerrit-Change-Number: 69827 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: mb/msi/ms7d25: Disable DMI ASPM
by Michał Żygowski (Code Review) 18 Nov '22

18 Nov '22

Attention is currently required from: Michał Kopeć. Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69826 ) Change subject: mb/msi/ms7d25: Disable DMI ASPM ...................................................................... mb/msi/ms7d25: Disable DMI ASPM Disable DMI link ASPM which can degrade performance of overall system. Desktop does not need to be concerned that much about idle power consumption. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I60af9d2ab2913db449059e1e007999fa2f307f5d --- M src/mainboard/msi/ms7d25/mainboard.c M src/mainboard/msi/ms7d25/romstage_fsp_params.c 2 files changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/69826/1 diff --git a/src/mainboard/msi/ms7d25/mainboard.c b/src/mainboard/msi/ms7d25/mainboard.c index 20b3817..9e676ce 100644 --- a/src/mainboard/msi/ms7d25/mainboard.c +++ b/src/mainboard/msi/ms7d25/mainboard.c @@ -86,6 +86,9 @@ params->PcieRpFunctionSwap = 0; params->CpuPcieRpFunctionSwap = 0; + params->PchLegacyIoLowLatency = 1; + params->PchDmiAspmCtrl = 0; + params->CpuPcieRpPmSci[0] = 1; // M2_1 params->CpuPcieRpPmSci[1] = 1; // PCI_E1 params->PcieRpPmSci[0] = 1; // PCI_E2 diff --git a/src/mainboard/msi/ms7d25/romstage_fsp_params.c b/src/mainboard/msi/ms7d25/romstage_fsp_params.c index b11991c..d176ac8 100644 --- a/src/mainboard/msi/ms7d25/romstage_fsp_params.c +++ b/src/mainboard/msi/ms7d25/romstage_fsp_params.c @@ -63,6 +63,8 @@ memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[1] = CONFIG(PCIEXP_CLK_PM); memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[2] = CONFIG(PCIEXP_CLK_PM); memupd->FspmConfig.DmiMaxLinkSpeed = 4; // Gen4 speed, undocumented + memupd->FspmConfig.DmiAspm = 0; + memupd->FspmConfig.DmiAspmCtrl = 0; memupd->FspmConfig.SkipExtGfxScan = 0; memupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/69826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60af9d2ab2913db449059e1e007999fa2f307f5d Gerrit-Change-Number: 69826 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: mb/msi/ms7d25: Configure ASPM and Clock PM based on Kconfig
by Michał Żygowski (Code Review) 18 Nov '22

18 Nov '22

Attention is currently required from: Michał Kopeć. Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69825 ) Change subject: mb/msi/ms7d25: Configure ASPM and Clock PM based on Kconfig ...................................................................... mb/msi/ms7d25: Configure ASPM and Clock PM based on Kconfig Add support for FSP ASPM and Clock PM configuration based on Kconfig. For some use cases it may be desirable to disable ASPM and Clock PM to achieve more deterministic and higher performance of PCIe devices. TEST=Boot MSI PRO Z690-A DDR4 without ASPM and Clock PM. Confirm all PCIe devices are still working and ASPM and Clock PM capabilities are not present on the PCIe Root Ports. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I6d9d11016bed89dcfee6909d0d3e3e2e56237a2f --- M src/mainboard/msi/ms7d25/devicetree.cb M src/mainboard/msi/ms7d25/gpio.h M src/mainboard/msi/ms7d25/mainboard.c M src/mainboard/msi/ms7d25/romstage_fsp_params.c 4 files changed, 204 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/69825/1 diff --git a/src/mainboard/msi/ms7d25/devicetree.cb b/src/mainboard/msi/ms7d25/devicetree.cb index f7a7ccf..fa46469 100644 --- a/src/mainboard/msi/ms7d25/devicetree.cb +++ b/src/mainboard/msi/ms7d25/devicetree.cb @@ -97,8 +97,6 @@ .clk_src = 0, .clk_req = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, - .PcieRpL1Substates = L1_SS_L1_2, - .pcie_rp_aspm = ASPM_L0S_L1, }" smbios_slot_desc "SlotTypePciExpressGen5x16" "SlotLengthLong" "PCI_E1" "SlotDataBusWidth16X" @@ -110,8 +108,6 @@ .clk_src = 9, .clk_req = 9, .flags = PCIE_RP_LTR | PCIE_RP_AER, - .PcieRpL1Substates = L1_SS_L1_2, - .pcie_rp_aspm = ASPM_L0S_L1, }" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M2_1" "SlotDataBusWidth4X" @@ -140,8 +136,6 @@ .clk_src = 10, .clk_req = 10, .flags = PCIE_RP_LTR | PCIE_RP_AER, - .PcieRpL1Substates = L1_SS_L1_2, - .pcie_rp_aspm = ASPM_L0S_L1, }" smbios_slot_desc "SlotTypePciExpressGen3X1" "SlotLengthShort" "PCI_E2" "SlotDataBusWidth1X" @@ -151,8 +145,6 @@ .clk_src = 17, .clk_req = 17, .flags = PCIE_RP_LTR | PCIE_RP_AER, - .PcieRpL1Substates = L1_SS_L1_2, - .pcie_rp_aspm = ASPM_L0S_L1, }" smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "PCI_E4" "SlotDataBusWidth1X" @@ -162,8 +154,6 @@ register "pch_pcie_rp[PCH_RP(3)]" = "{ .clk_src = 12, .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN, - .PcieRpL1Substates = L1_SS_L1_2, - .pcie_rp_aspm = ASPM_L0S_L1, }" end device ref pcie_rp4 off end @@ -173,8 +163,6 @@ .clk_src = 15, .clk_req = 15, .flags = PCIE_RP_LTR | PCIE_RP_AER, - .PcieRpL1Substates = L1_SS_L1_2, - .pcie_rp_aspm = ASPM_L0S_L1, }" smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "PCI_E3" "SlotDataBusWidth4X" @@ -185,8 +173,6 @@ .clk_src = 13, .clk_req = 13, .flags = PCIE_RP_LTR | PCIE_RP_AER, - .PcieRpL1Substates = L1_SS_L1_2, - .pcie_rp_aspm = ASPM_L0S_L1, }" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M2_3" "SlotDataBusWidth4X" @@ -209,8 +195,6 @@ .clk_src = 14, .clk_req = 14, .flags = PCIE_RP_LTR | PCIE_RP_AER, - .PcieRpL1Substates = L1_SS_L1_2, - .pcie_rp_aspm = ASPM_L0S_L1, }" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M2_4" "SlotDataBusWidth4X" @@ -221,8 +205,6 @@ .clk_src = 8, .clk_req = 8, .flags = PCIE_RP_LTR | PCIE_RP_AER, - .PcieRpL1Substates = L1_SS_L1_2, - .pcie_rp_aspm = ASPM_L0S_L1, }" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M2_2" "SlotDataBusWidth4X" diff --git a/src/mainboard/msi/ms7d25/gpio.h b/src/mainboard/msi/ms7d25/gpio.h index c388262..3d3e662 100644 --- a/src/mainboard/msi/ms7d25/gpio.h +++ b/src/mainboard/msi/ms7d25/gpio.h @@ -699,3 +699,109 @@ /* GPP_D23 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D23, NONE, PLTRST, OFF, ACPI), }; + +static const struct pad_config clkreq_disabled_table[] = { + /* GPP_J9 - SRCCLKREQ17# */ + PAD_NC(GPP_J9, NONE), + /* GPP_H2 - SRCCLKREQ8# */ + PAD_NC(GPP_H2, NONE), + /* GPP_H3 - SRCCLKREQ9# */ + PAD_NC(GPP_H3, NONE), + /* GPP_H4 - SRCCLKREQ10# */ + PAD_NC(GPP_H4, NONE), + /* GPP_H6 - SRCCLKREQ12# */ + PAD_NC(GPP_H6, NONE), + /* GPP_H7 - SRCCLKREQ13# */ + PAD_NC(GPP_H7, NONE), + /* GPP_H8 - SRCCLKREQ14# */ + PAD_NC(GPP_H8, NONE), + /* GPP_H9 - SRCCLKREQ15# */ + PAD_NC(GPP_H9, NONE), + /* GPP_D0 - SRCCLKREQ0# */ + PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), + + /* CPU PCIe CLKREQ virtual wire message buses */ + _PAD_CFG_STRUCT(VGPIO_PCIE_0, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_1, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_2, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_3, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_4, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_5, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_6, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_7, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_8, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_9, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_10, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_11, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_12, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_13, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_14, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_15, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_64, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_65, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_66, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_67, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + + _PAD_CFG_STRUCT(VGPIO_PCIE_16, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_17, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_18, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_19, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_20, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_21, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_22, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_23, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_24, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_25, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_26, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_27, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_28, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_29, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_30, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_31, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_68, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_69, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_70, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_71, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + + _PAD_CFG_STRUCT(VGPIO_PCIE_32, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_33, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_34, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_35, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_36, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_37, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_38, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_39, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_40, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_41, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_42, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_43, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_44, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_45, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_46, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_47, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_72, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_73, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_74, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_75, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + + _PAD_CFG_STRUCT(VGPIO_PCIE_48, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_49, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_50, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_51, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_52, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_53, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_54, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_55, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_56, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_57, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_58, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_59, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_60, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_61, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_62, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_63, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_76, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_77, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_78, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_79, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), +}; diff --git a/src/mainboard/msi/ms7d25/mainboard.c b/src/mainboard/msi/ms7d25/mainboard.c index 9c3a3ae..20b3817 100644 --- a/src/mainboard/msi/ms7d25/mainboard.c +++ b/src/mainboard/msi/ms7d25/mainboard.c @@ -59,6 +59,21 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) { + uint8_t aspm, aspm_l1; + + /* ASPM L1 sub-states require CLKREQ, so CLK_PM should be enabled as well */ + if (CONFIG(PCIEXP_L1_SUB_STATE) && CONFIG(PCIEXP_CLK_PM)) + aspm_l1 = 2; // 2 - L1.1 and L1.2 + else + aspm_l1 = 0; + + if (CONFIG(PCIEXP_ASPM)) { + aspm = CONFIG(PCIEXP_L1_SUB_STATE) ? 3 : 1; // 3 - L0sL1, 1 - L0s + } else { + aspm = 0; + aspm_l1 = 0; + } + memset(params->PcieRpEnableCpm, 0, sizeof(params->PcieRpEnableCpm)); memset(params->CpuPcieRpEnableCpm, 0, sizeof(params->CpuPcieRpEnableCpm)); memset(params->CpuPcieClockGating, 0, sizeof(params->CpuPcieClockGating)); @@ -81,13 +96,13 @@ params->PcieRpPmSci[20] = 1; // M2_4 params->PcieRpPmSci[24] = 1; // M2_2 - params->PcieRpMaxPayload[0] = 1; // PCI_E2 - params->PcieRpMaxPayload[1] = 1; // PCI_E4 - params->PcieRpMaxPayload[2] = 1; // Ethernet - params->PcieRpMaxPayload[4] = 1; // PCI_E3 - params->PcieRpMaxPayload[8] = 1; // M2_3 - params->PcieRpMaxPayload[20] = 1; // M2_4 - params->PcieRpMaxPayload[24] = 1; // M2_2 + params->PcieRpMaxPayload[0] = 1; // PCI_E2 + params->PcieRpMaxPayload[1] = 1; // PCI_E4 + params->PcieRpMaxPayload[2] = 1; // Ethernet + params->PcieRpMaxPayload[4] = 1; // PCI_E3 + params->PcieRpMaxPayload[8] = 1; // M2_3 + params->PcieRpMaxPayload[20] = 1; // M2_4 + params->PcieRpMaxPayload[24] = 1; // M2_2 params->CpuPcieRpTransmitterHalfSwing[0] = 1; // M2_1 params->CpuPcieRpTransmitterHalfSwing[1] = 1; // PCI_E1 @@ -99,12 +114,32 @@ params->PcieRpTransmitterHalfSwing[20] = 1; // M2_4 params->PcieRpTransmitterHalfSwing[24] = 1; // M2_2 - params->PcieRpEnableCpm[0] = 1; // PCI_E2 - params->PcieRpEnableCpm[1] = 1; // PCI_E4 - params->PcieRpEnableCpm[4] = 1; // PCI_E3 - params->PcieRpEnableCpm[8] = 1; // M2_3 - params->PcieRpEnableCpm[20] = 1; // M2_4 - params->PcieRpEnableCpm[24] = 1; // M2_2 + params->CpuPcieRpEnableCpm[0] = CONFIG(PCIEXP_CLK_PM); // M2_1 + params->CpuPcieRpEnableCpm[1] = CONFIG(PCIEXP_CLK_PM); // PCI_E1 + params->PcieRpEnableCpm[0] = CONFIG(PCIEXP_CLK_PM); // PCI_E2 + params->PcieRpEnableCpm[1] = CONFIG(PCIEXP_CLK_PM); // PCI_E4 + params->PcieRpEnableCpm[4] = CONFIG(PCIEXP_CLK_PM); // PCI_E3 + params->PcieRpEnableCpm[8] = CONFIG(PCIEXP_CLK_PM); // M2_3 + params->PcieRpEnableCpm[20] = CONFIG(PCIEXP_CLK_PM); // M2_4 + params->PcieRpEnableCpm[24] = CONFIG(PCIEXP_CLK_PM); // M2_2 + + params->CpuPcieRpL1Substates[0] = aspm_l1; // M2_1 + params->CpuPcieRpL1Substates[1] = aspm_l1; // PCI_E1 + params->PcieRpL1Substates[0] = aspm_l1; // PCI_E2 + params->PcieRpL1Substates[1] = aspm_l1; // PCI_E4 + params->PcieRpL1Substates[4] = aspm_l1; // PCI_E3 + params->PcieRpL1Substates[8] = aspm_l1; // M2_3 + params->PcieRpL1Substates[20] = aspm_l1; // M2_4 + params->PcieRpL1Substates[24] = aspm_l1; // M2_2 + + params->CpuPcieRpAspm[0] = aspm; // M2_1 + params->CpuPcieRpAspm[1] = aspm; // PCI_E1 + params->PcieRpAspm[0] = aspm; // PCI_E2 + params->PcieRpAspm[1] = aspm; // PCI_E4 + params->PcieRpAspm[4] = aspm; // PCI_E3 + params->PcieRpAspm[8] = aspm; // M2_3 + params->PcieRpAspm[20] = aspm; // M2_4 + params->PcieRpAspm[24] = aspm; // M2_2 params->PcieRpAcsEnabled[0] = 1; // PCI_E2 params->PcieRpAcsEnabled[1] = 1; // PCI_E4 @@ -114,17 +149,15 @@ params->PcieRpAcsEnabled[20] = 1; // M2_4 params->PcieRpAcsEnabled[24] = 1; // M2_2 - params->CpuPcieRpEnableCpm[0] = 1; // M2_1 - params->CpuPcieClockGating[0] = 1; - params->CpuPciePowerGating[0] = 1; + params->CpuPcieClockGating[0] = CONFIG(PCIEXP_CLK_PM); + params->CpuPciePowerGating[0] = CONFIG(PCIEXP_CLK_PM); params->CpuPcieRpMultiVcEnabled[0] = 1; params->CpuPcieRpPeerToPeerMode[0] = 1; params->CpuPcieRpMaxPayload[0] = 2; // 512B params->CpuPcieRpAcsEnabled[0] = 1; - params->CpuPcieRpEnableCpm[1] = 1; // PCI_E1 - params->CpuPcieClockGating[1] = 1; - params->CpuPciePowerGating[1] = 1; + params->CpuPcieClockGating[1] = CONFIG(PCIEXP_CLK_PM); + params->CpuPciePowerGating[1] = CONFIG(PCIEXP_CLK_PM); params->CpuPcieRpPeerToPeerMode[1] = 1; params->CpuPcieRpMaxPayload[1] = 2; // 512B params->CpuPcieRpAcsEnabled[1] = 1; diff --git a/src/mainboard/msi/ms7d25/romstage_fsp_params.c b/src/mainboard/msi/ms7d25/romstage_fsp_params.c index 5d535ed..b11991c 100644 --- a/src/mainboard/msi/ms7d25/romstage_fsp_params.c +++ b/src/mainboard/msi/ms7d25/romstage_fsp_params.c @@ -5,9 +5,13 @@ #include <fsp/api.h> #include <soc/romstage.h> #include <soc/meminit.h> +#include <string.h> #include "gpio.h" +#define FSP_CLK_NOTUSED 0xFF +#define FSP_CLK_FREE_RUNNING 0x80 + static const struct mb_cfg ddr4_mem_config = { .type = MEM_TYPE_DDR4, @@ -35,11 +39,29 @@ }, }; +static void disable_pcie_clock_requests(FSP_M_CONFIG *m_cfg) +{ + memset(m_cfg->PcieClkSrcUsage, FSP_CLK_NOTUSED, sizeof(m_cfg->PcieClkSrcUsage)); + memset(m_cfg->PcieClkSrcClkReq, FSP_CLK_NOTUSED, sizeof(m_cfg->PcieClkSrcClkReq)); + + m_cfg->PcieClkSrcUsage[0] = FSP_CLK_FREE_RUNNING; + m_cfg->PcieClkSrcUsage[8] = FSP_CLK_FREE_RUNNING; + m_cfg->PcieClkSrcUsage[9] = FSP_CLK_FREE_RUNNING; + m_cfg->PcieClkSrcUsage[10] = FSP_CLK_FREE_RUNNING; + m_cfg->PcieClkSrcUsage[12] = FSP_CLK_FREE_RUNNING; + m_cfg->PcieClkSrcUsage[13] = FSP_CLK_FREE_RUNNING; + m_cfg->PcieClkSrcUsage[14] = FSP_CLK_FREE_RUNNING; + m_cfg->PcieClkSrcUsage[15] = FSP_CLK_FREE_RUNNING; + m_cfg->PcieClkSrcUsage[17] = FSP_CLK_FREE_RUNNING; + + gpio_configure_pads(clkreq_disabled_table, ARRAY_SIZE(clkreq_disabled_table)); +} + void mainboard_memory_init_params(FSPM_UPD *memupd) { - memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[0] = 1; - memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[1] = 1; - memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[2] = 0; + memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[0] = CONFIG(PCIEXP_CLK_PM); + memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[1] = CONFIG(PCIEXP_CLK_PM); + memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[2] = CONFIG(PCIEXP_CLK_PM); memupd->FspmConfig.DmiMaxLinkSpeed = 4; // Gen4 speed, undocumented memupd->FspmConfig.SkipExtGfxScan = 0; @@ -49,4 +71,7 @@ memcfg_init(memupd, &ddr4_mem_config, &dimm_module_spd_info, false); gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + + if (!CONFIG(PCIEXP_CLK_PM)) + disable_pcie_clock_requests(&memupd->FspmConfig); } -- To view, visit https://review.coreboot.org/c/coreboot/+/69825 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d9d11016bed89dcfee6909d0d3e3e2e56237a2f Gerrit-Change-Number: 69825 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-MessageType: newchange

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2022