coreboot-gerrit November 2022

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[M] Change in coreboot[master]: cbmem_top_chipset: Change the return value to uintptr_t
by Felix Held (Code Review) 18 Nov '22

18 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69078 ) Change subject: cbmem_top_chipset: Change the return value to uintptr_t ...................................................................... cbmem_top_chipset: Change the return value to uintptr_t Get rid of a lot of casts. Change-Id: I93645ef5dd270905ce421e68e342aff4c331eae6 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69078 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jakub Czapiga <jacz(a)semihalf.com> --- M src/drivers/amd/agesa/romstage.c M src/drivers/intel/fsp2_0/cbmem.c M src/include/cbmem.h M src/lib/imd_cbmem.c M src/mainboard/emulation/qemu-aarch64/cbmem.c M src/mainboard/emulation/qemu-armv7/cbmem.c M src/mainboard/emulation/qemu-i440fx/memmap.c M src/mainboard/emulation/qemu-power8/cbmem.c M src/mainboard/emulation/qemu-power9/cbmem.c M src/northbridge/intel/e7505/memmap.c M src/northbridge/intel/gm45/memmap.c M src/northbridge/intel/haswell/memmap.c M src/northbridge/intel/i440bx/memmap.c M src/northbridge/intel/i945/memmap.c M src/northbridge/intel/ironlake/memmap.c M src/northbridge/intel/pineview/memmap.c M src/northbridge/intel/sandybridge/memmap.c M src/northbridge/intel/x4x/memmap.c M src/soc/amd/stoneyridge/memmap.c M src/soc/cavium/cn81xx/cbmem.c M src/soc/intel/baytrail/memmap.c M src/soc/intel/braswell/memmap.c M src/soc/intel/broadwell/memmap.c M src/soc/mediatek/common/cbmem.c M src/soc/nvidia/tegra124/cbmem.c M src/soc/nvidia/tegra210/cbmem.c M src/soc/nvidia/tegra210/ramstage.c M src/soc/qualcomm/ipq40xx/cbmem.c M src/soc/qualcomm/ipq806x/cbmem.c M src/soc/qualcomm/qcs405/cbmem.c M src/soc/qualcomm/sc7180/cbmem.c M src/soc/qualcomm/sc7280/cbmem.c M src/soc/rockchip/common/cbmem.c M src/soc/samsung/exynos5250/cbmem.c M src/soc/samsung/exynos5420/cbmem.c M src/soc/sifive/fu540/cbmem.c M src/soc/ti/am335x/cbmem.c M src/soc/ucb/riscv/cbmem.c M tests/lib/coreboot_table-test.c M tests/lib/imd_cbmem-test.c 40 files changed, 101 insertions(+), 90 deletions(-) Approvals: build bot (Jenkins): Verified Jakub Czapiga: Looks good to me, approved diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index 5c3d904..132cb3e 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -93,8 +93,8 @@ halt(); } -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { /* Top of CBMEM is at highest usable DRAM address below 4GiB. */ - return (void *)restore_top_of_low_cacheable(); + return restore_top_of_low_cacheable(); } diff --git a/src/drivers/intel/fsp2_0/cbmem.c b/src/drivers/intel/fsp2_0/cbmem.c index 0efb462..176d256 100644 --- a/src/drivers/intel/fsp2_0/cbmem.c +++ b/src/drivers/intel/fsp2_0/cbmem.c @@ -3,10 +3,10 @@ #include <cbmem.h> #include <fsp/util.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { struct range_entry tolum; fsp_find_bootloader_tolum(&tolum); - return (void *)(uintptr_t)range_entry_end(&tolum); + return range_entry_end(&tolum); } diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 40a0acb..5e2128e 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -65,7 +65,7 @@ * in the _cbmem_top_ptr symbol. Without CONFIG_RAMSTAGE_CBMEM_TOP_ARG the same * implementation as used in romstage will be used. */ -void *cbmem_top_chipset(void); +uintptr_t cbmem_top_chipset(void); /* Add a cbmem entry of a given size and id. These return NULL on failure. The * add function performs a find first and do not check against the original diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index a855cf1..91c8621 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -18,11 +18,11 @@ void *cbmem_top(void) { if (ENV_CREATES_CBMEM) { - static void *top; + static uintptr_t top; if (top) - return top; + return (void *)top; top = cbmem_top_chipset(); - return top; + return (void *)top; } if (ENV_POSTCAR || ENV_RAMSTAGE) return (void *)_cbmem_top_ptr; diff --git a/src/mainboard/emulation/qemu-aarch64/cbmem.c b/src/mainboard/emulation/qemu-aarch64/cbmem.c index 6b6ac72..389ff4e 100644 --- a/src/mainboard/emulation/qemu-aarch64/cbmem.c +++ b/src/mainboard/emulation/qemu-aarch64/cbmem.c @@ -4,7 +4,7 @@ #include <ramdetect.h> #include <symbols.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return _dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); + return (uintptr_t)_dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); } diff --git a/src/mainboard/emulation/qemu-armv7/cbmem.c b/src/mainboard/emulation/qemu-armv7/cbmem.c index 157e443..5c423a0 100644 --- a/src/mainboard/emulation/qemu-armv7/cbmem.c +++ b/src/mainboard/emulation/qemu-armv7/cbmem.c @@ -4,7 +4,7 @@ #include <symbols.h> #include <ramdetect.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return _dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); + return (uintptr_t)_dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); } diff --git a/src/mainboard/emulation/qemu-i440fx/memmap.c b/src/mainboard/emulation/qemu-i440fx/memmap.c index 75ab352..efe83c3 100644 --- a/src/mainboard/emulation/qemu-i440fx/memmap.c +++ b/src/mainboard/emulation/qemu-i440fx/memmap.c @@ -41,7 +41,7 @@ return tomk; } -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { uintptr_t top = 0; @@ -56,7 +56,7 @@ smm_region(&top, &smm_size); } - return (void *)top; + return top; } /* Nothing to do, MTRRs are no-op on QEMU. */ diff --git a/src/mainboard/emulation/qemu-power8/cbmem.c b/src/mainboard/emulation/qemu-power8/cbmem.c index 15c20f8..1c0c62b 100644 --- a/src/mainboard/emulation/qemu-power8/cbmem.c +++ b/src/mainboard/emulation/qemu-power8/cbmem.c @@ -2,10 +2,9 @@ #include <cbmem.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { /* Top of cbmem is at lowest usable DRAM address below 4GiB. */ /* For now, last 1M of 4G */ - void *ptr = (void *) ((1ULL << 32) - 1048576); - return ptr; + return (1ULL << 32) - 1048576; } diff --git a/src/mainboard/emulation/qemu-power9/cbmem.c b/src/mainboard/emulation/qemu-power9/cbmem.c index 1b7b690..82ae74e 100644 --- a/src/mainboard/emulation/qemu-power9/cbmem.c +++ b/src/mainboard/emulation/qemu-power9/cbmem.c @@ -3,7 +3,7 @@ #include <cbmem.h> #include <ramdetect.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)(probe_ramsize(0, CONFIG_DRAM_SIZE_MB) * MiB); + return probe_ramsize(0, CONFIG_DRAM_SIZE_MB) * MiB; } diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c index b1ac3d1..0d90175 100644 --- a/src/northbridge/intel/e7505/memmap.c +++ b/src/northbridge/intel/e7505/memmap.c @@ -3,14 +3,16 @@ // Use simple device model for this file even in ramstage #define __SIMPLE_DEVICE__ -#include <device/pci_ops.h> #include <arch/romstage.h> #include <cbmem.h> #include <cpu/x86/mtrr.h> +#include <device/pci_ops.h> #include <program_loading.h> +#include <stdint.h> + #include "e7505.h" -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { const pci_devfn_t mch = PCI_DEV(0, 0, 0); uintptr_t tolm; @@ -19,7 +21,7 @@ tolm = pci_read_config16(mch, TOLM) >> 11; tolm <<= 27; - return (void *)tolm; + return tolm; } void northbridge_write_smram(u8 smram); diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c index 28edb38..35ec41d 100644 --- a/src/northbridge/intel/gm45/memmap.c +++ b/src/northbridge/intel/gm45/memmap.c @@ -104,10 +104,9 @@ * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); - return (void *) top_of_ram; + return ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); } void smm_region(uintptr_t *start, size_t *size) diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c index c19cfec..6b75caa 100644 --- a/src/northbridge/intel/haswell/memmap.c +++ b/src/northbridge/intel/haswell/memmap.c @@ -54,9 +54,9 @@ return tolum; } -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)top_of_low_usable_memory(); + return top_of_low_usable_memory(); } void smm_region(uintptr_t *start, size_t *size) diff --git a/src/northbridge/intel/i440bx/memmap.c b/src/northbridge/intel/i440bx/memmap.c index b6d9526..5cee1b4 100644 --- a/src/northbridge/intel/i440bx/memmap.c +++ b/src/northbridge/intel/i440bx/memmap.c @@ -8,7 +8,7 @@ #include <program_loading.h> #include "i440bx.h" -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { /* Base of TSEG is top of usable DRAM */ /* @@ -39,7 +39,7 @@ * * Source: 440BX datasheet, pages 3-28 thru 3-29. */ - unsigned long tom = pci_read_config8(NB, DRB7) * 8 * MiB; + uintptr_t tom = pci_read_config8(NB, DRB7) * 8 * MiB; int gsmrame = pci_read_config8(NB, SMRAM) & 0x8; /* T_SZ and TSEG_EN */ @@ -48,7 +48,7 @@ int tseg_size = 128 * KiB * (1 << (tseg >> 1)); tom -= tseg_size; } - return (void *)tom; + return tom; } void fill_postcar_frame(struct postcar_frame *pcf) diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c index 1fa0358..e0352fb 100644 --- a/src/northbridge/intel/i945/memmap.c +++ b/src/northbridge/intel/i945/memmap.c @@ -57,10 +57,9 @@ * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); - return (void *) top_of_ram; + return ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); } /* Decodes used Graphics Mode Select (GMS) to kilobytes. */ diff --git a/src/northbridge/intel/ironlake/memmap.c b/src/northbridge/intel/ironlake/memmap.c index 78fbae8..bdb76c1 100644 --- a/src/northbridge/intel/ironlake/memmap.c +++ b/src/northbridge/intel/ironlake/memmap.c @@ -22,9 +22,9 @@ return CONFIG_SMM_TSEG_SIZE; } -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)northbridge_get_tseg_base(); + return northbridge_get_tseg_base(); } void smm_region(uintptr_t *start, size_t *size) diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c index c02cf35..55d7046 100644 --- a/src/northbridge/intel/pineview/memmap.c +++ b/src/northbridge/intel/pineview/memmap.c @@ -73,9 +73,9 @@ * Depending of UMA and TSEG configuration, TSEG might start at any 1 MiB alignment. * As this may cause very greedy MTRR setup, push CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *) ALIGN_DOWN(northbridge_get_tseg_base(), 4 * MiB); + return ALIGN_DOWN(northbridge_get_tseg_base(), 4 * MiB); } diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c index f667544..ac95ab5 100644 --- a/src/northbridge/intel/sandybridge/memmap.c +++ b/src/northbridge/intel/sandybridge/memmap.c @@ -54,9 +54,9 @@ return tolum; } -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)top_of_low_usable_memory(); + return top_of_low_usable_memory(); } void smm_region(uintptr_t *start, size_t *size) diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c index dced902..0b085cf 100644 --- a/src/northbridge/intel/x4x/memmap.c +++ b/src/northbridge/intel/x4x/memmap.c @@ -71,10 +71,9 @@ * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); - return (void *) top_of_ram; + return ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); } void smm_region(uintptr_t *start, size_t *size) diff --git a/src/soc/amd/stoneyridge/memmap.c b/src/soc/amd/stoneyridge/memmap.c index f015740..7a225e1 100644 --- a/src/soc/amd/stoneyridge/memmap.c +++ b/src/soc/amd/stoneyridge/memmap.c @@ -12,7 +12,7 @@ #include <soc/iomap.h> #include <amdblocks/biosram.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { msr_t tom = rdmsr(TOP_MEM); @@ -20,8 +20,7 @@ return 0; /* 8MB alignment to keep MTRR usage low */ - return (void *)ALIGN_DOWN(restore_top_of_low_cacheable() - - CONFIG_SMM_TSEG_SIZE, 8 * MiB); + return ALIGN_DOWN(restore_top_of_low_cacheable() - CONFIG_SMM_TSEG_SIZE, 8 * MiB); } static uintptr_t smm_region_start(void) diff --git a/src/soc/cavium/cn81xx/cbmem.c b/src/soc/cavium/cn81xx/cbmem.c index d50fe16..0b0c717 100644 --- a/src/soc/cavium/cn81xx/cbmem.c +++ b/src/soc/cavium/cn81xx/cbmem.c @@ -5,8 +5,8 @@ #include <soc/sdram.h> #include <symbols.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { /* Make sure not to overlap with reserved ATF scratchpad */ - return (void *)((uintptr_t)_dram + (sdram_size_mb() - 1) * MiB); + return (uintptr_t)_dram + (sdram_size_mb() - 1) * MiB; } diff --git a/src/soc/intel/baytrail/memmap.c b/src/soc/intel/baytrail/memmap.c index aa8e890..43b96c1 100644 --- a/src/soc/intel/baytrail/memmap.c +++ b/src/soc/intel/baytrail/memmap.c @@ -16,9 +16,9 @@ return CONFIG_SMM_TSEG_SIZE; } -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *) smm_region_start(); + return smm_region_start(); } void smm_region(uintptr_t *start, size_t *size) diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c index 4a791ef..3c3ad74 100644 --- a/src/soc/intel/braswell/memmap.c +++ b/src/soc/intel/braswell/memmap.c @@ -19,7 +19,7 @@ *size = smm_region_size(); } -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { uintptr_t smm_base; size_t smm_size; @@ -53,5 +53,5 @@ */ smm_region(&smm_base, &smm_size); - return (void *)smm_base; + return smm_base; } diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index b467dc0..98c8016 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -29,9 +29,9 @@ return tom; } -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *) dpr_region_start(); + return dpr_region_start(); } void smm_region(uintptr_t *start, size_t *size) diff --git a/src/soc/mediatek/common/cbmem.c b/src/soc/mediatek/common/cbmem.c index f9d11e9..0ca9e6b 100644 --- a/src/soc/mediatek/common/cbmem.c +++ b/src/soc/mediatek/common/cbmem.c @@ -7,7 +7,7 @@ #define MAX_DRAM_ADDRESS ((uintptr_t)4 * GiB) -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)MIN((uintptr_t)_dram + sdram_size(), MAX_DRAM_ADDRESS); + return MIN((uintptr_t)_dram + sdram_size(), MAX_DRAM_ADDRESS); } diff --git a/src/soc/nvidia/tegra124/cbmem.c b/src/soc/nvidia/tegra124/cbmem.c index 3f59f06..287ef629 100644 --- a/src/soc/nvidia/tegra124/cbmem.c +++ b/src/soc/nvidia/tegra124/cbmem.c @@ -1,10 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <cbmem.h> +#include <commonlib/bsd/helpers.h> #include <soc/display.h> #include <soc/sdram.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)((sdram_max_addressable_mb() - FB_SIZE_MB) << 20UL); + return (sdram_max_addressable_mb() - FB_SIZE_MB) * MiB; } diff --git a/src/soc/nvidia/tegra210/cbmem.c b/src/soc/nvidia/tegra210/cbmem.c index d9b2226..a56f150 100644 --- a/src/soc/nvidia/tegra210/cbmem.c +++ b/src/soc/nvidia/tegra210/cbmem.c @@ -3,7 +3,7 @@ #include <cbmem.h> #include <soc/addressmap.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { static uintptr_t addr; @@ -19,5 +19,5 @@ addr = end_mib << 20; } - return (void *)addr; + return addr; } diff --git a/src/soc/nvidia/tegra210/ramstage.c b/src/soc/nvidia/tegra210/ramstage.c index 50249b7..45b221b 100644 --- a/src/soc/nvidia/tegra210/ramstage.c +++ b/src/soc/nvidia/tegra210/ramstage.c @@ -59,7 +59,7 @@ /* Ramstage is run on a different core, so passing cbmem_top via calling arguments is not an option, but it is not a problem to call cbmem_top_chipset() again here to populate _cbmem_top_ptr. */ - _cbmem_top_ptr = (uintptr_t)cbmem_top_chipset(); + _cbmem_top_ptr = cbmem_top_chipset(); /* Jump to boot state machine in common code. */ main(); diff --git a/src/soc/qualcomm/ipq40xx/cbmem.c b/src/soc/qualcomm/ipq40xx/cbmem.c index 0ee9f9a..c5d1a81 100644 --- a/src/soc/qualcomm/ipq40xx/cbmem.c +++ b/src/soc/qualcomm/ipq40xx/cbmem.c @@ -10,7 +10,7 @@ cbmem_backing_store_ready = 1; } -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { /* * In romstage, make sure that cbmem backing store is ready before @@ -19,7 +19,7 @@ * for loading ipq blobs before DRAM is initialized). */ if (cbmem_backing_store_ready == 0) - return NULL; + return 0; - return _memlayout_cbmem_top; + return (uintptr_t)_memlayout_cbmem_top; } diff --git a/src/soc/qualcomm/ipq806x/cbmem.c b/src/soc/qualcomm/ipq806x/cbmem.c index a695cf8..8196416 100644 --- a/src/soc/qualcomm/ipq806x/cbmem.c +++ b/src/soc/qualcomm/ipq806x/cbmem.c @@ -10,7 +10,7 @@ cbmem_backing_store_ready = 1; } -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { /* * In romstage, make sure that cbmem backing store is ready before @@ -20,7 +20,7 @@ * initialized). */ if (cbmem_backing_store_ready == 0) - return NULL; + return 0; - return _memlayout_cbmem_top; + return (uintptr_t)_memlayout_cbmem_top; } diff --git a/src/soc/qualcomm/qcs405/cbmem.c b/src/soc/qualcomm/qcs405/cbmem.c index 97ba38b..e8bab77 100644 --- a/src/soc/qualcomm/qcs405/cbmem.c +++ b/src/soc/qualcomm/qcs405/cbmem.c @@ -2,7 +2,7 @@ #include <cbmem.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)((uintptr_t)3 * GiB); + return (uintptr_t)3 * GiB; } diff --git a/src/soc/qualcomm/sc7180/cbmem.c b/src/soc/qualcomm/sc7180/cbmem.c index 4b9eb37..5fff371 100644 --- a/src/soc/qualcomm/sc7180/cbmem.c +++ b/src/soc/qualcomm/sc7180/cbmem.c @@ -2,7 +2,7 @@ #include <cbmem.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)((uintptr_t)4 * GiB); + return (uintptr_t)4 * GiB; } diff --git a/src/soc/qualcomm/sc7280/cbmem.c b/src/soc/qualcomm/sc7280/cbmem.c index 4b9eb37..5fff371 100644 --- a/src/soc/qualcomm/sc7280/cbmem.c +++ b/src/soc/qualcomm/sc7280/cbmem.c @@ -2,7 +2,7 @@ #include <cbmem.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)((uintptr_t)4 * GiB); + return (uintptr_t)4 * GiB; } diff --git a/src/soc/rockchip/common/cbmem.c b/src/soc/rockchip/common/cbmem.c index 5650114..172491e 100644 --- a/src/soc/rockchip/common/cbmem.c +++ b/src/soc/rockchip/common/cbmem.c @@ -6,8 +6,7 @@ #include <soc/sdram.h> #include <symbols.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)MIN((uintptr_t)_dram + sdram_size_mb() * MiB, - MAX_DRAM_ADDRESS); + return MIN((uintptr_t)_dram + sdram_size_mb() * MiB, MAX_DRAM_ADDRESS); } diff --git a/src/soc/samsung/exynos5250/cbmem.c b/src/soc/samsung/exynos5250/cbmem.c index 167bd80..d74b414 100644 --- a/src/soc/samsung/exynos5250/cbmem.c +++ b/src/soc/samsung/exynos5250/cbmem.c @@ -3,7 +3,7 @@ #include <cbmem.h> #include <soc/cpu.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)(get_fb_base_kb() * KiB); + return get_fb_base_kb() * KiB; } diff --git a/src/soc/samsung/exynos5420/cbmem.c b/src/soc/samsung/exynos5420/cbmem.c index 167bd80..d74b414 100644 --- a/src/soc/samsung/exynos5420/cbmem.c +++ b/src/soc/samsung/exynos5420/cbmem.c @@ -3,7 +3,7 @@ #include <cbmem.h> #include <soc/cpu.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)(get_fb_base_kb() * KiB); + return get_fb_base_kb() * KiB; } diff --git a/src/soc/sifive/fu540/cbmem.c b/src/soc/sifive/fu540/cbmem.c index af04130..53e5fcf 100644 --- a/src/soc/sifive/fu540/cbmem.c +++ b/src/soc/sifive/fu540/cbmem.c @@ -6,8 +6,7 @@ #include <soc/sdram.h> #include <symbols.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)MIN((uintptr_t)_dram + sdram_size_mb() * MiB, - FU540_MAXDRAM); + return MIN((uintptr_t)_dram + sdram_size_mb() * MiB, FU540_MAXDRAM); } diff --git a/src/soc/ti/am335x/cbmem.c b/src/soc/ti/am335x/cbmem.c index 170695e..14c927e 100644 --- a/src/soc/ti/am335x/cbmem.c +++ b/src/soc/ti/am335x/cbmem.c @@ -4,7 +4,7 @@ #include <commonlib/bsd/helpers.h> #include <symbols.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return _dram + CONFIG_DRAM_SIZE_MB * MiB; + return (uintptr_t)_dram + CONFIG_DRAM_SIZE_MB * MiB; } diff --git a/src/soc/ucb/riscv/cbmem.c b/src/soc/ucb/riscv/cbmem.c index 157e443..5c423a0 100644 --- a/src/soc/ucb/riscv/cbmem.c +++ b/src/soc/ucb/riscv/cbmem.c @@ -4,7 +4,7 @@ #include <symbols.h> #include <ramdetect.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return _dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); + return (uintptr_t)_dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); } diff --git a/tests/lib/coreboot_table-test.c b/tests/lib/coreboot_table-test.c index 16ab97f..aa10f65 100644 --- a/tests/lib/coreboot_table-test.c +++ b/tests/lib/coreboot_table-test.c @@ -243,9 +243,9 @@ } extern uintptr_t _cbmem_top_ptr; -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)_cbmem_top_ptr; + return _cbmem_top_ptr; } #define CBMEM_SIZE (64 * KiB) diff --git a/tests/lib/imd_cbmem-test.c b/tests/lib/imd_cbmem-test.c index fe25285..e345c84 100644 --- a/tests/lib/imd_cbmem-test.c +++ b/tests/lib/imd_cbmem-test.c @@ -36,9 +36,9 @@ function_called(); } -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)_cbmem_top_ptr; + return _cbmem_top_ptr; } static void *get_cbmem_ptr(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/69078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93645ef5dd270905ce421e68e342aff4c331eae6 Gerrit-Change-Number: 69078 Gerrit-PatchSet: 13 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/amd/acpi: Expand 5 DPTC thermal profiles acpigen support for Alib
by Felix Held (Code Review) 18 Nov '22

18 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68470 ) Change subject: soc/amd/acpi: Expand 5 DPTC thermal profiles acpigen support for Alib ...................................................................... soc/amd/acpi: Expand 5 DPTC thermal profiles acpigen support for Alib Update acpigen_write_alib_dptc() to support extra 5 thermal profiles. User can use these profiles for dynamic thermal table switching support. BUG=b:232946420 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Change-Id: I9e6d5c0fc6f492340c935899920d9ee7c9396256 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68470 Reviewed-by: Tim Van Patten <timvp(a)google.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> --- M src/soc/amd/common/block/acpi/alib.c M src/soc/amd/common/block/include/amdblocks/alib.h 2 files changed, 177 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Dtrain Hsu: Looks good to me, approved Tim Van Patten: Looks good to me, approved diff --git a/src/soc/amd/common/block/acpi/alib.c b/src/soc/amd/common/block/acpi/alib.c index 3c01d85..da54248 100644 --- a/src/soc/amd/common/block/acpi/alib.c +++ b/src/soc/amd/common/block/acpi/alib.c @@ -102,3 +102,148 @@ acpigen_write_scope_end(); } + +void acpigen_write_alib_dptc_thermal_B(uint8_t *thermal_param_B, size_t thermal_param_B_len) +{ + /* Scope (\_SB) */ + acpigen_write_scope("\\_SB"); + + /* Table B for dynamic DPTC*/ + /* Scope (\_SB) + * { + * Method (DTTB, 0, Serialized) + * { + * Debug = "DPTC: TABLE B" + * Name (THTB, Buffer (0x25) + * { + * ... + * }) + * \_SB.ALIB + * 0x0C + * THTB + * } + * } + */ + acpigen_write_method_serialized("DTTB", 0); + acpigen_write_debug_string("DPTC: TABLE B"); + acpigen_dptc_call_alib("THTB", thermal_param_B, thermal_param_B_len); + acpigen_write_method_end(); + + acpigen_write_scope_end(); +} + +void acpigen_write_alib_dptc_thermal_C(uint8_t *thermal_param_C, size_t thermal_param_C_len) +{ + /* Scope (\_SB) */ + acpigen_write_scope("\\_SB"); + + /* Table C for dynamic DPTC*/ + /* Scope (\_SB) + * { + * Method (DTTC, 0, Serialized) + * { + * Debug = "DPTC: TABLE C" + * Name (THTC, Buffer (0x25) + * { + * ... + * }) + * \_SB.ALIB + * 0x0C + * THTC + * } + * } + */ + acpigen_write_method_serialized("DTTC", 0); + acpigen_write_debug_string("DPTC: TABLE C"); + acpigen_dptc_call_alib("THTC", thermal_param_C, thermal_param_C_len); + acpigen_write_method_end(); + + acpigen_write_scope_end(); +} + +void acpigen_write_alib_dptc_thermal_D(uint8_t *thermal_param_D, size_t thermal_param_D_len) +{ + /* Scope (\_SB) */ + acpigen_write_scope("\\_SB"); + + /* Table D for dynamic DPTC*/ + /* Scope (\_SB) + * { + * Method (DTTD, 0, Serialized) + * { + * Debug = "DPTC: Using normal SOC DPTC Settings." + * Name (THTD, Buffer (0x25) + * { + * ... + * }) + * \_SB.ALIB + * 0x0C + * THTD + * } + * } + */ + acpigen_write_method_serialized("DTTD", 0); + acpigen_write_debug_string("DPTC: TABLE D"); + acpigen_dptc_call_alib("THTD", thermal_param_D, thermal_param_D_len); + acpigen_write_method_end(); + + acpigen_write_scope_end(); +} + +void acpigen_write_alib_dptc_thermal_E(uint8_t *thermal_param_E, size_t thermal_param_E_len) +{ + /* Scope (\_SB) */ + acpigen_write_scope("\\_SB"); + + /* Table E for dynamic DPTC*/ + /* Scope (\_SB) + * { + * Method (DTTE, 0, Serialized) + * { + * Debug = "DPTC: TABLE E" + * Name (THTE, Buffer (0x25) + * { + * ... + * }) + * \_SB.ALIB + * 0x0C + * THTE + * } + * } + */ + acpigen_write_method_serialized("DTTE", 0); + acpigen_write_debug_string("DPTC: TABLE E"); + acpigen_dptc_call_alib("THTE", thermal_param_E, thermal_param_E_len); + acpigen_write_method_end(); + + acpigen_write_scope_end(); +} + +void acpigen_write_alib_dptc_thermal_F(uint8_t *thermal_param_F, size_t thermal_param_F_len) +{ + /* Scope (\_SB) */ + acpigen_write_scope("\\_SB"); + + /* Table F for dynamic DPTC*/ + /* Scope (\_SB) + * { + * Method (DTTF, 0, Serialized) + * { + * Debug = "DPTC: TABLE F" + * Name (THTF, Buffer (0x25) + * { + * ... + * }) + * \_SB.ALIB + * 0x0C + * THTF + * } + * } + */ + acpigen_write_method_serialized("DTTF", 0); + acpigen_write_debug_string("DPTC: TABLE F"); + acpigen_dptc_call_alib("THTF", thermal_param_F, thermal_param_F_len); + acpigen_write_method_end(); + + acpigen_write_scope_end(); +} diff --git a/src/soc/amd/common/block/include/amdblocks/alib.h b/src/soc/amd/common/block/include/amdblocks/alib.h index 3de4018..82d6935 100644 --- a/src/soc/amd/common/block/include/amdblocks/alib.h +++ b/src/soc/amd/common/block/include/amdblocks/alib.h @@ -20,6 +20,12 @@ ALIB_DPTC_VRM_MAXIMUM_CURRENT_LIMIT = 0xc, /* Picasso: SetVrmSocCurrentLimit (0xe) is not implemented in alib. */ ALIB_DPTC_VRM_SOC_CURRENT_LIMIT_ID = 0xe, + + ALIB_DPTC_STT_SKIN_TEMPERATURE_LIMIT_APU_ID = 0x22, + ALIB_DPTC_STT_M1_ID = 0x26, + ALIB_DPTC_STT_M2_ID = 0x27, + ALIB_DPTC_STT_C_APU_ID = 0x2C, + ALIB_DPTC_STT_MIN_LIMIT_ID = 0x2E, }; struct alib_dptc_param { @@ -30,7 +36,11 @@ void acpigen_write_alib_dptc_default(uint8_t *default_param, size_t default_param_len); void acpigen_write_alib_dptc_no_battery(uint8_t *no_battery_param, size_t no_battery_param_len); void acpigen_write_alib_dptc_tablet(uint8_t *tablet_param, size_t tablet_param_len); - +void acpigen_write_alib_dptc_thermal_B(uint8_t *thermal_param_B, size_t thermal_param_B_len); +void acpigen_write_alib_dptc_thermal_C(uint8_t *thermal_param_C, size_t thermal_param_C_len); +void acpigen_write_alib_dptc_thermal_D(uint8_t *thermal_param_D, size_t thermal_param_D_len); +void acpigen_write_alib_dptc_thermal_E(uint8_t *thermal_param_E, size_t thermal_param_E_len); +void acpigen_write_alib_dptc_thermal_F(uint8_t *thermal_param_F, size_t thermal_param_F_len); #endif /* !__ACPI__ */ #endif /* AMD_COMMON_ALIB_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/68470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e6d5c0fc6f492340c935899920d9ee7c9396256 Gerrit-Change-Number: 68470 Gerrit-PatchSet: 23 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nelson Ye <nelson_ye(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/amd/acpi: Expand 5 DPTC thermal profiles acpigen support for Alib
by Felix Held (Code Review) 18 Nov '22

18 Nov '22

Attention is currently required from: Jason Glenesk, EricKY Cheng, Matt DeVillier, Nelson Ye, Eric Peers, Fred Reitberger, Karthikeyan Ramasubramanian. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68470 ) Change subject: soc/amd/acpi: Expand 5 DPTC thermal profiles acpigen support for Alib ...................................................................... Patch Set 22: (1 comment) Patchset: PS22: it's probably worth looking into combining all those very similar functions into one that takes another parameter to avoid code duplication. for now i'm ok with this to keep things moving -- To view, visit https://review.coreboot.org/c/coreboot/+/68470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e6d5c0fc6f492340c935899920d9ee7c9396256 Gerrit-Change-Number: 68470 Gerrit-PatchSet: 22 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nelson Ye <nelson_ye(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Nelson Ye <nelson_ye(a)compal.corp-partner.google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Comment-Date: Fri, 18 Nov 2022 15:54:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/mediatek/mt8188: Enable and initialize EINT
by Felix Held (Code Review) 18 Nov '22

18 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69688 ) Change subject: soc/mediatek/mt8188: Enable and initialize EINT ...................................................................... soc/mediatek/mt8188: Enable and initialize EINT Issue: Device can't wake up using power key. Root cause and solution: EINT event mask register is used to mask EINT wakeup sources. All wakeup sources are masked by default. So we add a driver here to unmask all wakeup sources. BUG=none TEST=wake the device up by power key on MT8188 EVB. Signed-off-by: Johnson Wang <johnson.wang(a)mediatek.com> Change-Id: I94b20909b0b8d77f75c41bc745f892baded7a54b Reviewed-on: https://review.coreboot.org/c/coreboot/+/69688 Reviewed-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8188/Makefile.inc M src/soc/mediatek/mt8188/bootblock.c 2 files changed, 29 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, but someone else must approve Rex-BC Chen: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/mt8188/Makefile.inc b/src/soc/mediatek/mt8188/Makefile.inc index 13fea31..59ec553 100644 --- a/src/soc/mediatek/mt8188/Makefile.inc +++ b/src/soc/mediatek/mt8188/Makefile.inc @@ -10,6 +10,7 @@ all-y += ../common/uart.c bootblock-y += bootblock.c +bootblock-y += ../common/eint_event.c bootblock-y += ../common/mmu_operations.c bootblock-y += ../common/tracker.c ../common/tracker_v2.c bootblock-y += ../common/wdt.c ../common/wdt_req.c wdt.c diff --git a/src/soc/mediatek/mt8188/bootblock.c b/src/soc/mediatek/mt8188/bootblock.c index 75fab9a..32ef4af 100644 --- a/src/soc/mediatek/mt8188/bootblock.c +++ b/src/soc/mediatek/mt8188/bootblock.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ #include <bootblock_common.h> +#include <soc/eint_event.h> #include <soc/mmu_operations.h> #include <soc/pll.h> #include <soc/tracker_common.h> @@ -12,4 +13,5 @@ bustracker_init(); mtk_wdt_init(); mt_pll_init(); + unmask_eint_event_mask(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/69688 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94b20909b0b8d77f75c41bc745f892baded7a54b Gerrit-Change-Number: 69688 Gerrit-PatchSet: 4 Gerrit-Owner: johnson wang <johnson.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/qualcomm/sc7280: Skip PCIe ops for eMMC SKUs
by Felix Held (Code Review) 18 Nov '22

18 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69690 ) Change subject: soc/qualcomm/sc7280: Skip PCIe ops for eMMC SKUs ...................................................................... soc/qualcomm/sc7280: Skip PCIe ops for eMMC SKUs On Herobrine, we will determine if we have an NVMe device based on SKU id. Basically, if bit 0 is 2 (or Z), then we know that we have an NVMe device and thus will need to go through PCIe initialization. Otherwise, we know that we are booting an eMMC device. BUG=b:254281839 BRANCH=None TEST=build firmware image and boot and make sure we can boot up Tested on villager, which does not have NVMe and made sure that it boots still. Check cbmem dump to make sure that device configuration entry is still low since it's not initializing PCIe devices: 40:device configuration 730,203 (1,295) Change-Id: I1fa0ad392ba6320fdbab54b3b5dc83ac28cd20ba Signed-off-by: Shelley Chen <shchen(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69690 Reviewed-by: Julius Werner <jwerner(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/qualcomm/common/pcie_common.c M src/soc/qualcomm/sc7280/soc.c 2 files changed, 36 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/soc/qualcomm/common/pcie_common.c b/src/soc/qualcomm/common/pcie_common.c index 2f53e28..940b206 100644 --- a/src/soc/qualcomm/common/pcie_common.c +++ b/src/soc/qualcomm/common/pcie_common.c @@ -416,6 +416,9 @@ */ enum cb_err fill_lb_pcie(struct lb_pcie *pcie) { + if (!mainboard_needs_pcie_init()) + return CB_ERR_NOT_IMPLEMENTED; + pcie_cntlr_cfg_t *pcierc = qcom_pcie_cfg.cntlr_cfg; pcie->ctrl_base = (uintptr_t)pcierc->dbi_base; return CB_SUCCESS; diff --git a/src/soc/qualcomm/sc7280/soc.c b/src/soc/qualcomm/sc7280/soc.c index dc5a9b0..268f080 100644 --- a/src/soc/qualcomm/sc7280/soc.c +++ b/src/soc/qualcomm/sc7280/soc.c @@ -43,9 +43,12 @@ static void enable_soc_dev(struct device *dev) { /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) - dev->ops = &pci_domain_ops; - else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) + if (dev->path.type == DEVICE_PATH_DOMAIN) { + if (mainboard_needs_pcie_init()) + dev->ops = &pci_domain_ops; + else + printk(BIOS_DEBUG, "Skip setting PCIe ops\n"); + } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) dev->ops = &soc_ops; } -- To view, visit https://review.coreboot.org/c/coreboot/+/69690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fa0ad392ba6320fdbab54b3b5dc83ac28cd20ba Gerrit-Change-Number: 69690 Gerrit-PatchSet: 5 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-CC: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-CC: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/herobrine: Implement mainboard_needs_pcie_init
by Felix Held (Code Review) 18 Nov '22

18 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69689 ) Change subject: mb/google/herobrine: Implement mainboard_needs_pcie_init ...................................................................... mb/google/herobrine: Implement mainboard_needs_pcie_init Implement mainboard_needs_pcie_init() for herobrine in order to determine if we need to initialize the pcie links. When the SKU id is unknown or unprovisioned (for example at the beginning of the factory flow), we should still initialize PCIe. Otherwise the devices with NVMe will fail to boot. BUG=b:254281839 BRANCH=None TEST=emerge-herobrine coreboot Change-Id: I8972424f0c5d082165c185ab52a638e8b134064c Signed-off-by: Shelley Chen <shchen(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69689 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/mainboard/google/herobrine/mainboard.c M src/soc/qualcomm/common/include/soc/pcie.h 2 files changed, 50 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/mainboard/google/herobrine/mainboard.c b/src/mainboard/google/herobrine/mainboard.c index ece6d68..2648392 100644 --- a/src/mainboard/google/herobrine/mainboard.c +++ b/src/mainboard/google/herobrine/mainboard.c @@ -8,10 +8,12 @@ #include <delay.h> #include <device/device.h> #include <device/mmio.h> +#include <ec/google/chromeec/ec.h> #include <edid.h> #include <soc/clock.h> #include <soc/display/mdssreg.h> #include <soc/display/edp_ctrl.h> +#include <soc/pcie.h> #include <soc/qupv3_config_common.h> #include <soc/qup_se_handlers_common.h> #include <soc/qcom_qup_se.h> @@ -82,6 +84,30 @@ } } +/* + * Determine if board need to perform PCIe initialization. On Herobrine, + * resistor strapping will be such that bit 0 will be assigned 2 (high Z) if it + * is an NVMe enabled platform. + */ +bool mainboard_needs_pcie_init(void) +{ + uint32_t sku = sku_id(); + + if (sku == CROS_SKU_UNKNOWN) { + printk(BIOS_WARNING, "Unknown SKU (%#x); assuming PCIe", sku); + return true; + } else if (sku == CROS_SKU_UNPROVISIONED) { + printk(BIOS_WARNING, "Unprovisioned SKU (%#x); assuming PCIe", sku); + return true; + } + + if ((sku % 3) == 2) + return true; + + /* Otherwise, eMMC */ + return false; +} + static void mainboard_init(struct device *dev) { /* Configure clock for eMMC */ diff --git a/src/soc/qualcomm/common/include/soc/pcie.h b/src/soc/qualcomm/common/include/soc/pcie.h index 09ea671..b2f9e45 100644 --- a/src/soc/qualcomm/common/include/soc/pcie.h +++ b/src/soc/qualcomm/common/include/soc/pcie.h @@ -221,5 +221,6 @@ void gcom_pcie_get_config(struct qcom_pcie_cntlr_t *host_cfg); void qcom_pci_domain_read_resources(struct device *dev); void qcom_setup_pcie_host(struct device *dev); +bool mainboard_needs_pcie_init(void); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/69689 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8972424f0c5d082165c185ab52a638e8b134064c Gerrit-Change-Number: 69689 Gerrit-PatchSet: 4 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-CC: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-CC: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/meteorlake: Add Meteor Lake MCH device ID
by Felix Held (Code Review) 18 Nov '22

18 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69560 ) Change subject: soc/intel/meteorlake: Add Meteor Lake MCH device ID ...................................................................... soc/intel/meteorlake: Add Meteor Lake MCH device ID Add Meteor Lake MCH device ID 0x7d15. TEST=Build and verify boot on MTL RVP With patch, coreboot log: `[DEBUG] MCH: device id 7d15 (rev 00) is Meteorlake P` Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: If46b01910239173cd74bf6eebc69a81291b6e15a Reviewed-on: https://review.coreboot.org/c/coreboot/+/69560 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu(a)intel.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/meteorlake/bootblock/report_platform.c M src/soc/intel/meteorlake/chip.h M src/soc/intel/meteorlake/systemagent.c 5 files changed, 29 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Jamie Ryu: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 5e270ce..f1f77e0 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4131,6 +4131,7 @@ #define PCI_DID_INTEL_MTL_P_ID_1 0x7D01 #define PCI_DID_INTEL_MTL_P_ID_2 0x7D02 #define PCI_DID_INTEL_MTL_P_ID_3 0x7d14 +#define PCI_DID_INTEL_MTL_P_ID_4 0x7d15 #define PCI_DID_INTEL_RPL_P_ID_1 0xa706 #define PCI_DID_INTEL_RPL_P_ID_2 0xa707 #define PCI_DID_INTEL_RPL_P_ID_3 0xa708 diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index e74c118..90b3335 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -340,6 +340,7 @@ PCI_DID_INTEL_MTL_P_ID_1, PCI_DID_INTEL_MTL_P_ID_2, PCI_DID_INTEL_MTL_P_ID_3, + PCI_DID_INTEL_MTL_P_ID_4, PCI_DID_INTEL_GLK_NB, PCI_DID_INTEL_APL_NB, PCI_DID_INTEL_CNL_ID_U, diff --git a/src/soc/intel/meteorlake/bootblock/report_platform.c b/src/soc/intel/meteorlake/bootblock/report_platform.c index 156102d..982a0c5 100644 --- a/src/soc/intel/meteorlake/bootblock/report_platform.c +++ b/src/soc/intel/meteorlake/bootblock/report_platform.c @@ -29,6 +29,7 @@ { PCI_DID_INTEL_MTL_P_ID_1, "MeteorLake P" }, { PCI_DID_INTEL_MTL_P_ID_2, "MeteorLake P" }, { PCI_DID_INTEL_MTL_P_ID_3, "MeteorLake P" }, + { PCI_DID_INTEL_MTL_P_ID_4, "MeteorLake P" }, }; static struct { diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h index b6e3ab2..19b34a2 100644 --- a/src/soc/intel/meteorlake/chip.h +++ b/src/soc/intel/meteorlake/chip.h @@ -22,6 +22,7 @@ MTL_P_POWER_LIMITS_1, MTL_P_POWER_LIMITS_2, MTL_P_POWER_LIMITS_3, + MTL_P_POWER_LIMITS_4, MTL_POWER_LIMITS_COUNT }; diff --git a/src/soc/intel/meteorlake/systemagent.c b/src/soc/intel/meteorlake/systemagent.c index c6c1ada..c91d3bd 100644 --- a/src/soc/intel/meteorlake/systemagent.c +++ b/src/soc/intel/meteorlake/systemagent.c @@ -77,6 +77,9 @@ case PCI_DID_INTEL_MTL_P_ID_3: soc_config = &config->power_limits_config[MTL_P_POWER_LIMITS_3]; break; + case PCI_DID_INTEL_MTL_P_ID_4: + soc_config = &config->power_limits_config[MTL_P_POWER_LIMITS_4]; + break; default: printk(BIOS_ERR, "unknown SA ID: 0x%4x, skipping power limits configuration\n", sa_pci_id); -- To view, visit https://review.coreboot.org/c/coreboot/+/69560 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If46b01910239173cd74bf6eebc69a81291b6e15a Gerrit-Change-Number: 69560 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/msi/ms7d25: Add console die notification
by Michał Żygowski (Code Review) 18 Nov '22

18 Nov '22

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69821 ) Change subject: mb/msi/ms7d25: Add console die notification ...................................................................... mb/msi/ms7d25: Add console die notification Add beeps and blink SATA LED on critical errors. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I45b8b4fda00d58a1ab1d7dfab49d6f841bc0b000 --- M src/mainboard/msi/ms7d25/Kconfig M src/mainboard/msi/ms7d25/Makefile.inc A src/mainboard/msi/ms7d25/die.c 3 files changed, 58 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/69821/1 diff --git a/src/mainboard/msi/ms7d25/Kconfig b/src/mainboard/msi/ms7d25/Kconfig index 0c8130f..e55d03d 100644 --- a/src/mainboard/msi/ms7d25/Kconfig +++ b/src/mainboard/msi/ms7d25/Kconfig @@ -13,6 +13,7 @@ select INTEL_GMA_HAVE_VBT select CRB_TPM select HAVE_INTEL_PTT + select USE_LEGACY_8254_TIMER if BOARD_MSI_MS7D25 @@ -41,10 +42,6 @@ bool default n -config USE_LEGACY_8254_TIMER - bool - default n - config CBFS_SIZE hex default 0x1000000 diff --git a/src/mainboard/msi/ms7d25/Makefile.inc b/src/mainboard/msi/ms7d25/Makefile.inc index 2e6759f..deb5ff6 100644 --- a/src/mainboard/msi/ms7d25/Makefile.inc +++ b/src/mainboard/msi/ms7d25/Makefile.inc @@ -5,3 +5,6 @@ romstage-y += romstage_fsp_params.c ramstage-y += mainboard.c + +all-y += die.c +smm-y += die.c diff --git a/src/mainboard/msi/ms7d25/die.c b/src/mainboard/msi/ms7d25/die.c new file mode 100644 index 0000000..52b3338 --- /dev/null +++ b/src/mainboard/msi/ms7d25/die.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <pc80/i8254.h> +#include <soc/gpio.h> +#include <delay.h> +#include <gpio.h> + +static void beep_and_blink(void) +{ + static uint8_t blink = 0; + static uint8_t beep_count = 0; + + gpio_set(GPP_E8, blink); + /* Beep 12 times at most, constant beeps may be annoying */ + if (beep_count < 12) { + beep(800, 300); + mdelay(200); + beep_count++; + } else { + mdelay(500); + } + + blink ^= 1; +} + +void die_notify(void) +{ + if (ENV_POSTCAR) + return; + + /* Make SATA LED blink and use PC SPKR */ + gpio_output(GPP_E8, 0); + + while (1) { + beep_and_blink(); + beep_and_blink(); + beep_and_blink(); + beep_and_blink(); + delay(2); + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/69821 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45b8b4fda00d58a1ab1d7dfab49d6f841bc0b000 Gerrit-Change-Number: 69821 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/msi/ms7d25: Update USB port macros
by Michał Żygowski (Code Review) 18 Nov '22

18 Nov '22

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69820 ) Change subject: mb/msi/ms7d25: Update USB port macros ...................................................................... mb/msi/ms7d25: Update USB port macros Update USB port macros: - change onboard ports to SHORT: MYSTIC LIGHT, LAN_USB1, PS2_USB1, HUB to USB 2.0 headers, HUB to read USB 2.0 - change USB type C header to LONG which caused hard lockups on the port making it unable to enumerate in UEFI Payload and Linux - add empty definitions for USBr ports Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I91198aa713e9084ff3906c267ee1b37b10c71843 --- M src/mainboard/msi/ms7d25/devicetree.cb 1 file changed, 28 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/69820/1 diff --git a/src/mainboard/msi/ms7d25/devicetree.cb b/src/mainboard/msi/ms7d25/devicetree.cb index 189faf6..ec2a5a3 100644 --- a/src/mainboard/msi/ms7d25/devicetree.cb +++ b/src/mainboard/msi/ms7d25/devicetree.cb @@ -13,20 +13,22 @@ register "pmc_gpe0_dw2" = "GPD" # USB Configuration - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # USB-C LAN_USB1 - register "usb2_ports[1]" = "USB2_PORT_MAX(OC1)" # MSI MYSTIC LIGHT - register "usb2_ports[2]" = "USB2_PORT_MAX(OC0)" # USB-A LAN_USB1 - register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC0)" # JUSB5 - register "usb2_ports[4]" = "USB2_PORT_MAX(OC3)" # HUB to rear USB 2.0 + register "usb2_ports[0]" = "USB2_PORT_SHORT(OC2)" # USB-C LAN_USB1 + register "usb2_ports[1]" = "USB2_PORT_SHORT(OC1)" # MSI MYSTIC LIGHT + register "usb2_ports[2]" = "USB2_PORT_SHORT(OC0)" # USB-A LAN_USB1 + register "usb2_ports[3]" = "USB2_PORT_LONG(OC0)" # JUSB5 + register "usb2_ports[4]" = "USB2_PORT_SHORT(OC3)" # HUB to rear USB 2.0 register "usb2_ports[5]" = "USB2_PORT_LONG(OC3)" # empty? register "usb2_ports[6]" = "USB2_PORT_LONG(OC7)" # JUSB4 register "usb2_ports[7]" = "USB2_PORT_LONG(OC0)" # JUSB4 register "usb2_ports[8]" = "USB2_PORT_LONG(OC2)" # JUSB3 register "usb2_ports[9]" = "USB2_PORT_LONG(OC7)" # JUSB3 - register "usb2_ports[10]" = "USB2_PORT_MAX(OC0)" # PS2_USB1 - register "usb2_ports[11]" = "USB2_PORT_MAX(OC0)" # PS2_USB1 - register "usb2_ports[12]" = "USB2_PORT_MAX(OC0)" # HUB to USB 2.0 headers - register "usb2_ports[13]" = "USB2_PORT_MAX(OC6)" # CNVi BT + register "usb2_ports[10]" = "USB2_PORT_SHORT(OC0)" # PS2_USB1 + register "usb2_ports[11]" = "USB2_PORT_SHORT(OC0)" # PS2_USB1 + register "usb2_ports[12]" = "USB2_PORT_SHORT(OC0)" # HUB to USB 2.0 headers + register "usb2_ports[13]" = "USB2_PORT_SHORT(OC6)" # CNVi BT + register "usb2_ports[14]" = "USB2_PORT_EMPTY" # USB Redirection port 1 + register "usb2_ports[15]" = "USB2_PORT_EMPTY" # USB Redirection port 2 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # USB-C LAN_USB1 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB-A LAN_USB1 -- To view, visit https://review.coreboot.org/c/coreboot/+/69820 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91198aa713e9084ff3906c267ee1b37b10c71843 Gerrit-Change-Number: 69820 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: intelblocks/vtd: Add VT-d block with DMA protection API
by Michał Żygowski (Code Review) 18 Nov '22

18 Nov '22

Attention is currently required from: Michał Kopeć, Angel Pons. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68449 ) Change subject: intelblocks/vtd: Add VT-d block with DMA protection API ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/common/block/vtd/vtd.c: https://review.coreboot.org/c/coreboot/+/68449/comment/6b2db699_a36435e5 PS7, Line 158: if (vtd_read32(vtd_base, PMEN_REG) & PMEN_PRS) { > Looks like these `if`s don't need to be nested This is a recheck if the protection has been really disabled after clearing PMEN_EPM. What do you mean by "don't need to be nested"? -- To view, visit https://review.coreboot.org/c/coreboot/+/68449 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id7edf982457c1139624e5cd383788eda41d6a948 Gerrit-Change-Number: 68449 Gerrit-PatchSet: 7 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 18 Nov 2022 15:24:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-MessageType: comment

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