coreboot-gerrit November 2022

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[L] Change in coreboot[master]: [RFC] Pull ligfxinit in early romstage
by build bot (Jenkins) (Code Review) 19 Nov '22

19 Nov '22

Attention is currently required from: Nico Huber, Tarun Tuli, Martin L Roth, Angel Pons, Andrey Petrov. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69757 ) Change subject: [RFC] Pull ligfxinit in early romstage ...................................................................... Patch Set 2: (16 comments) File src/soc/intel/alderlake/romstage/graphics.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164071): https://review.coreboot.org/c/coreboot/+/69757/comment/1b3debc7_6f459809 PS2, Line 13: struct cpuid_result cp = cpuid_ext(1, 0); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164071): https://review.coreboot.org/c/coreboot/+/69757/comment/fe784de1_fa2b9190 PS2, Line 16: if (!(cp.ecx & (1 << 6))) please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164071): https://review.coreboot.org/c/coreboot/+/69757/comment/68beda0c_d52e1c31 PS2, Line 16: if (!(cp.ecx & (1 << 6))) suspect code indent for conditional statements (7, 15) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164071): https://review.coreboot.org/c/coreboot/+/69757/comment/dc60b22e_1fde611a PS2, Line 17: return; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164071): https://review.coreboot.org/c/coreboot/+/69757/comment/23bf10b9_cecca2e6 PS2, Line 17: return; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164071): https://review.coreboot.org/c/coreboot/+/69757/comment/0f6a79d9_9c5956c7 PS2, Line 20: if (!(read32((void *)0xfed30010) & 1)) please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164071): https://review.coreboot.org/c/coreboot/+/69757/comment/e5566f3e_14214e00 PS2, Line 20: if (!(read32((void *)0xfed30010) & 1)) suspect code indent for conditional statements (7, 15) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164071): https://review.coreboot.org/c/coreboot/+/69757/comment/e54881da_185e190f PS2, Line 21: return; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164071): https://review.coreboot.org/c/coreboot/+/69757/comment/7d0cb6ca_7a90e240 PS2, Line 21: return; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164071): https://review.coreboot.org/c/coreboot/+/69757/comment/346b0fdb_70e31760 PS2, Line 24: while (!(read8((void *)0xfed40000) & (1 << 7))) please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164071): https://review.coreboot.org/c/coreboot/+/69757/comment/95bd8cbc_89b392cd PS2, Line 24: while (!(read8((void *)0xfed40000) & (1 << 7))) suspect code indent for conditional statements (7, 15) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164071): https://review.coreboot.org/c/coreboot/+/69757/comment/dcbc4fa7_54b4306e PS2, Line 25: ; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164071): https://review.coreboot.org/c/coreboot/+/69757/comment/b00cf2e7_674ac7aa PS2, Line 25: ; please, no spaces at the start of a line File src/soc/intel/common/block/graphics/romstage.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164071): https://review.coreboot.org/c/coreboot/+/69757/comment/0d90df30_583313ba PS2, Line 27: if (CONFIG(ROMSTAGE_MAINBOARD_USE_LIBGFXINIT)) { code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164071): https://review.coreboot.org/c/coreboot/+/69757/comment/b03d76dd_ed056cd2 PS2, Line 27: if (CONFIG(ROMSTAGE_MAINBOARD_USE_LIBGFXINIT)) { please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164071): https://review.coreboot.org/c/coreboot/+/69757/comment/efa4a604_534d5038 PS2, Line 27: if (CONFIG(ROMSTAGE_MAINBOARD_USE_LIBGFXINIT)) { please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/69757 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3357e746a7d94afe9d285c36ed6172c7bfd9718 Gerrit-Change-Number: 69757 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Sat, 19 Nov 2022 01:22:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/var/marasov: update field STORAGE of fw_config
by Nick Vaccaro (Code Review) 19 Nov '22

19 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Kyle Lin, Frank Chu. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69786 ) Change subject: mb/google/brya/var/marasov: update field STORAGE of fw_config ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69786 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17f8a852808d279a1f2b08b364cd4e525a807560 Gerrit-Change-Number: 69786 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kyle Lin <kylelinck(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Tammy Huang <tammy_huang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kyle Lin <kylelinck(a)google.com> Gerrit-Attention: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Sat, 19 Nov 2022 01:14:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: src/northbridge: Remove unnecessary space after casts
by Angel Pons (Code Review) 19 Nov '22

19 Nov '22

Attention is currently required from: Elyes Haouas. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69813 ) Change subject: src/northbridge: Remove unnecessary space after casts ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69813 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6c1a17d15e24ecdc56b0cc9cb7e7dc7d6e6936b Gerrit-Change-Number: 69813 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sat, 19 Nov 2022 01:06:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: adds basic support for Raptorlake-S CPUs on Alderlake PCH (#640555)
by Name of user not set (Code Review) 19 Nov '22

19 Nov '22

Name of user not set #1004406 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69798 ) Change subject: adds basic support for Raptorlake-S CPUs on Alderlake PCH (#640555) ...................................................................... adds basic support for Raptorlake-S CPUs on Alderlake PCH (#640555) Change-Id: I767dd08a169a6af59188d9ecd73520b916f69155 Signed-off-by: Max Fritz <antischmock(a)googlemail.com> --- M 3rdparty/intel-microcode M src/include/cpu/intel/cpu_ids.h M src/include/device/pci_ids.h M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/alderlake/bootblock/report_platform.c M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/cpu.c M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/include/soc/cpu.h M src/soc/intel/alderlake/vr_config.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/systemagent/systemagent.c 13 files changed, 81 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/69798/1 diff --git a/3rdparty/intel-microcode b/3rdparty/intel-microcode index 6c0c469..262f0c9 160000 --- a/3rdparty/intel-microcode +++ b/3rdparty/intel-microcode @@ -1 +1 @@ -Subproject commit 6c0c4691e5bb446e0e428ebca595164709c59586 +Subproject commit 262f0c97f2fbc3839a59523cc6c6bcf500e2850b diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h index 381f20c..2a16f6f 100644 --- a/src/include/cpu/intel/cpu_ids.h +++ b/src/include/cpu/intel/cpu_ids.h @@ -64,6 +64,7 @@ #define CPUID_ALDERLAKE_N_A0 0xb06e0 #define CPUID_METEORLAKE_A0_1 0xa06a0 #define CPUID_METEORLAKE_A0_2 0xa06a1 +#define CPUID_RAPTORLAKE_S_S0 0xb0671 #define CPUID_RAPTORLAKE_P_J0 0xb06a2 #define CPUID_RAPTORLAKE_P_Q0 0xb06a3 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index f1f77e0..c645a3b 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3989,10 +3989,10 @@ #define PCI_DID_INTEL_ADL_P_GT2_7 0x4628 #define PCI_DID_INTEL_ADL_P_GT2_8 0x46b1 #define PCI_DID_INTEL_ADL_P_GT2_9 0x4626 -#define PCI_DID_INTEL_ADL_S_GT1 0x4680 -#define PCI_DID_INTEL_ADL_S_GT1_1 0x4682 +#define PCI_DID_INTEL_ADL_S_GT1 0x4680 // RPL_S_6P_8E +#define PCI_DID_INTEL_ADL_S_GT1_1 0x4682 // RPL_S_4P_6E #define PCI_DID_INTEL_ADL_S_GT2 0x4690 -#define PCI_DID_INTEL_ADL_S_GT2_1 0x4692 +#define PCI_DID_INTEL_ADL_S_GT2_1 0x4692 // RPL_S_4P_0E #define PCI_DID_INTEL_ADL_S_GT2_2 0x4693 #define PCI_DID_INTEL_ADL_M_GT1 0x46c0 #define PCI_DID_INTEL_ADL_M_GT2 0x46aa @@ -4005,6 +4005,9 @@ #define PCI_DID_INTEL_MTL_P_GT2_2 0x7d50 #define PCI_DID_INTEL_MTL_P_GT2_3 0x7d55 #define PCI_DID_INTEL_MTL_P_GT2_4 0x7d60 +#define PCI_DID_INTEL_RPL_S_GT1 0xa780 +#define PCI_DID_INTEL_RPL_S_GT2 0xa782 +#define PCI_DID_INTEL_RPL_S_GT3 0xa783 #define PCI_DID_INTEL_RPL_P_GT1 0xa720 #define PCI_DID_INTEL_RPL_P_GT2 0xa7a8 #define PCI_DID_INTEL_RPL_P_GT3 0xa7a0 @@ -4102,9 +4105,9 @@ #define PCI_DID_INTEL_ADL_S_ID_3 0x4668 #define PCI_DID_INTEL_ADL_S_ID_4 0x466c #define PCI_DID_INTEL_ADL_S_ID_5 0x4670 -#define PCI_DID_INTEL_ADL_S_ID_6 0x4640 +#define PCI_DID_INTEL_ADL_S_ID_6 0x4640 // RPL_S_6P_8E #define PCI_DID_INTEL_ADL_S_ID_7 0x4644 -#define PCI_DID_INTEL_ADL_S_ID_8 0x4648 +#define PCI_DID_INTEL_ADL_S_ID_8 0x4648 // RPL_S_6P_4E #define PCI_DID_INTEL_ADL_S_ID_9 0x464c #define PCI_DID_INTEL_ADL_S_ID_10 0x4650 #define PCI_DID_INTEL_ADL_S_ID_11 0x4630 @@ -4132,6 +4135,11 @@ #define PCI_DID_INTEL_MTL_P_ID_2 0x7D02 #define PCI_DID_INTEL_MTL_P_ID_3 0x7d14 #define PCI_DID_INTEL_MTL_P_ID_4 0x7d15 +#define PCI_DID_INTEL_RPL_S_ID_1 0xa700 +#define PCI_DID_INTEL_RPL_S_ID_2 0xa703 +#define PCI_DID_INTEL_RPL_S_ID_3 0xa704 +#define PCI_DID_INTEL_RPL_S_ID_4 0xa705 +#define PCI_DID_INTEL_RPL_S_ID_5 0x4692 #define PCI_DID_INTEL_RPL_P_ID_1 0xa706 #define PCI_DID_INTEL_RPL_P_ID_2 0xa707 #define PCI_DID_INTEL_RPL_P_ID_3 0xa708 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 08d4132..a09db54 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -154,7 +154,7 @@ config MAX_CPUS int - default 24 + default 32 config DCACHE_RAM_BASE default 0xfef00000 diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index 7f808ff..6f603b7 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -78,6 +78,7 @@ # 06-97-02 are ADL-S/HX Quality Samples but also ADL-HX Engineering Samples # ADL-S/HX C0 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-97-02 +cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-b7-01 # ADL-S H0 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-97-05 else diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c index 2be7546..e7d85b5 100644 --- a/src/soc/intel/alderlake/bootblock/report_platform.c +++ b/src/soc/intel/alderlake/bootblock/report_platform.c @@ -34,6 +34,7 @@ { CPUID_ALDERLAKE_S_C0, "Alderlake-S C0 Platform" }, { CPUID_ALDERLAKE_S_G0, "Alderlake-S G0 Platform" }, { CPUID_ALDERLAKE_S_H0, "Alderlake-S H0 Platform" }, + { CPUID_RAPTORLAKE_S_S0, "Raptorlake-S S0 Platform" }, { CPUID_RAPTORLAKE_P_J0, "Raptorlake-P J0 Platform" }, { CPUID_RAPTORLAKE_P_Q0, "Raptorlake-P Q0 Platform" }, }; @@ -71,6 +72,11 @@ { PCI_DID_INTEL_ADL_S_ID_12, "Alderlake-S (2+0)" }, { PCI_DID_INTEL_ADL_S_ID_13, "Alderlake-S" }, { PCI_DID_INTEL_ADL_S_ID_14, "Alderlake-S" }, + { PCI_DID_INTEL_RPL_S_ID_1, "Raptorlake-S (8+16)" }, + { PCI_DID_INTEL_RPL_S_ID_2, "Raptorlake-S (8+8)" }, + { PCI_DID_INTEL_RPL_S_ID_3, "Raptorlake-S (6+8)" }, + { PCI_DID_INTEL_RPL_S_ID_4, "Raptorlake-S (6+4)" }, + { PCI_DID_INTEL_RPL_S_ID_5, "Raptorlake-S (4+0)" }, { PCI_DID_INTEL_RPL_P_ID_1, "Raptorlake-P" }, { PCI_DID_INTEL_RPL_P_ID_2, "Raptorlake-P" }, { PCI_DID_INTEL_RPL_P_ID_3, "Raptorlake-P" }, @@ -198,6 +204,9 @@ { PCI_DID_INTEL_ADL_S_GT2, "Alderlake S GT2" }, { PCI_DID_INTEL_ADL_S_GT2_1, "Alderlake S GT2" }, { PCI_DID_INTEL_ADL_S_GT2_2, "Alderlake S GT2" }, + { PCI_DID_INTEL_RPL_S_GT1, "Raptorlake S GT1(32EU)" }, + { PCI_DID_INTEL_RPL_S_GT2, "Raptorlake S GT2(24EU)" }, + { PCI_DID_INTEL_RPL_S_GT3, "Raptorlake S GT3(16EU)" }, { PCI_DID_INTEL_RPL_P_GT1, "Raptorlake P GT1" }, { PCI_DID_INTEL_RPL_P_GT2, "Raptorlake P GT2" }, { PCI_DID_INTEL_RPL_P_GT3, "Raptorlake P GT3" }, diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index a732fe6..cdf47a1 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -132,6 +132,9 @@ { PCI_DID_INTEL_ADL_S_ID_11, ADL_S_402_60W_CORE, TDP_60W }, { PCI_DID_INTEL_ADL_S_ID_12, ADL_S_202_35W_CORE, TDP_35W }, { PCI_DID_INTEL_ADL_S_ID_12, ADL_S_202_46W_CORE, TDP_46W }, + { PCI_DID_INTEL_RPL_S_ID_1, ADL_S_882_125W_CORE, TDP_125W }, + { PCI_DID_INTEL_RPL_S_ID_2, ADL_S_882_125W_CORE, TDP_125W }, + { PCI_DID_INTEL_RPL_S_ID_3, ADL_S_882_125W_CORE, TDP_125W }, { PCI_DID_INTEL_RPL_P_ID_1, RPL_P_682_642_482_45W_CORE, TDP_45W }, { PCI_DID_INTEL_RPL_P_ID_2, RPL_P_682_482_282_28W_CORE, TDP_28W }, { PCI_DID_INTEL_RPL_P_ID_3, RPL_P_282_242_142_15W_CORE, TDP_15W }, diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index 027e978..4ec1479 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -245,6 +245,14 @@ PCI_DID_INTEL_ADL_N_ID_4, }; + const uint16_t rpl_s_mch_ids[] = { + PCI_DID_INTEL_RPL_S_ID_1, + PCI_DID_INTEL_RPL_S_ID_2, + PCI_DID_INTEL_RPL_S_ID_3, + PCI_DID_INTEL_RPL_S_ID_4, + PCI_DID_INTEL_RPL_S_ID_5 + }; + const uint16_t rpl_p_mch_ids[] = { PCI_DID_INTEL_RPL_P_ID_1, PCI_DID_INTEL_RPL_P_ID_2, @@ -271,6 +279,11 @@ return ADL_S; } + for (size_t i = 0; i < ARRAY_SIZE(rpl_s_mch_ids); i++) { + if (rpl_s_mch_ids[i] == mchid) + return RPL_S; + } + for (size_t i = 0; i < ARRAY_SIZE(adl_n_mch_ids); i++) { if (adl_n_mch_ids[i] == mchid) return ADL_N; @@ -294,6 +307,7 @@ case RPL_P: return LPM_S0i2_0 | LPM_S0i3_0; case ADL_S: + case RPL_S: return LPM_S0i2_0 | LPM_S0i2_1; default: printk(BIOS_ERR, "Unknown ADL CPU type: %d\n", type); diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 26eba76..1826be3 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -536,6 +536,11 @@ case PCI_DID_INTEL_ADL_S_ID_10: case PCI_DID_INTEL_ADL_S_ID_11: case PCI_DID_INTEL_ADL_S_ID_12: + case PCI_DID_INTEL_RPL_S_ID_1: + case PCI_DID_INTEL_RPL_S_ID_2: + case PCI_DID_INTEL_RPL_S_ID_3: + case PCI_DID_INTEL_RPL_S_ID_4: + case PCI_DID_INTEL_RPL_S_ID_5: return ICC_MAX_ADL_S; default: printk(BIOS_ERR, "Unknown MCH ID: 0x%4x, skipping VccInAuxImonIccMax config\n", diff --git a/src/soc/intel/alderlake/include/soc/cpu.h b/src/soc/intel/alderlake/include/soc/cpu.h index 424e02a..4cee4ae 100644 --- a/src/soc/intel/alderlake/include/soc/cpu.h +++ b/src/soc/intel/alderlake/include/soc/cpu.h @@ -25,6 +25,7 @@ ADL_N, ADL_P, ADL_S, + RPL_S, RPL_P, }; diff --git a/src/soc/intel/alderlake/vr_config.c b/src/soc/intel/alderlake/vr_config.c index c090641..080856a 100644 --- a/src/soc/intel/alderlake/vr_config.c +++ b/src/soc/intel/alderlake/vr_config.c @@ -126,6 +126,10 @@ { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, + { PCI_DID_INTEL_RPL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) }, + { PCI_DID_INTEL_RPL_S_ID_2, 125, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) }, + { PCI_DID_INTEL_RPL_S_ID_3, 125, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) }, + { PCI_DID_INTEL_RPL_S_ID_4, 125, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) }, { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) }, @@ -167,6 +171,10 @@ { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_ICC(102, 55) }, { PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) }, { PCI_DID_INTEL_RPL_P_ID_4, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) }, + { PCI_DID_INTEL_RPL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_ICC(280, 30) }, + { PCI_DID_INTEL_RPL_S_ID_2, 125, VR_CFG_ALL_DOMAINS_ICC(280, 30) }, + { PCI_DID_INTEL_RPL_S_ID_3, 125, VR_CFG_ALL_DOMAINS_ICC(280, 30) }, + { PCI_DID_INTEL_RPL_S_ID_4, 125, VR_CFG_ALL_DOMAINS_ICC(280, 30) }, { PCI_DID_INTEL_ADL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_ICC(280, 30) }, { PCI_DID_INTEL_ADL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_ICC(280, 30) }, { PCI_DID_INTEL_ADL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_ICC(240, 30) }, @@ -204,6 +212,10 @@ { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_RPL_P_ID_4, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DID_INTEL_RPL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, + { PCI_DID_INTEL_RPL_S_ID_2, 125, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, + { PCI_DID_INTEL_RPL_S_ID_3, 125, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, + { PCI_DID_INTEL_RPL_S_ID_4, 125, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, { PCI_DID_INTEL_ADL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, { PCI_DID_INTEL_ADL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, { PCI_DID_INTEL_ADL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, @@ -241,6 +253,10 @@ { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(54, 54) }, { PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(41, 41) }, { PCI_DID_INTEL_RPL_P_ID_4, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(41, 41) }, + { PCI_DID_INTEL_RPL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 132) }, + { PCI_DID_INTEL_RPL_S_ID_2, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 132) }, + { PCI_DID_INTEL_RPL_S_ID_3, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 132) }, + { PCI_DID_INTEL_RPL_S_ID_4, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 132) }, { PCI_DID_INTEL_ADL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 132) }, { PCI_DID_INTEL_ADL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 132) }, { PCI_DID_INTEL_ADL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 89) }, diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index d8ca0b3..395ffa4 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -81,6 +81,7 @@ { X86_VENDOR_INTEL, CPUID_ALDERLAKE_Q0 }, { X86_VENDOR_INTEL, CPUID_ALDERLAKE_R0 }, { X86_VENDOR_INTEL, CPUID_ALDERLAKE_N_A0 }, + { X86_VENDOR_INTEL, CPUID_RAPTORLAKE_S_S0 }, { X86_VENDOR_INTEL, CPUID_RAPTORLAKE_P_J0 }, { X86_VENDOR_INTEL, CPUID_RAPTORLAKE_P_Q0 }, { 0, 0 }, diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 90b3335..aafdffb 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -439,6 +439,11 @@ PCI_DID_INTEL_ADL_N_ID_2, PCI_DID_INTEL_ADL_N_ID_3, PCI_DID_INTEL_ADL_N_ID_4, + PCI_DID_INTEL_RPL_S_ID_1, + PCI_DID_INTEL_RPL_S_ID_2, + PCI_DID_INTEL_RPL_S_ID_3, + PCI_DID_INTEL_RPL_S_ID_4, + PCI_DID_INTEL_RPL_S_ID_5, PCI_DID_INTEL_RPL_P_ID_1, PCI_DID_INTEL_RPL_P_ID_2, PCI_DID_INTEL_RPL_P_ID_3, -- To view, visit https://review.coreboot.org/c/coreboot/+/69798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I767dd08a169a6af59188d9ecd73520b916f69155 Gerrit-Change-Number: 69798 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1004406 Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: [RFC] Pull ligfxinit in early romstage
by Jérémy Compostella (Code Review) 19 Nov '22

19 Nov '22

Attention is currently required from: Nico Huber, Tarun Tuli, Martin L Roth, Angel Pons, Andrey Petrov. Hello build bot (Jenkins), Tarun Tuli, Martin L Roth, Subrata Banik, Angel Pons, Andrey Petrov, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69757 to look at the new patch set (#2). Change subject: [RFC] Pull ligfxinit in early romstage ...................................................................... [RFC] Pull ligfxinit in early romstage The goal is to display a text message while memory training is in progress. Change-Id: If3357e746a7d94afe9d285c36ed6172c7bfd9718 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M Makefile M src/arch/x86/car.ld M src/console/Makefile.inc M src/device/Kconfig M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/intel/gma/Kconfig M src/drivers/intel/gma/Makefile.inc M src/drivers/pc80/vga/Kconfig M src/drivers/pc80/vga/Makefile.inc M src/include/adainit.h M src/lib/Kconfig M src/lib/Makefile.inc M src/lib/gnat/Makefile.inc M src/mainboard/google/brya/Makefile.inc A src/mainboard/google/brya/gma-mainboard.ads M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/romstage/Makefile.inc A src/soc/intel/alderlake/romstage/graphics.c M src/soc/intel/common/block/graphics/Makefile.inc A src/soc/intel/common/block/graphics/romstage.c 21 files changed, 305 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/69757/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69757 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3357e746a7d94afe9d285c36ed6172c7bfd9718 Gerrit-Change-Number: 69757 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: acpi/Kconfig: Remove unused ACPI_EINJ config option
by David Hendricks (Code Review) 19 Nov '22

19 Nov '22

Attention is currently required from: Lance Zhao, Nico Huber, David Hendricks, Tim Wawrzynczak, Eric Lai, Elyes Haouas. David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68593 ) Change subject: acpi/Kconfig: Remove unused ACPI_EINJ config option ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > Just to make sure we're on the same page: Did anyone see a `CONFIG_ACPI_EINJ`, […] Yes, it's used in silicon vendors' development repos which are used by various other companies who are working on coreboot for server platforms. Moving the Kconfig variable somewhere else downstream will only require a little bit of extra effort. IMO it's more valuable to have people work with upstream as much as possible rather than push them to diverge further away. -- To view, visit https://review.coreboot.org/c/coreboot/+/68593 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I222478572a9e5efadd6719a164558833298e4c99 Gerrit-Change-Number: 68593 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Hendricks Gerrit-CC: David Hendricks <david.hendricks(a)gmail.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-CC: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Lance Zhao Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sat, 19 Nov 2022 00:00:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: David Hendricks <david.hendricks(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/mendocino: Increase CBFS_MCACHE size
by Felix Held (Code Review) 19 Nov '22

19 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin L Roth, Matt DeVillier, Jon Murphy, Fred Reitberger, Karthik Ramasubramanian. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69827 ) Change subject: soc/amd/mendocino: Increase CBFS_MCACHE size ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69827 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35e1a8c6d73e0870b6a43aac604f83a0b6c3aabe Gerrit-Change-Number: 69827 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 18 Nov 2022 22:34:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: include/memlayout.h: update comment about VBOOT2 work buffer size
by Felix Held (Code Review) 19 Nov '22

19 Nov '22

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69797 ) Change subject: include/memlayout.h: update comment about VBOOT2 work buffer size ...................................................................... include/memlayout.h: update comment about VBOOT2 work buffer size VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE is nowadays defined in vboot/firmware/2lib/include/2constants.h, so update the comment. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ia7c9a5476ae06d4bac762da1729aff878b7d0965 --- M src/include/memlayout.h 1 file changed, 14 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/69797/1 diff --git a/src/include/memlayout.h b/src/include/memlayout.h index 1e9fca8..7b6cfb6 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -161,7 +161,7 @@ #endif /* VBOOT2_WORK must always use VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE for its - * size argument. The constant is imported via vb2_workbuf_size.h. */ + * size argument. The constant is imported via 2constants.h. */ #define VBOOT2_WORK(addr, sz) \ REGION(vboot2_work, addr, sz, 16) \ _ = ASSERT(sz == VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE, \ -- To view, visit https://review.coreboot.org/c/coreboot/+/69797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7c9a5476ae06d4bac762da1729aff878b7d0965 Gerrit-Change-Number: 69797 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: libpayload: Fix compiler warnings
by Felix Singer (Code Review) 18 Nov '22

18 Nov '22

Attention is currently required from: Nico Huber, Thomas Heijligen. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69764 ) Change subject: libpayload: Fix compiler warnings ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69764 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id285c24cba790f181fa203f3117e5df35bed27c4 Gerrit-Change-Number: 69764 Gerrit-PatchSet: 2 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Comment-Date: Fri, 18 Nov 2022 21:12:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex: Disable `ACPI PM timer`
by Felix Held (Code Review) 18 Nov '22

18 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69685 ) Change subject: mb/google/rex: Disable `ACPI PM timer` ...................................................................... mb/google/rex: Disable `ACPI PM timer` This patch deselects `USE_PM_ACPI_TIMER` kconfig to ensure that ACPI PM timer remains disabled. The PM timer (by PMC IP) consumes more power and blocks S0ix so the timer is emulated by ucode to save power and unblock S0ix. TEST=Able to boot Google, Rex and ensure PMC MMIO register 0x18fc BIT 1 is set. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I2a23b417ff7fb6328323380a7df46b4b397fc8eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/69685 Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/rex/Kconfig 1 file changed, 26 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig index 05b4747..66e3591 100644 --- a/src/mainboard/google/rex/Kconfig +++ b/src/mainboard/google/rex/Kconfig @@ -106,4 +106,7 @@ int default 35 # GPE0_DW1_03 (GPP_E03) +config USE_PM_ACPI_TIMER + default n + endif # BOARD_GOOGLE_REX_COMMON -- To view, visit https://review.coreboot.org/c/coreboot/+/69685 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a23b417ff7fb6328323380a7df46b4b397fc8eb Gerrit-Change-Number: 69685 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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