coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[master]: Add basic support for Rapto Lake S CPUs on Alder Lake PCH (#640555) T...
by Name of user not set (Code Review) 20 Nov '22

20 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Name of user not set #1004406, Michal Zygowski. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Michal Zygowski, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69798 to look at the new patch set (#3). Change subject: Add basic support for Rapto Lake S CPUs on Alder Lake PCH (#640555) This was tested on a MSI PRO Z690-A (ms7d25) with Ubuntu 22.10 and LinuxBoot. TODOS are Intel VBT. ...................................................................... Add basic support for Rapto Lake S CPUs on Alder Lake PCH (#640555) This was tested on a MSI PRO Z690-A (ms7d25) with Ubuntu 22.10 and LinuxBoot. TODOS are Intel VBT. Change-Id: I767dd08a169a6af59188d9ecd73520b916f69155 Signed-off-by: Max Fritz <antischmock(a)googlemail.com> --- M 3rdparty/intel-microcode M src/include/cpu/intel/cpu_ids.h M src/include/device/pci_ids.h M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/alderlake/bootblock/report_platform.c M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/cpu.c M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/include/soc/cpu.h M src/soc/intel/alderlake/vr_config.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/systemagent/systemagent.c 13 files changed, 83 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/69798/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/69798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I767dd08a169a6af59188d9ecd73520b916f69155 Gerrit-Change-Number: 69798 Gerrit-PatchSet: 3 Gerrit-Owner: Name of user not set #1004406 Gerrit-Reviewer: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Name of user not set #1004406 Gerrit-Attention: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: Adds basic support for Rapto Lake S CPUs on Alder Lake PCH (#640555) ...
by Name of user not set (Code Review) 19 Nov '22

19 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Name of user not set #1004406, Michal Zygowski. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Michal Zygowski, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69798 to look at the new patch set (#2). Change subject: Adds basic support for Rapto Lake S CPUs on Alder Lake PCH (#640555) This was tested on a MSI PRO Z690-A (ms7d25) with Ubuntu 22.10 and LinuxBoot. TODOS are Intel VBT. ...................................................................... Adds basic support for Rapto Lake S CPUs on Alder Lake PCH (#640555) This was tested on a MSI PRO Z690-A (ms7d25) with Ubuntu 22.10 and LinuxBoot. TODOS are Intel VBT. Change-Id: I767dd08a169a6af59188d9ecd73520b916f69155 Signed-off-by: Max Fritz <antischmock(a)googlemail.com> --- M 3rdparty/intel-microcode M src/include/cpu/intel/cpu_ids.h M src/include/device/pci_ids.h M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/alderlake/bootblock/report_platform.c M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/cpu.c M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/include/soc/cpu.h M src/soc/intel/alderlake/vr_config.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/systemagent/systemagent.c 13 files changed, 83 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/69798/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I767dd08a169a6af59188d9ecd73520b916f69155 Gerrit-Change-Number: 69798 Gerrit-PatchSet: 2 Gerrit-Owner: Name of user not set #1004406 Gerrit-Reviewer: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Name of user not set #1004406 Gerrit-Attention: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: adds basic support for Raptorlake-S CPUs on Alderlake PCH (#640555)
by Paul Menzel (Code Review) 19 Nov '22

19 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Name of user not set #1004406, Michal Zygowski. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69798 ) Change subject: adds basic support for Raptorlake-S CPUs on Alderlake PCH (#640555) ...................................................................... Patch Set 1: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/69798/comment/c1deca27_31ee9852 PS1, Line 7: Alderlake Alder Lake https://review.coreboot.org/c/coreboot/+/69798/comment/0fafd8ce_7d316d16 PS1, Line 7: adds Add https://review.coreboot.org/c/coreboot/+/69798/comment/05a74d2f_07f2e690 PS1, Line 8: Please elaborate, what you did, and how it was tested. Patchset: PS1: Welcome to coreboot, and thank you for the contribution. -- To view, visit https://review.coreboot.org/c/coreboot/+/69798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I767dd08a169a6af59188d9ecd73520b916f69155 Gerrit-Change-Number: 69798 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1004406 Gerrit-Reviewer: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Name of user not set #1004406 Gerrit-Attention: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-Comment-Date: Sat, 19 Nov 2022 21:23:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/mendocino: Increase CBFS_MCACHE size
by Paul Menzel (Code Review) 19 Nov '22

19 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Jon Murphy, Fred Reitberger, Karthik Ramasubramanian. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69827 ) Change subject: soc/amd/mendocino: Increase CBFS_MCACHE size ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69827/comment/d12c49bf_b7f08e2f PS1, Line 12: to required : 14 KiB. How was the required size determined? -- To view, visit https://review.coreboot.org/c/coreboot/+/69827 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35e1a8c6d73e0870b6a43aac604f83a0b6c3aabe Gerrit-Change-Number: 69827 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Sat, 19 Nov 2022 21:22:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/common: Fix the TCSS DisplayPort detection flow
by 9elements QA (Code Review) 19 Nov '22

19 Nov '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69694 ) Change subject: soc/intel/common: Fix the TCSS DisplayPort detection flow ...................................................................... Patch Set 3: Automatic boot test returned (PASS/FAIL/TOTAL): 14 / 1 / 15 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/137299 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/137298 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/137297 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/137296 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/137295 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/137294 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/137293 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/137292 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/137291 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/137290 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/137289 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/137288 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/137287 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/137286 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/137285 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/69694 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cb95ec7fcc7e1a86e86466e6d45390eedcc4531 Gerrit-Change-Number: 69694 Gerrit-PatchSet: 3 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Sat, 19 Nov 2022 17:55:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: [NOTFORMERGE] squashed intel pmutil ops
by build bot (Jenkins) (Code Review) 19 Nov '22

19 Nov '22

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[L] Change in coreboot[master]: [NOTFORMERGE] aopen,smm,i82801,e7505
by build bot (Jenkins) (Code Review) 19 Nov '22

19 Nov '22

Attention is currently required from: Lance Zhao, Tim Wawrzynczak. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69759 ) Change subject: [NOTFORMERGE] aopen,smm,i82801,e7505 ...................................................................... Patch Set 2: (1 comment) File src/northbridge/intel/e7505/memmap.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164077): https://review.coreboot.org/c/coreboot/+/69759/comment/e4c0f463_b1175a34 PS2, Line 40: return 512 *KiB; need consistent spacing around '*' (ctx:WxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/69759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecfea92c032e89dff73d1258e031e9dc0b3ebeec Gerrit-Change-Number: 69759 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Comment-Date: Sat, 19 Nov 2022 16:25:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: [NOTFORMERGE] squashed intel pmutil ops
by Kyösti Mälkki (Code Review) 19 Nov '22

19 Nov '22

Attention is currently required from: Jeff Daly, Jonathan Zhang, Angel Pons, Arthur Heymans, Kyösti Mälkki, Tarun Tuli, Sean Rhodes, Subrata Banik, Johnny Lin, Kapil Porwal, Christian Walter, Vanessa Eusebio, Lean Sheng Tan, Werner Zeh, Tim Chu. Hello build bot (Jenkins), Jeff Daly, Jonathan Zhang, Angel Pons, Arthur Heymans, Tarun Tuli, Sean Rhodes, Subrata Banik, Johnny Lin, Kapil Porwal, Christian Walter, Vanessa Eusebio, Lean Sheng Tan, Werner Zeh, Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69760 to look at the new patch set (#3). Change subject: [NOTFORMERGE] squashed intel pmutil ops ...................................................................... [NOTFORMERGE] squashed intel pmutil ops Change-Id: I6b4db32888a6a979eee0cbcdbace97bc188ae71b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- A src/arch/x86/include/arch/io_bitops.h M src/mainboard/acer/aspire_vn7_572g/mainboard.c M src/mainboard/asus/p2b/variants/p3b-f/romstage.c M src/mainboard/google/auron/smihandler.c M src/mainboard/google/cyan/smihandler.c M src/mainboard/google/link/smihandler.c M src/mainboard/google/parrot/smihandler.c M src/mainboard/google/rambi/smihandler.c M src/mainboard/google/slippy/smihandler.c M src/mainboard/google/stout/ec.c M src/mainboard/google/stout/smihandler.c M src/mainboard/intel/strago/smihandler.c M src/mainboard/samsung/lumpy/smihandler.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/ironlake/gma.c M src/northbridge/intel/ironlake/raminit.c M src/northbridge/intel/sandybridge/gma.c M src/security/intel/txt/romstage.c M src/soc/intel/alderlake/acpi.c M src/soc/intel/alderlake/include/soc/pm.h M src/soc/intel/alderlake/pmutil.c M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/include/soc/pm.h M src/soc/intel/apollolake/pmutil.c M src/soc/intel/baytrail/bootblock/bootblock.c M src/soc/intel/baytrail/fadt.c M src/soc/intel/baytrail/include/soc/pm.h M src/soc/intel/baytrail/pmutil.c M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/baytrail/smihandler.c M src/soc/intel/baytrail/smm.c M src/soc/intel/braswell/bootblock/bootblock.c M src/soc/intel/braswell/fadt.c M src/soc/intel/braswell/gpio.c M src/soc/intel/braswell/include/soc/pm.h M src/soc/intel/braswell/lpc_init.c M src/soc/intel/braswell/pmutil.c M src/soc/intel/braswell/romstage/romstage.c M src/soc/intel/braswell/smihandler.c M src/soc/intel/braswell/smm.c M src/soc/intel/broadwell/include/soc/pm.h M src/soc/intel/broadwell/pch/bootblock.c M src/soc/intel/broadwell/pch/lpc.c M src/soc/intel/broadwell/pch/pmutil.c M src/soc/intel/broadwell/pch/power_state.c M src/soc/intel/broadwell/pch/smi.c M src/soc/intel/broadwell/pch/smihandler.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/include/soc/pm.h M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/include/intelblocks/tco.h M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/common/block/smbus/tco.c M src/soc/intel/common/block/smm/smihandler.c M src/soc/intel/common/block/smm/smitraphandler.c M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/denverton_ns/include/soc/soc_util.h M src/soc/intel/denverton_ns/pmutil.c M src/soc/intel/denverton_ns/romstage.c M src/soc/intel/denverton_ns/smihandler.c M src/soc/intel/denverton_ns/smm.c M src/soc/intel/denverton_ns/soc_util.c M src/soc/intel/elkhartlake/acpi.c M src/soc/intel/elkhartlake/bootblock/bootblock.c M src/soc/intel/elkhartlake/include/soc/pm.h M src/soc/intel/elkhartlake/pmutil.c M src/soc/intel/icelake/acpi.c M src/soc/intel/icelake/include/soc/pm.h M src/soc/intel/icelake/pmutil.c M src/soc/intel/jasperlake/acpi.c M src/soc/intel/jasperlake/include/soc/pm.h M src/soc/intel/jasperlake/pmutil.c M src/soc/intel/meteorlake/acpi.c M src/soc/intel/meteorlake/include/soc/pm.h M src/soc/intel/meteorlake/pmutil.c M src/soc/intel/quark/acpi.c M src/soc/intel/quark/include/soc/pm.h M src/soc/intel/quark/reg_access.c M src/soc/intel/skylake/fadt.c M src/soc/intel/skylake/include/soc/pm.h M src/soc/intel/skylake/pmc.c M src/soc/intel/skylake/pmutil.c M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/include/soc/pm.h M src/soc/intel/tigerlake/pmutil.c M src/soc/intel/xeon_sp/include/soc/pm.h M src/soc/intel/xeon_sp/pmutil.c M src/soc/intel/xeon_sp/skx/soc_acpi.c M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/bd82x6x/early_usb.c M src/southbridge/intel/bd82x6x/elog.c M src/southbridge/intel/bd82x6x/fadt.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/common/Makefile.inc M src/southbridge/intel/common/finalize.c M src/southbridge/intel/common/pmbase.c M src/southbridge/intel/common/pmbase.h M src/southbridge/intel/common/pmclib.c M src/southbridge/intel/common/pmutil.c M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/common/smi.c M src/southbridge/intel/common/smihandler.c A src/southbridge/intel/common/tco.c M src/southbridge/intel/common/tco.h M src/southbridge/intel/common/watchdog.c M src/southbridge/intel/i82371eb/acpi/i82371eb.asl M src/southbridge/intel/i82371eb/fadt.c M src/southbridge/intel/i82371eb/i82371eb.h M src/southbridge/intel/i82371eb/smbus.c M src/southbridge/intel/i82371eb/wakeup.c M src/southbridge/intel/i82801dx/fadt.c M src/southbridge/intel/i82801dx/i82801dx.h M src/southbridge/intel/i82801dx/lpc.c M src/southbridge/intel/i82801gx/early_init.c M src/southbridge/intel/i82801gx/fadt.c M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801ix/early_init.c M src/southbridge/intel/i82801ix/fadt.c M src/southbridge/intel/i82801ix/i82801ix.c M src/southbridge/intel/i82801ix/i82801ix.h M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801jx/early_init.c M src/southbridge/intel/i82801jx/fadt.c M src/southbridge/intel/i82801jx/i82801jx.c M src/southbridge/intel/i82801jx/i82801jx.h M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/early_pch.c M src/southbridge/intel/ibexpeak/early_usb.c M src/southbridge/intel/ibexpeak/fadt.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/pch.h M src/southbridge/intel/lynxpoint/early_pch.c M src/southbridge/intel/lynxpoint/elog.c M src/southbridge/intel/lynxpoint/fadt.c M src/southbridge/intel/lynxpoint/lp_gpio.c A src/southbridge/intel/lynxpoint/lp_gpio_ops.h M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/pch.c M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/intel/lynxpoint/pmutil.c M src/southbridge/intel/lynxpoint/smi.c M src/southbridge/intel/lynxpoint/smihandler.c 145 files changed, 1,096 insertions(+), 1,154 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/69760/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/69760 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b4db32888a6a979eee0cbcdbace97bc188ae71b Gerrit-Change-Number: 69760 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: [NOTFORMERGE] aopen,smm,i82801,e7505
by Kyösti Mälkki (Code Review) 19 Nov '22

19 Nov '22

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69759 to look at the new patch set (#2). Change subject: [NOTFORMERGE] aopen,smm,i82801,e7505 ...................................................................... [NOTFORMERGE] aopen,smm,i82801,e7505 Change-Id: Iecfea92c032e89dff73d1258e031e9dc0b3ebeec Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/acpi/Kconfig M src/acpi/acpi.c M src/cpu/intel/model_f2x/Kconfig M src/cpu/intel/model_f2x/Makefile.inc M src/cpu/intel/model_f2x/model_f2x_init.c A src/cpu/intel/model_f2x/mp_init.c M src/mainboard/asus/p2b/Kconfig D src/mainboard/asus/p2b/acpi_tables.c M src/northbridge/intel/e7505/Kconfig M src/northbridge/intel/e7505/e7505.h M src/northbridge/intel/e7505/memmap.c M src/northbridge/intel/e7505/northbridge.c M src/northbridge/intel/e7505/raminit.c M src/northbridge/intel/e7505/romstage.c M src/soc/intel/quark/Kconfig M src/soc/intel/quark/acpi.c M src/southbridge/intel/common/smi.c M src/southbridge/intel/i82801dx/Kconfig M src/southbridge/intel/i82801dx/Makefile.inc M src/southbridge/intel/i82801dx/bootblock.c A src/southbridge/intel/i82801dx/early_init.c D src/southbridge/intel/i82801dx/early_smbus.c M src/southbridge/intel/i82801dx/fadt.c M src/southbridge/intel/i82801dx/i82801dx.h M src/southbridge/intel/i82801dx/lpc.c A src/southbridge/intel/i82801dx/smihandler.c 26 files changed, 310 insertions(+), 161 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/69759/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecfea92c032e89dff73d1258e031e9dc0b3ebeec Gerrit-Change-Number: 69759 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: security/tpm: make log format configurable via Kconfig
by Martin L Roth (Code Review) 19 Nov '22

19 Nov '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68746 ) Change subject: security/tpm: make log format configurable via Kconfig ...................................................................... security/tpm: make log format configurable via Kconfig This commit doesn't add any new format options, just makes selecting existing format explicit. Ticket: https://ticket.coreboot.org/issues/422 Change-Id: I3903aff54e01093bc9ea75862bbf5989cc6e6c55 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68746 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/security/tpm/Kconfig M src/security/tpm/Makefile.inc M src/security/tpm/tspi/crtm.h 3 files changed, 47 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Michał Żygowski: Looks good to me, approved diff --git a/src/security/tpm/Kconfig b/src/security/tpm/Kconfig index fc339a2..5bc817d 100644 --- a/src/security/tpm/Kconfig +++ b/src/security/tpm/Kconfig @@ -94,6 +94,18 @@ help Enables measured boot (experimental) +choice + prompt "TPM event log format" + depends on TPM_MEASURED_BOOT + default TPM_LOG_CB + +config TPM_LOG_CB + bool "coreboot's custom format" + help + Custom coreboot-specific format of the log derived from TPM1 log format. + +endchoice + config TPM_MEASURED_BOOT_INIT_BOOTBLOCK bool depends on TPM_MEASURED_BOOT && !VBOOT diff --git a/src/security/tpm/Makefile.inc b/src/security/tpm/Makefile.inc index 8f633a8..7083c00 100644 --- a/src/security/tpm/Makefile.inc +++ b/src/security/tpm/Makefile.inc @@ -55,10 +55,10 @@ ramstage-y += tspi/crtm.c postcar-y += tspi/crtm.c -ramstage-y += tspi/log.c -romstage-y += tspi/log.c -verstage-y += tspi/log.c -postcar-y += tspi/log.c -bootblock-y += tspi/log.c +ramstage-$(CONFIG_TPM_LOG_CB) += tspi/log.c +romstage-$(CONFIG_TPM_LOG_CB) += tspi/log.c +verstage-$(CONFIG_TPM_LOG_CB) += tspi/log.c +postcar-$(CONFIG_TPM_LOG_CB) += tspi/log.c +bootblock-$(CONFIG_TPM_LOG_CB) += tspi/log.c endif # CONFIG_TPM_MEASURED_BOOT diff --git a/src/security/tpm/tspi/crtm.h b/src/security/tpm/tspi/crtm.h index bd5bc57..e8e44fd 100644 --- a/src/security/tpm/tspi/crtm.h +++ b/src/security/tpm/tspi/crtm.h @@ -16,7 +16,19 @@ */ #define TPM_RUNTIME_DATA_PCR 3 -#define TPM_MEASURE_ALGO (CONFIG(TPM1) ? VB2_HASH_SHA1 : VB2_HASH_SHA256) +#if CONFIG(TPM_LOG_CB) && CONFIG(TPM1) +# define TPM_MEASURE_ALGO VB2_HASH_SHA1 +#elif CONFIG(TPM_LOG_CB) && CONFIG(TPM2) +# define TPM_MEASURE_ALGO VB2_HASH_SHA256 +#endif + +#if !defined(TPM_MEASURE_ALGO) +# if !CONFIG(TPM_MEASURED_BOOT) +# define TPM_MEASURE_ALGO VB2_HASH_INVALID +# else +# error "Misconfiguration: failed to determine TPM hashing algorithm" +# endif +#endif /** * Measure digests cached in TCPA log entries into PCRs -- To view, visit https://review.coreboot.org/c/coreboot/+/68746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3903aff54e01093bc9ea75862bbf5989cc6e6c55 Gerrit-Change-Number: 68746 Gerrit-PatchSet: 8 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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