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Change subject: crossgcc: Upgrade CMake from 3.24.2 to 3.25.0
......................................................................
Patch Set 4: Code-Review+1
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Change subject: soc/cavium/common: Don't use Wstack-usage for llvm
......................................................................
Patch Set 1:
(1 comment)
File src/soc/cavium/common/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/69833/comment/08a19d2e_3f518743
PS1, Line 11: -Wframe-larger-than
Please mention the name in the commit message.
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Change subject: vc/amd/fsp/glinda/platform_descriptors.h: Update for glinda
......................................................................
Patch Set 1: Code-Review+2
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69704 )
Change subject: vc/amd/fsp/morgana/platform_descriptors.h: Update for morgana
......................................................................
vc/amd/fsp/morgana/platform_descriptors.h: Update for morgana
Update definitions to match morgana FSP.
Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com>
Change-Id: Ic893526789c05a298965702114d4a814466a5742
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69704
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de>
---
M src/vendorcode/amd/fsp/morgana/platform_descriptors.h
1 file changed, 36 insertions(+), 17 deletions(-)
Approvals:
build bot (Jenkins): Verified
Felix Held: Looks good to me, approved
diff --git a/src/vendorcode/amd/fsp/morgana/platform_descriptors.h b/src/vendorcode/amd/fsp/morgana/platform_descriptors.h
index 75bf3ad..4a02691 100644
--- a/src/vendorcode/amd/fsp/morgana/platform_descriptors.h
+++ b/src/vendorcode/amd/fsp/morgana/platform_descriptors.h
@@ -10,6 +10,8 @@
#ifndef PI_PLATFORM_DESCRIPTORS_H
#define PI_PLATFORM_DESCRIPTORS_H
+#include <stdint.h>
+
#define NUM_DXIO_PHY_PARAMS 6
#define NUM_DXIO_PORT_PARAMS 6
@@ -55,7 +57,7 @@
CLK_REQ1,
CLK_REQ2,
CLK_REQ3,
- CLK_REQ4_GFX,
+ CLK_REQ4,
CLK_REQ5,
CLK_REQ6,
CLK_ENABLE = 0xff,
@@ -144,8 +146,8 @@
DDI_DP_TO_LVDS, // DP-to-LVDS
DDI_NUTMEG_DP_TO_VGA, // Hudson-2 NutMeg DP-to-VGA
DDI_SINGLE_LINK_DVI_I, // Single Link DVI-I
- DDI_CRT, // CRT (VGA)
- DDI_LVDS, // LVDS
+ DDI_DP_W_TYPEC, // DP with USB type C
+ DDI_DP_WO_TYPEC, // DP without USB type C
DDI_EDP_TO_LVDS, // eDP-to-LVDS translator chip without AMD SW init
DDI_EDP_TO_LVDS_SW, // eDP-to-LVDS translator which requires AMD SW init
DDI_AUTO_DETECT, // VBIOS auto detect connector type
@@ -162,15 +164,17 @@
} fsp_ddi_descriptor;
/*
- * Mendocino DXIO Descriptor: Used for assigning lanes to PCIe engines, configure
+ * Morgana DXIO Descriptor: Used for assigning lanes to PCIe engines, configure
* bifurcation and other settings. Beware that the lane numbers in here are the
* logical and not the physical lane numbers!
*
- * Mendocino DXIO logical lane to physical PCIe lane mapping:
+ * Morgana DXIO logical lane to physical PCIe lane mapping:
*
- * logical | physical
- * --------|------------
- * [00:03] | GPP[03:00]
+ * logical | physical
+ * ----------|------------
+ * PA[00:03] | GPP[03:00]
+ * PA[04:05] | GPP[08:09]
+ * PB[00:07] | GPP[12:19]
*
* Different ports mustn't overlap or be assigned to the same lane(s). Within
* ports with the same width the one with a higher start logical lane number
@@ -183,7 +187,7 @@
uint8_t end_logical_lane; // End lane of the pci device
uint8_t gpio_group_id; // GPIO number used as reset
uint32_t port_present :1; // Should be TRUE if train link
- uint32_t reserved_3 :7;
+ uint32_t :7;
uint32_t device_number :5; // Desired root port device number
uint32_t function_number :3; // Desired root port function number
uint32_t link_speed_capability :2; // See dxio_link_speed_cap
@@ -193,14 +197,14 @@
uint32_t link_aspm_L1_1 :1; // En/Dis root port capabilities for L1.1
uint32_t link_aspm_L1_2 :1; // En/Dis root port capabilities for L1.2
uint32_t clk_req :4; // See cpm_clk_req
- uint8_t link_hotplug; // Currently unused by FSP
- uint8_t slot_power_limit; // Currently unused by FSP
- uint32_t slot_power_limit_scale :2; // Currently unused by FSP
- uint32_t reserved_4 :6;
- uint32_t link_compliance_mode :1; // Currently unused by FSP
- uint32_t link_safe_mode :1; // Currently unused by FSP
- uint32_t sb_link :1; // Currently unused by FSP
- uint32_t clk_pm_support :1; // Currently unused by FSP
+ uint8_t link_hotplug; // Hotplug control
+ uint8_t slot_power_limit; // PCIe slot power limit
+ uint32_t slot_power_limit_scale :2; // PCIe slot power limit scale
+ uint32_t :6;
+ uint32_t link_compliance_mode :1; // Force port into compliance mode
+ uint32_t link_safe_mode :1; // Safe mode capability
+ uint32_t sb_link :1; // Link type
+ uint32_t clk_pm_support :1; // Clock power management support
uint32_t channel_type :3; // See dxio_sata_channel_type
uint32_t turn_off_unused_lanes :1; // Power down lanes if device not present
uint8_t reserved[4];
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Change subject: vc/amd/fsp/morgana/platform_descriptors.h: Update for morgana
......................................................................
Patch Set 2: Code-Review+2
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69749 )
Change subject: mb/google/nissa/var/craask: Disable gpio export in crs for G2 touchscreen
......................................................................
mb/google/nissa/var/craask: Disable gpio export in crs for G2 touchscreen
BUG=b:235919755
Test=Check error message "Exposing GPIOs in Power Resource and _CRS"
not show in firmware log.
Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com>
Change-Id: I21a47adde48555098d041b94d483cad308bdb717
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69749
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Reviewed-by: David Wu <david_wu(a)quanta.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman(a)chromium.org>
---
M src/mainboard/google/brya/variants/craask/overridetree.cb
1 file changed, 20 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
David Wu: Looks good to me, approved
Reka Norman: Looks good to me, approved
Eric Lai: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/craask/overridetree.cb b/src/mainboard/google/brya/variants/craask/overridetree.cb
index 6db23d4..0687bf5 100644
--- a/src/mainboard/google/brya/variants/craask/overridetree.cb
+++ b/src/mainboard/google/brya/variants/craask/overridetree.cb
@@ -202,6 +202,7 @@
register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
register "generic.enable_delay_ms" = "12"
register "generic.has_power_resource" = "1"
+ register "generic.disable_gpio_export_in_crs" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 0x40 on end
end
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69613 )
Change subject: soc/intel/meteorlake: transition full control over PM Timer from FSP to coreboot
......................................................................
soc/intel/meteorlake: transition full control over PM Timer from FSP to coreboot
Set `EnableTcoTimer=1` in order to keep FSP from
1) enabling ACPI Timer emulation in uCode.
2) disabling the PM ACPI Timer.
Both actions are now done in coreboot.
`EnableTcoTimer=1` makes FSP skip these steps in any possible case
including `SkipMpInit=0`, `SkipMpInit=1`, use of the MP PPI or FSP
Multiphase Init. This way full control is left to coreboot.
Port of commit 0e905801f8ff ("soc/intel: transition full control over PM
Timer from FSP to coreboot").
NOTE: This will have a huge power impact when it's enabled. If TCO timer
is disabled, uCode ACPI timer emulation must be enabled, and WDAT table
must not be exposed to the OS.
BUG=none
TEST=Boot to OS on google/rex.
Excerpt from google/rex coreboot log:
[SPEW ] EnableTcoTimer = 1
Signed-off-by: Kapil Porwal <kapilporwal(a)google.com>
Change-Id: I2693f0390e6c9fa92fec366ab87589c3bcea9027
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69613
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Subrata Banik <subratabanik(a)google.com>
---
M src/soc/intel/meteorlake/fsp_params.c
1 file changed, 50 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Subrata Banik: Looks good to me, approved
diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c
index 4429dc0..2e1820e 100644
--- a/src/soc/intel/meteorlake/fsp_params.c
+++ b/src/soc/intel/meteorlake/fsp_params.c
@@ -349,6 +349,19 @@
s_cfg->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER);
}
+static void fill_fsps_pm_timer_params(FSP_S_CONFIG *s_cfg,
+ const struct soc_intel_meteorlake_config *config)
+{
+ /*
+ * Legacy PM ACPI Timer (and TCO Timer)
+ * This *must* be 1 in any case to keep FSP from
+ * 1) enabling PM ACPI Timer emulation in uCode.
+ * 2) disabling the PM ACPI Timer.
+ * We handle both by ourself!
+ */
+ s_cfg->EnableTcoTimer = 1;
+}
+
static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg,
const struct soc_intel_meteorlake_config *config)
{
@@ -429,6 +442,7 @@
fill_fsps_vmd_params,
fill_fsps_tbt_params,
fill_fsps_8254_params,
+ fill_fsps_pm_timer_params,
fill_fsps_pcie_params,
fill_fsps_misc_power_params,
fill_fsps_ufs_params,
--
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