coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: mb/google/rex: Enable TCSS DisplayPort detection at preboot
by Martin L Roth (Code Review) 19 Nov '22

19 Nov '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67742 ) Change subject: mb/google/rex: Enable TCSS DisplayPort detection at preboot ...................................................................... mb/google/rex: Enable TCSS DisplayPort detection at preboot This change enables the DisplayPort detection at preboot for Rex board. BUG=b:247670186 TEST=Built image and validated DisplayPort feature at preboot on Rex. Change-Id: I1a8a13e937c7132696aa39d85c3c6b6fb2dd13a5 Signed-off-by: zhaojohn <john.zhao(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67742 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/rex/Kconfig 1 file changed, 20 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig index 66e3591..0db76ac 100644 --- a/src/mainboard/google/rex/Kconfig +++ b/src/mainboard/google/rex/Kconfig @@ -27,6 +27,7 @@ select BOARD_GOOGLE_REX_COMMON select DRIVERS_INTEL_PMC select DRIVERS_WWAN_FM350GL + select ENABLE_TCSS_DISPLAY_DETECTION if RUN_FSP_GOP select MAINBOARD_HAS_CHROMEOS select MEMORY_SOLDERDOWN select SOC_INTEL_METEORLAKE -- To view, visit https://review.coreboot.org/c/coreboot/+/67742 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a8a13e937c7132696aa39d85c3c6b6fb2dd13a5 Gerrit-Change-Number: 67742 Gerrit-PatchSet: 8 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/common: Fix the TCSS DisplayPort detection flow
by Martin L Roth (Code Review) 19 Nov '22

19 Nov '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69694 ) Change subject: soc/intel/common: Fix the TCSS DisplayPort detection flow ...................................................................... soc/intel/common: Fix the TCSS DisplayPort detection flow After DisplayPort is plugged into type-C port, its hpd signal instantly presents and EC has mux_info for dp and hpd. This change fixes the DP detection flow to avoid the 1 second delay while no DP is connected. If DP is present, there will be requests towards PMC through the sequence of connect, safe mode, dp and hpd mode. BUG=b:247670186 TEST=Built image and validated the DisplayPort preboot feature on Rex. Change-Id: I7cb95ec7fcc7e1a86e86466e6d45390eedcc4531 Signed-off-by: zhaojohn <john.zhao(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69694 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/soc/intel/common/block/tcss/tcss.c 1 file changed, 24 insertions(+), 18 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/soc/intel/common/block/tcss/tcss.c b/src/soc/intel/common/block/tcss/tcss.c index df331c2..b4a5a0e 100644 --- a/src/soc/intel/common/block/tcss/tcss.c +++ b/src/soc/intel/common/block/tcss/tcss.c @@ -202,7 +202,6 @@ req.buf[0] = cmd; return send_pmc_req(HPD_REQ, &req, &rsp, PMC_IPC_HPD_REQ_SIZE); - } static int send_pmc_dp_mode_request(int port, const struct usbc_mux_info *mux_data, @@ -287,7 +286,7 @@ static void tcss_configure_dp_mode(const struct tcss_port_map *port_map, size_t num_ports) { - int ret, port_bitmask; + int ret; size_t i; const struct usbc_ops *ops; struct usbc_mux_info mux_info; @@ -300,24 +299,9 @@ if (ops == NULL) return; - port_bitmask = ops->dp_ops.wait_for_connection(WAIT_FOR_DISPLAYPORT_TIMEOUT_MS); - if (!port_bitmask) /* No DP device is connected */ - return; - for (i = 0; i < num_ports; i++) { - if (!(port_bitmask & BIT(i))) - continue; - - ret = ops->dp_ops.enter_dp_mode(i); - if (ret < 0) - continue; - - ret = ops->dp_ops.wait_for_hpd(i, WAIT_FOR_HPD_TIMEOUT_MS); - if (ret < 0) - continue; - ret = ops->mux_ops.get_mux_info(i, &mux_info); - if (ret < 0) + if ((ret < 0) || (!mux_info.dp)) continue; port_info = &port_map[i]; -- To view, visit https://review.coreboot.org/c/coreboot/+/69694 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cb95ec7fcc7e1a86e86466e6d45390eedcc4531 Gerrit-Change-Number: 69694 Gerrit-PatchSet: 3 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/mendocino: Increase CBFS_MCACHE size
by Martin L Roth (Code Review) 19 Nov '22

19 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Jon Murphy, Fred Reitberger, Karthik Ramasubramanian. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69827 ) Change subject: soc/amd/mendocino: Increase CBFS_MCACHE size ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: I assume that the 4KiB is still large enough to hold everything. -- To view, visit https://review.coreboot.org/c/coreboot/+/69827 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35e1a8c6d73e0870b6a43aac604f83a0b6c3aabe Gerrit-Change-Number: 69827 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Sat, 19 Nov 2022 15:05:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: vboot/vboot_common: Fix vboot_save_data() code exclusion guard
by Yu-Ping Wu (Code Review) 19 Nov '22

19 Nov '22

Attention is currently required from: Jakub Czapiga, Julius Werner. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69761 ) Change subject: vboot/vboot_common: Fix vboot_save_data() code exclusion guard ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69761 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5330efeeb4cfd7477cf8f7f64c6abed68281e30 Gerrit-Change-Number: 69761 Gerrit-PatchSet: 3 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Sat, 19 Nov 2022 14:50:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: [RFC] Pull ligfxinit in early romstage
by Angel Pons (Code Review) 19 Nov '22

19 Nov '22

Attention is currently required from: Nico Huber, Tarun Tuli, Martin L Roth, Jérémy Compostella, Paul Menzel, Andrey Petrov. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69757 ) Change subject: [RFC] Pull ligfxinit in early romstage ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69757/comment/70d26084_0d1092ea PS2, Line 9: The goal is to display a text message while memory training is in : progress. > Isn’t that against the goal of coreboot? On what systems does initializing memory take that long (an […] What is *the* goal of coreboot that this goes against? Homepage says "fast, secure and flexible": we can be fast and flexible by simply making this optional, just like other consoles (flashconsole, EHCI debug, serial port...). And security is something we should always keep in mind no matter what. This option can be extremely useful for debug purposes, as it would allow one to view coreboot logs without having to do anything special. Also, should one implement open-source RAM init, showing fancy margin art would be a nice way to make up for the long training times. (Well, maybe not everyone finds margin diagrams and the like artistic.) -- To view, visit https://review.coreboot.org/c/coreboot/+/69757 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3357e746a7d94afe9d285c36ed6172c7bfd9718 Gerrit-Change-Number: 69757 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Sat, 19 Nov 2022 14:29:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: libpayload: Fix compiler warnings
by Paul Menzel (Code Review) 19 Nov '22

19 Nov '22

Attention is currently required from: Nico Huber, Thomas Heijligen. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69764 ) Change subject: libpayload: Fix compiler warnings ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69764/comment/be51644f_a9665603 PS2, Line 9: drivers/serial/8250.c:75: [-Werror=unused-variable] : Move variable declaration inside the : `#if !CONFIG(LP_PL011_SERIAL_CONSOLE)` block : : drivers/udc/dwc2.c:505: [-Werror=format=] : use `%zd` to match type `size_t` > Next time, it’d be great, if you did two commits with a commit message about the change. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/69764 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id285c24cba790f181fa203f3117e5df35bed27c4 Gerrit-Change-Number: 69764 Gerrit-PatchSet: 2 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Comment-Date: Sat, 19 Nov 2022 13:14:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: libpayload: Fix compiler warnings
by Paul Menzel (Code Review) 19 Nov '22

19 Nov '22

Attention is currently required from: Nico Huber, Thomas Heijligen. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69764 ) Change subject: libpayload: Fix compiler warnings ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/69764/comment/b9cc06db_3155f50d PS2, Line 8: Please mention the compiler. https://review.coreboot.org/c/coreboot/+/69764/comment/343115dd_fdb5a8f5 PS2, Line 9: drivers/serial/8250.c:75: [-Werror=unused-variable] : Move variable declaration inside the : `#if !CONFIG(LP_PL011_SERIAL_CONSOLE)` block : : drivers/udc/dwc2.c:505: [-Werror=format=] : use `%zd` to match type `size_t` Next time, it’d be great, if you did two commits with a commit message about the change. “Fix compiler warnings” is too broad in my opinion, and people have to look at the diff to know what it is about. -- To view, visit https://review.coreboot.org/c/coreboot/+/69764 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id285c24cba790f181fa203f3117e5df35bed27c4 Gerrit-Change-Number: 69764 Gerrit-PatchSet: 2 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Comment-Date: Sat, 19 Nov 2022 13:14:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: crossgcc: Upgrade LLVM from 15.0.0 to 15.0.5
by Paul Menzel (Code Review) 19 Nov '22

19 Nov '22

Attention is currently required from: Martin L Roth, Arthur Heymans, Elyes Haouas. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69700 ) Change subject: crossgcc: Upgrade LLVM from 15.0.0 to 15.0.5 ...................................................................... Patch Set 7: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69700/comment/6d99c4bf_e6bebed1 PS7, Line 8: Did you make a test build of emulation/qemu-i440fx or another board, and compare the generated code? -- To view, visit https://review.coreboot.org/c/coreboot/+/69700 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e6c23c6552eded92e706bc21bb162a66767572e Gerrit-Change-Number: 69700 Gerrit-PatchSet: 7 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sat, 19 Nov 2022 13:13:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: [RFC] Pull ligfxinit in early romstage
by Paul Menzel (Code Review) 19 Nov '22

19 Nov '22

Attention is currently required from: Nico Huber, Tarun Tuli, Martin L Roth, Jérémy Compostella, Angel Pons, Andrey Petrov. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69757 ) Change subject: [RFC] Pull ligfxinit in early romstage ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69757/comment/97c0eccc_8ce1a6b6 PS2, Line 9: The goal is to display a text message while memory training is in : progress. Isn’t that against the goal of coreboot? On what systems does initializing memory take that long (and in subsequent boots the cache should be used). Please start a discussion on the mailing list, if these things are wanted. -- To view, visit https://review.coreboot.org/c/coreboot/+/69757 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3357e746a7d94afe9d285c36ed6172c7bfd9718 Gerrit-Change-Number: 69757 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Sat, 19 Nov 2022 13:11:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: cpu/intel/socket_*: Clean up Kconfig files
by Angel Pons (Code Review) 19 Nov '22

19 Nov '22

Attention is currently required from: Stefan Ott, Nico Huber, Arthur Heymans, Kyösti Mälkki, Alexander Couzens, Elyes Haouas. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69447 ) Change subject: cpu/intel/socket_*: Clean up Kconfig files ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69447/comment/871c8455_72b8c434 PS3, Line 10: Move MAX_CPUS to mainboards. > > The problem with having the defaults for `MAX_CPUS` in `cpu/intel/model_*/Kconfig` is that sockets […] Arthur, the Atom 330 is dual-core, has Hyper-Threading and is paired with the i945 northbridge, which is why `MAX_CPUS` is 4 for i945. See the commit message of CB:41845 and https://www.intel.com/content/www/us/en/products/sku/35641/intel-atom-proce… -- To view, visit https://review.coreboot.org/c/coreboot/+/69447 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2265ac716e90720e7ccc550239737d40c2f7a0a Gerrit-Change-Number: 69447 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sat, 19 Nov 2022 13:06:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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coreboot-gerrit November 2022