coreboot-gerrit October 2022

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[S] Change in coreboot[master]: Makefile.inc: Decrease minimal pagesize from 4 kB to 1 kB
by build bot (Jenkins) (Code Review) 02 Oct '22

02 Oct '22

Attention is currently required from: Martin L Roth, Angel Pons, Julius Werner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62830 ) Change subject: Makefile.inc: Decrease minimal pagesize from 4 kB to 1 kB ...................................................................... Patch Set 2: (4 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159567): https://review.coreboot.org/c/coreboot/+/62830/comment/00e0931d_167c2eb0 PS2, Line 17: In function 'write_ble8', Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159567): https://review.coreboot.org/c/coreboot/+/62830/comment/e3232dd7_bf64b06c PS2, Line 20: inlined from 'setup_ebda' at src/arch/x86/ebda.c:35:2, Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159567): https://review.coreboot.org/c/coreboot/+/62830/comment/b2e416c0_443d6468 PS2, Line 21: inlined from 'setup_default_ebda' at src/arch/x86/ebda.c:48:2: Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159567): https://review.coreboot.org/c/coreboot/+/62830/comment/0fd1ac9d_073c1cf9 PS2, Line 30: pointer arithmetics from NULL while addresses equal or larger than that Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/62830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e36633f42cb4dc5af53212c10c919a86e451ee0 Gerrit-Change-Number: 62830 Gerrit-PatchSet: 2 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Sun, 02 Oct 2022 18:29:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: Makefile.inc: Decrease minimal pagesize from 4 kB to 1 kB
by Paul Menzel (Code Review) 02 Oct '22

02 Oct '22

Attention is currently required from: Paul Menzel, Angel Pons, Julius Werner. Hello build bot (Jenkins), Nico Huber, Angel Pons, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62830 to look at the new patch set (#2). Change subject: Makefile.inc: Decrease minimal pagesize from 4 kB to 1 kB ...................................................................... Makefile.inc: Decrease minimal pagesize from 4 kB to 1 kB GCC 12 incorrectly warns about an array out of bounds issue: ``` $ make V=1 # emulation/qemu-i440fx […] CC ramstage/arch/x86/ebda.o x86_64-linux-gnu-gcc-12 -MMD -Isrc -Isrc/include -Isrc/commonlib/include -Isrc/commonlib/bsd/include -Ibuild -I3rdparty/vboot/firmware/include -include src/include/kconfig.h -include src/include/rules.h -include src/commonlib/bsd/include/commonlib/bsd/compiler.h -I3rdparty -D__BUILD_DIR__=\"build\" -Isrc/arch/x86/include -D__ARCH_x86_32__ -pipe -g -nostdinc -std=gnu11 -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough -Wshadow -Wdate-time -Wtype-limits -Wvla -Wdangling-else -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer -fstrict-aliasing -ffunction-sections -fdata-sections -fno-pie -Wno-packed-not-aligned -fconserve-stack -Wnull-dereference -Wreturn-type -Wlogical-op -Wduplicated-cond -Wno-unused-but-set-variable -Werror -Os -Wno-address-of-packed-member -m32 -Wl,-b,elf32-i386 -Wl,-melf_i386 -m32 -fuse-ld=bfd -fno-stack-protector -Wl,--build-id=none -fno-delete-null-pointer-checks -Wlogical-op -march=i686 -mno-mmx -MT build/ramstage/arch/x86/ebda.o -D__RAMSTAGE__ -c -o build/ramstage/arch/x86/ebda.o src/arch/x86/ebda.c In file included from src/arch/x86/ebda.c:6: In function 'write_ble8', inlined from 'write_le8' at src/commonlib/include/commonlib/endian.h:155:2, inlined from 'write_le16' at src/commonlib/include/commonlib/endian.h:178:2, inlined from 'setup_ebda' at src/arch/x86/ebda.c:35:2, inlined from 'setup_default_ebda' at src/arch/x86/ebda.c:48:2: src/commonlib/include/commonlib/endian.h:27:26: error: array subscript 0 is outside array bounds of 'void[0]' [-Werror=array-bounds] 27 | *(uint8_t *)dest = val; | ~~~~~~~~~~~~~~~~~^~~~~ […] ``` [In GCC 12 the new parameter `min-pagesize` is added and defaults 4 kB.][1] It treats INTEGER_CST addresses smaller than that as assumed results of pointer arithmetics from NULL while addresses equal or larger than that as expected user constant addresses. For GCC 13 we can represent results from pointer arithmetics on NULL using &MEM[(void*)0 + offset] instead of (void*)offset INTEGER_CSTs. [1]: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99578#c36 TEST=No compile error with gcc (Debian 12.2.0-3) 12.2.0 Change-Id: I6e36633f42cb4dc5af53212c10c919a86e451ee0 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M Makefile.inc 1 file changed, 40 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/62830/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e36633f42cb4dc5af53212c10c919a86e451ee0 Gerrit-Change-Number: 62830 Gerrit-PatchSet: 2 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: lib/prog_ops.c: Add <types.h>
by Elyes Haouas (Code Review) 02 Oct '22

02 Oct '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68051 ) Change subject: lib/prog_ops.c: Add <types.h> ...................................................................... lib/prog_ops.c: Add <types.h> Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: Ibacf704d362eecea3f7216ffcb02c2ef6f9a6d8f --- M src/lib/prog_ops.c 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/68051/1 diff --git a/src/lib/prog_ops.c b/src/lib/prog_ops.c index 2b965ed..9aa0b58 100644 --- a/src/lib/prog_ops.c +++ b/src/lib/prog_ops.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <program_loading.h> +#include <types.h> /* For each segment of a program loaded this function is called*/ void prog_segment_loaded(uintptr_t start, size_t size, int flags) -- To view, visit https://review.coreboot.org/c/coreboot/+/68051 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibacf704d362eecea3f7216ffcb02c2ef6f9a6d8f Gerrit-Change-Number: 68051 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: nb/intel/i945/memmap.c: Clean up includes
by Elyes Haouas (Code Review) 02 Oct '22

02 Oct '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68050 ) Change subject: nb/intel/i945/memmap.c: Clean up includes ...................................................................... nb/intel/i945/memmap.c: Clean up includes Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: Ie5d7d1dd446428d12a2f904545682e8fb9cd82f9 --- M src/northbridge/intel/i945/memmap.c 1 file changed, 13 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/68050/1 diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c index 58e29c8..1fa0358 100644 --- a/src/northbridge/intel/i945/memmap.c +++ b/src/northbridge/intel/i945/memmap.c @@ -3,17 +3,16 @@ // Use simple device model for this file even in ramstage #define __SIMPLE_DEVICE__ -#include <device/pci_ops.h> #include <arch/romstage.h> #include <cbmem.h> -#include "i945.h" #include <console/console.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> -#include <program_loading.h> -#include <cpu/intel/smm_reloc.h> +#include <device/pci_ops.h> #include <types.h> +#include "i945.h" + /* Decodes TSEG region size to bytes. */ u32 decode_tseg_size(const u8 esmramc) { -- To view, visit https://review.coreboot.org/c/coreboot/+/68050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie5d7d1dd446428d12a2f904545682e8fb9cd82f9 Gerrit-Change-Number: 68050 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: sb/intel/common/pmbase.c: Clean up includes
by Elyes Haouas (Code Review) 02 Oct '22

02 Oct '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68049 ) Change subject: sb/intel/common/pmbase.c: Clean up includes ...................................................................... sb/intel/common/pmbase.c: Clean up includes Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: Ie23472d45c8232f5c907ec1757a648fa1a27d533 --- M src/southbridge/intel/common/pmbase.c 1 file changed, 13 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/68049/1 diff --git a/src/southbridge/intel/common/pmbase.c b/src/southbridge/intel/common/pmbase.c index d5578fc..2fddfc9 100644 --- a/src/southbridge/intel/common/pmbase.c +++ b/src/southbridge/intel/common/pmbase.c @@ -1,13 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> #include <acpi/acpi.h> #include <arch/io.h> +#include <assert.h> #include <bootmode.h> #include <device/pci_ops.h> -#include <device/device.h> -#include <device/pci.h> -#include <assert.h> +#include <device/pci_type.h> +#include <stdint.h> #include "pmbase.h" #include "pmutil.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/68049 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie23472d45c8232f5c907ec1757a648fa1a27d533 Gerrit-Change-Number: 68049 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: sb/intel/common/rtc.c: Clean up includes
by Elyes Haouas (Code Review) 02 Oct '22

02 Oct '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68048 ) Change subject: sb/intel/common/rtc.c: Clean up includes ...................................................................... sb/intel/common/rtc.c: Clean up includes Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: Ibcd61e44f8e165627851e2c5325985f0765634b6 --- M src/southbridge/intel/common/rtc.c 1 file changed, 14 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/68048/1 diff --git a/src/southbridge/intel/common/rtc.c b/src/southbridge/intel/common/rtc.c index ef30d9a5..933ac63 100644 --- a/src/southbridge/intel/common/rtc.c +++ b/src/southbridge/intel/common/rtc.c @@ -3,11 +3,12 @@ #define __SIMPLE_DEVICE__ #include <console/console.h> -#include <device/pci_def.h> #include <device/pci_ops.h> -#include <security/vboot/vbnv.h> -#include <pc80/mc146818rtc.h> +#include <device/pci_type.h> #include <elog.h> +#include <pc80/mc146818rtc.h> +#include <security/vboot/vbnv.h> + #include "pmutil.h" #include "rtc.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/68048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibcd61e44f8e165627851e2c5325985f0765634b6 Gerrit-Change-Number: 68048 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[XL] Change in coreboot[master]: RFC: Add initial support for the bootguarded framework tigerlake lapt...
by Keith Hui (Code Review) 02 Oct '22

02 Oct '22

Attention is currently required from: Felix Singer, Jonathan Neuschäfer, Mimoja, Christoph Pomaska. Keith Hui has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62569 ) Change subject: RFC: Add initial support for the bootguarded framework tigerlake laptop (hx20) ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: Framework is launching a Chromebook edition: https://frame.work/ca/en/laptop-chromebook-12-gen-intel If this chromebook is like others we've seen in-tree, I expect some code drops here that should help this project along. I also expect minimal hardware differences if any between this and the standard versions. Also, in the description is this gem: "Since the Framework Laptop Chromebook Edition chassis is compatible with Framework Laptop Mainboards, there is always an upgrade path available if you want to move to a different OS or processor in the future." To me, it implies moving from ChromeOS to anything else requires mainboard replacement. Your being provided a bootguard-free unit also means a bootguard-free mainboard can be offered as a DIY option. I expect anyone choosing this option would run Linux and not care whether TPM works or not, or if Windows 11 would install. The same Framework chassis can then carry 3 types of mainboards: Standard board for Windows 11, ChromeOS board, Bootguard-free board for coreboot+whatever (presumably without vPro). In my opinion, if this code can completely boot the hardware to Linux login prompt minus bootguard, take it. Add a disclaimer. Leave FOSS purism to libreboot. If you have a channel open with Framework, please advocate for bootguard-free mainboard option. My perfect laptop is a Framework convertible tablet that can run coreboot. I'm still waiting while hanging on to my X230 Tablet, which is a "close" second. -- To view, visit https://review.coreboot.org/c/coreboot/+/62569 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifaf215cccae8836d691392e3e584f49f675f8456 Gerrit-Change-Number: 62569 Gerrit-PatchSet: 6 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Christoph Pomaska <github(a)slrie.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Attention: Mimoja <coreboot(a)mimoja.de> Gerrit-Attention: Christoph Pomaska <github(a)slrie.de> Gerrit-Comment-Date: Sun, 02 Oct 2022 17:52:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: console/console.c: Sort includes and add <types.h>
by Elyes Haouas (Code Review) 02 Oct '22

02 Oct '22

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68035 to look at the new patch set (#2). Change subject: console/console.c: Sort includes and add <types.h> ...................................................................... console/console.c: Sort includes and add <types.h> Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: I1d2d85ff8cfca58295117b5cb625cadfc9008311 --- M src/console/console.c 1 file changed, 15 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/68035/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68035 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d2d85ff8cfca58295117b5cb625cadfc9008311 Gerrit-Change-Number: 68035 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: nb/intel/i945/rcven.c: Sort includes and add <stdint.h>
by Elyes Haouas (Code Review) 02 Oct '22

02 Oct '22

Attention is currently required from: Paul Menzel. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68045 ) Change subject: nb/intel/i945/rcven.c: Sort includes and add <stdint.h> ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/68045/comment/90a2d921_54cb9451 PS1, Line 7: Sorte > Sort […] Thank you Paul -- To view, visit https://review.coreboot.org/c/coreboot/+/68045 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I360e4f8ed3b87225a09c7cbb761c570a579771cf Gerrit-Change-Number: 68045 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sun, 02 Oct 2022 12:35:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: nb/intel/i945/rcven.c: Sort includes and add <stdint.h>
by Elyes Haouas (Code Review) 02 Oct '22

02 Oct '22

Attention is currently required from: Elyes Haouas. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68045 to look at the new patch set (#2). Change subject: nb/intel/i945/rcven.c: Sort includes and add <stdint.h> ...................................................................... nb/intel/i945/rcven.c: Sort includes and add <stdint.h> Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: I360e4f8ed3b87225a09c7cbb761c570a579771cf --- M src/northbridge/intel/i945/rcven.c 1 file changed, 13 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/68045/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68045 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I360e4f8ed3b87225a09c7cbb761c570a579771cf Gerrit-Change-Number: 68045 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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coreboot-gerrit October 2022