coreboot-gerrit October 2022

coreboot-gerrit@coreboot.org

1 participants
5881 discussions

[S] Change in coreboot[master]: cpu/x86/smm/smm_module_loader.c: Clean*up includes
by Elyes Haouas (Code Review) 02 Oct '22

02 Oct '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68032 ) Change subject: cpu/x86/smm/smm_module_loader.c: Clean*up includes ...................................................................... cpu/x86/smm/smm_module_loader.c: Clean*up includes Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: I36c54e62797e67c1732f8deaf8843daf35610e22 --- M src/cpu/x86/smm/smm_module_loader.c 1 file changed, 11 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/68032/1 diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 0555424..71d49ab 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include "assert.h" #include <acpi/acpi_gnvs.h> #include <cbmem.h> #include <commonlib/helpers.h> @@ -8,12 +7,9 @@ #include <console/console.h> #include <cpu/x86/smm.h> #include <rmodule.h> -#include <security/intel/stm/SmmStm.h> -#include <stddef.h> -#include <stdint.h> #include <stdio.h> -#include <stdlib.h> #include <string.h> +#include <types.h> #define FXSAVE_SIZE 512 #define SMM_CODE_SEGMENT_SIZE 0x10000 -- To view, visit https://review.coreboot.org/c/coreboot/+/68032 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36c54e62797e67c1732f8deaf8843daf35610e22 Gerrit-Change-Number: 68032 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: cpu/x86/mtrr/mtrr.c: Add missing <stdbool.h>
by Elyes Haouas (Code Review) 02 Oct '22

02 Oct '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68031 ) Change subject: cpu/x86/mtrr/mtrr.c: Add missing <stdbool.h> ...................................................................... cpu/x86/mtrr/mtrr.c: Add missing <stdbool.h> Remove <stdint.h>, <stddef.h> and add <stdbool.h>. All of them are included through <types.h>. Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: If5296988c68302896e3676d7b80d0f133d5d4264 --- M src/cpu/x86/mtrr/mtrr.c 1 file changed, 21 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/68031/1 diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 41164bb..5f7535f 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -8,21 +8,21 @@ * Programming */ -#include <stddef.h> -#include <stdint.h> -#include <string.h> +#include <assert.h> #include <bootstate.h> #include <commonlib/helpers.h> #include <console/console.h> -#include <device/device.h> -#include <device/pci_ids.h> +#include <cpu/amd/mtrr.h> #include <cpu/cpu.h> +#include <cpu/x86/cache.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> -#include <cpu/x86/cache.h> +#include <device/device.h> +#include <device/pci_ids.h> #include <memrange.h> -#include <cpu/amd/mtrr.h> -#include <assert.h> +#include <string.h> +#include <types.h> + #if CONFIG(X86_AMD_FIXED_MTRRS) #define MTRR_FIXED_WRBACK_BITS (MTRR_READ_MEM | MTRR_WRITE_MEM) #else -- To view, visit https://review.coreboot.org/c/coreboot/+/68031 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5296988c68302896e3676d7b80d0f133d5d4264 Gerrit-Change-Number: 68031 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 0

[S] Change in libgfxinit[master]: hw-gfx-dp_training.adb: Fix `EQ_Delay` function
by Nico Huber (Code Review) 01 Oct '22

01 Oct '22

Attention is currently required from: Angel Pons. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/67447 ) Change subject: hw-gfx-dp_training.adb: Fix `EQ_Delay` function ...................................................................... Patch Set 1: Verified+1 Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/libgfxinit/+/67447/comment/e6911afa_b4db1a51 PS1, Line 7: hw-gfx-dp_training.adb Just noticed, we usually don't do file names, something like `dp training:` should suffice. -- To view, visit https://review.coreboot.org/c/libgfxinit/+/67447 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I18d118ff1bf013175290a1c9fba4d449c7b00cb4 Gerrit-Change-Number: 67447 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sat, 01 Oct 2022 14:06:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in libgfxinit[master]: hw-gfx-dp_info.adb: Fix reading `Aux_RD_Interval`
by Nico Huber (Code Review) 01 Oct '22

01 Oct '22

Nico Huber has submitted this change. ( https://review.coreboot.org/c/libgfxinit/+/67445 ) Change subject: hw-gfx-dp_info.adb: Fix reading `Aux_RD_Interval` ...................................................................... hw-gfx-dp_info.adb: Fix reading `Aux_RD_Interval` Starting with DP v1.4, the definition of DPCD address 0xe was updated to include a new field. Bit 7 now indicates whether a DP receiver has an Extended Receiver Capability field, so `Aux_RD_Interval` is now in bits 6:0. This change is backwards compatible with older hardware, as the defined values for `Aux_RD_Interval` range from 0 to 4, and bit 7 is always zero. However, libgfxinit does not make sure the value is valid before using it in calculations, so the `EQ_Delay` function may return an extremely large value if bit 7 is set. To avoid this, add some masks to properly obtain the value for `Aux_RD_Interval`. Change-Id: If22d8dbc0517daeaa043ede30bf69e7a65ab154b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/libgfxinit/+/67445 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Tim Wawrzynczak <inforichland(a)gmail.com> Tested-by: Nico Huber <nico.h(a)gmx.de> --- M common/hw-gfx-dp_info.adb 1 file changed, 28 insertions(+), 2 deletions(-) Approvals: Nico Huber: Verified; Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/common/hw-gfx-dp_info.adb b/common/hw-gfx-dp_info.adb index bf09933..392fee1 100644 --- a/common/hw-gfx-dp_info.adb +++ b/common/hw-gfx-dp_info.adb @@ -72,7 +72,7 @@ Link.Receiver_Caps.TPS3_Supported := (Data (2) and 16#40#) /= 0; Link.Receiver_Caps.Enhanced_Framing := (Data (2) and 16#80#) /= 0; Link.Receiver_Caps.No_Aux_Handshake := (Data (3) and 16#40#) /= 0; - Link.Receiver_Caps.Aux_RD_Interval := Data (14); + Link.Receiver_Caps.Aux_RD_Interval := Data (14) and 16#7f#; pragma Debug (Debug.New_Line); pragma Debug (Debug.Put_Line ("DPCD:")); @@ -82,7 +82,7 @@ pragma Debug (Debug.Put_Reg8 (" TPS3_Supported ", Data (2) and 16#40#)); pragma Debug (Debug.Put_Reg8 (" Enhanced_Framing", Data (2) and 16#80#)); pragma Debug (Debug.Put_Reg8 (" No_Aux_Handshake", Data (3) and 16#40#)); - pragma Debug (Debug.Put_Reg8 (" Aux_RD_Interval ", Data (14))); + pragma Debug (Debug.Put_Reg8 (" Aux_RD_Interval ", Data (14) and 16#7f#)); pragma Debug (Debug.New_Line); end if; end Read_Caps; -- To view, visit https://review.coreboot.org/c/libgfxinit/+/67445 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: If22d8dbc0517daeaa043ede30bf69e7a65ab154b Gerrit-Change-Number: 67445 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-MessageType: merged

1 0

[S] Change in libgfxinit[master]: hw-gfx-dp_info.adb: Fix reading `Aux_RD_Interval`
by Nico Huber (Code Review) 01 Oct '22

01 Oct '22

Attention is currently required from: Angel Pons. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/67445 ) Change subject: hw-gfx-dp_info.adb: Fix reading `Aux_RD_Interval` ...................................................................... Patch Set 1: Verified+1 -- To view, visit https://review.coreboot.org/c/libgfxinit/+/67445 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: If22d8dbc0517daeaa043ede30bf69e7a65ab154b Gerrit-Change-Number: 67445 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sat, 01 Oct 2022 13:52:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: mb/google/brya: Update entries for UFC to support IMX208
by Varshit Pandya (Code Review) 01 Oct '22

01 Oct '22

Varshit Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56621 ) Change subject: mb/google/brya: Update entries for UFC to support IMX208 ...................................................................... Patch Set 11: (1 comment) Patchset: PS11: > Hi, […] Hello Nick, Back when this patch was pushed, it was decided that there wont be support for any version of brya hardware before P2. Since this was confirmed I had pushed this patch. If I recall correctly along with this, there were I2C changes related to TPM which had corresponding support in depthcharge which made hardware before P2 not bootable in payload phase. If you are adding support for old brya hardware back, you might want to redo the depthcharge part based on some board/sku id. Thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/56621 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a3bf13ec844fb46e11ce58382057fcc7187c135 Gerrit-Change-Number: 56621 Gerrit-PatchSet: 11 Gerrit-Owner: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Maulik Vaghela <maulikvaghela(a)google.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sat, 01 Oct 2022 09:11:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/intel/alderlake: Fix unknown upgrade in SMBIOS
by Elyes Haouas (Code Review) 01 Oct '22

01 Oct '22

Attention is currently required from: Zhixing Ma, Bora Guvendik, Jérémy Compostella, Nick Vaccaro. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68024 ) Change subject: soc/intel/alderlake: Fix unknown upgrade in SMBIOS ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/68024/comment/903a846c_a2c6989a PS1, Line 7: soc/intel/alderlake: Fix unknown upgrade in SMBIOS arch/x86/smbios.c: Upgrade processor information in SMBIOS ? File src/arch/x86/smbios.c: https://review.coreboot.org/c/coreboot/+/68024/comment/c7ee06a9_4a0ce7ee PS1, Line 391: SOC_INTEL_ALDERLAKE) and SOC_INTEL_RAPTORLAKE ? -- To view, visit https://review.coreboot.org/c/coreboot/+/68024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5796d31fa2d31b17afa5eddde0799b0f68d69909 Gerrit-Change-Number: 68024 Gerrit-PatchSet: 1 Gerrit-Owner: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Sat, 01 Oct 2022 07:26:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/brya/var/brya0: add new THERMAL FW_CONFIG field
by YH Lin (Code Review) 01 Oct '22

01 Oct '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Tim Wawrzynczak, Nick Vaccaro. YH Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68025 ) Change subject: mb/google/brya/var/brya0: add new THERMAL FW_CONFIG field ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/68025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba3bd87abd4c112ceff4bbe51a7cf9eae3a694f2 Gerrit-Change-Number: 68025 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Sat, 01 Oct 2022 00:45:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mrc_cache: Update metadata signature
by Felix Held (Code Review) 01 Oct '22

01 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68012 ) Change subject: mrc_cache: Update metadata signature ...................................................................... mrc_cache: Update metadata signature CB:67670 recently changed the format of the MRC metadata header, but left the signature the same. That kinda defeats the purpose of having a signature which is to make a data structure recognizable (because now the same signature can refer to two different structures that cannot be otherwise distinguished). While we don't know of any use case where anything other than coreboot currently parses this data structure (other than a ChromeOS-internal utility that's about to be removed), it's probably better to still switch to a different signature for the new header format just to stay on the safe side (e.g. if we ever need to start parsing this somewhere else in the future). CB:67670 only landed a week ago so hopefully the old signature + new format variant hasn't had much time to escape into the wild yet. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: Ic08b23862720db832a08dc4c6818894492f43cc3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68012 Reviewed-by: Reka Norman <rekanorman(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/mrc_cache/mrc_cache.c 1 file changed, 29 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Reka Norman: Looks good to me, approved diff --git a/src/drivers/mrc_cache/mrc_cache.c b/src/drivers/mrc_cache/mrc_cache.c index 2800c90..fd3853f 100644 --- a/src/drivers/mrc_cache/mrc_cache.c +++ b/src/drivers/mrc_cache/mrc_cache.c @@ -22,7 +22,8 @@ #define RECOVERY_MRC_CACHE "RECOVERY_MRC_CACHE" #define UNIFIED_MRC_CACHE "UNIFIED_MRC_CACHE" -#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) +/* Signature "MRCD" was used for older header format before CB:67670. */ +#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('d'<<24)) struct mrc_metadata { uint32_t signature; -- To view, visit https://review.coreboot.org/c/coreboot/+/68012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic08b23862720db832a08dc4c6818894492f43cc3 Gerrit-Change-Number: 68012 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: soc/nvidia/tegra124/sor.c: Remove trailing semicolon
by 9elements QA (Code Review) 01 Oct '22

01 Oct '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67968 ) Change subject: soc/nvidia/tegra124/sor.c: Remove trailing semicolon ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/125563 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/125562 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/125561 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/125560 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/125559 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/125558 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/125557 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/125556 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/125555 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/125554 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/125553 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/125552 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/125551 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/125550 FAIL: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/125549 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/125548 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/67968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9563a7f6d37937a4951c5053dcfee140579098e8 Gerrit-Change-Number: 67968 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Sat, 01 Oct 2022 00:35:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2022