coreboot-gerrit October 2022

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: mb/google/nissa/var/xivu: Change TPM I2C freqeuncy to 1 MHz
by Ian Feng (Code Review) 03 Oct '22

03 Oct '22

Ian Feng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68071 ) Change subject: mb/google/nissa/var/xivu: Change TPM I2C freqeuncy to 1 MHz ...................................................................... mb/google/nissa/var/xivu: Change TPM I2C freqeuncy to 1 MHz Change the TPM I2C freqeuncy to 1 MHz for xivu. BUG=b:249953477 TEST=On xivu, all timing requirements in the spec are met. Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Change-Id: I33f712c14978b95f3a4da82d6f1f5fbae1283b17 --- M src/mainboard/google/brya/variants/xivu/overridetree.cb 1 file changed, 27 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/68071/1 diff --git a/src/mainboard/google/brya/variants/xivu/overridetree.cb b/src/mainboard/google/brya/variants/xivu/overridetree.cb index f919cef..03203b0 100644 --- a/src/mainboard/google/brya/variants/xivu/overridetree.cb +++ b/src/mainboard/google/brya/variants/xivu/overridetree.cb @@ -41,6 +41,19 @@ #| I2C3 | Audio | #| I2C5 | Trackpad | #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .early_init = 1, + .speed = I2C_SPEED_FAST_PLUS, + .speed_config[0] = { + .speed = I2C_SPEED_FAST_PLUS, + .scl_lcnt = 55, + .scl_hcnt = 30, + .sda_hold = 7, + } + }, + }" + device domain 0 on device ref dtt on chip drivers/intel/dptf -- To view, visit https://review.coreboot.org/c/coreboot/+/68071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33f712c14978b95f3a4da82d6f1f5fbae1283b17 Gerrit-Change-Number: 68071 Gerrit-PatchSet: 1 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/skyrim: Adjust Makefile to look for SPD
by Martin L Roth (Code Review) 03 Oct '22

03 Oct '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68018 ) ( 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/skyrim: Adjust Makefile to look for SPD ...................................................................... mb/google/skyrim: Adjust Makefile to look for SPD Adjust the Makefile to look for SPD source Makefile. The current SPD guard isn't set up correctly and is attempting to build the APCB with SPD when SPD isn't present. BUG=b:249988439 TEST=util/abuild/abuild -x -t GOOGLE_MORTHAL --verbose util/abuild/abuild -x -t GOOGLE_SKYRIM --verbose util/abuild/abuild -x -t GOOGLE_WINTERHOLD --verbose Change-Id: I9cf13acb1188309ea6a1e6bdacc37d80b01f70a8 Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68018 Reviewed-by: Robert Zieba <robertzieba(a)google.com> Reviewed-by: Tim Van Patten <timvp(a)google.com> Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/skyrim/Makefile.inc 1 file changed, 25 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Robert Zieba: Looks good to me, but someone else must approve Tim Van Patten: Looks good to me, but someone else must approve Martin Roth: Looks good to me, approved diff --git a/src/mainboard/google/skyrim/Makefile.inc b/src/mainboard/google/skyrim/Makefile.inc index 869916e..ba175a2 100644 --- a/src/mainboard/google/skyrim/Makefile.inc +++ b/src/mainboard/google/skyrim/Makefile.inc @@ -19,7 +19,7 @@ ifneq ($(wildcard $(MAINBOARD_BLOBS_DIR)/APCB_MDN_D5.bin),) $(info APCB sources present.) -ifneq ($(wildcard $(top)/$(SPD_SOURCES)),) +ifneq ($(wildcard $(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/memory/Makefile.inc),) LIB_SPD_DEPS = $(SPD_SOURCES) -- To view, visit https://review.coreboot.org/c/coreboot/+/68018 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cf13acb1188309ea6a1e6bdacc37d80b01f70a8 Gerrit-Change-Number: 68018 Gerrit-PatchSet: 6 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/brya/var/skolas: Add new FW_CONFIG option for THERMAL
by AlanKY Lee (Code Review) 03 Oct '22

03 Oct '22

AlanKY Lee has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/67718 ) Change subject: mb/google/brya/var/skolas: Add new FW_CONFIG option for THERMAL ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/67718 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cb8982e96ebb5a4f229343c67555fc25cab74b7 Gerrit-Change-Number: 67718 Gerrit-PatchSet: 7 Gerrit-Owner: AlanKY Lee <alanky_lee(a)compal.corp-partner.google.com> Gerrit-Reviewer: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[S] Change in coreboot[master]: mb/google/brya/var/skolas: Add new FW_CONFIG option for THERMAL
by AlanKY Lee (Code Review) 03 Oct '22

03 Oct '22

Attention is currently required from: Frank Wu, Tim Wawrzynczak, Sumeet R Pawnikar, Amanda Hwang. AlanKY Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67718 ) Change subject: mb/google/brya/var/skolas: Add new FW_CONFIG option for THERMAL ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: Abandoned. Duplicated with 68025. -- To view, visit https://review.coreboot.org/c/coreboot/+/67718 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cb8982e96ebb5a4f229343c67555fc25cab74b7 Gerrit-Change-Number: 67718 Gerrit-PatchSet: 7 Gerrit-Owner: AlanKY Lee <alanky_lee(a)compal.corp-partner.google.com> Gerrit-Reviewer: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Mon, 03 Oct 2022 02:15:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/var/skolas: Add new FW_CONFIG option for THERMAL
by AlanKY Lee (Code Review) 03 Oct '22

03 Oct '22

Attention is currently required from: Frank Wu, Tim Wawrzynczak, Sumeet R Pawnikar, Amanda Hwang, AlanKY Lee. Hello Frank Wu, YH Lin, Tim Wawrzynczak, Nick Vaccaro, Amanda Hwang, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/67718 to look at the new patch set (#7). Change subject: mb/google/brya/var/skolas: Add new FW_CONFIG option for THERMAL ...................................................................... mb/google/brya/var/skolas: Add new FW_CONFIG option for THERMAL Add the new option for CPU 15W and 28W, for different thermal settings. 0: SOC_28W 1: SOC_15W BUG=b:250089101 BRANCH=firmware-brya-14505.B TEST=FW_NAME="skolas" emerge-brya coreboot Signed-off-by: AlanKY Lee <alanky_lee(a)compal.corp-partner.google.com> Change-Id: I6cb8982e96ebb5a4f229343c67555fc25cab74b7 --- M src/mainboard/google/brya/variants/skolas/overridetree.cb 1 file changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/67718/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/67718 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cb8982e96ebb5a4f229343c67555fc25cab74b7 Gerrit-Change-Number: 67718 Gerrit-PatchSet: 7 Gerrit-Owner: AlanKY Lee <alanky_lee(a)compal.corp-partner.google.com> Gerrit-Reviewer: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Attention: AlanKY Lee <alanky_lee(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/brya/var/skolas: Add new FW_CONFIG option for THERMAL
by AlanKY Lee (Code Review) 03 Oct '22

03 Oct '22

Attention is currently required from: Frank Wu, Tim Wawrzynczak, Sumeet R Pawnikar, Amanda Hwang, AlanKY Lee. Hello Frank Wu, YH Lin, Tim Wawrzynczak, Nick Vaccaro, Amanda Hwang, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/67718 to look at the new patch set (#6). Change subject: mb/google/brya/var/skolas: Add new FW_CONFIG option for THERMAL ...................................................................... mb/google/brya/var/skolas: Add new FW_CONFIG option for THERMAL Add the new option for CPU 15W and 28W, for different thermal settings. 0: SOC_28W 1: SOC_15W BUG=b:250089101 BRANCH=firmware-brya-14505.B TEST=FW_NAME="skolas" emerge-brya coreboot Signed-off-by: AlanKY Lee <alanky_lee(a)compal.corp-partner.google.com> Change-Id: I6cb8982e96ebb5a4f229343c67555fc25cab74b7 --- M src/mainboard/google/brya/variants/skolas/overridetree.cb 1 file changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/67718/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/67718 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cb8982e96ebb5a4f229343c67555fc25cab74b7 Gerrit-Change-Number: 67718 Gerrit-PatchSet: 6 Gerrit-Owner: AlanKY Lee <alanky_lee(a)compal.corp-partner.google.com> Gerrit-Reviewer: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Attention: AlanKY Lee <alanky_lee(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/skyrim: Enable amdfw separation
by Martin Roth (Code Review) 03 Oct '22

03 Oct '22

Attention is currently required from: Robert Zieba, Raul Rangel, Jason Nien, Tim Van Patten, Karthik Ramasubramanian. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67261 ) Change subject: mb/google/skyrim: Enable amdfw separation ...................................................................... Patch Set 14: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/67261/comment/6ed26683_77641c86 PS14, Line 17: Before this patch series: > Possible unwrapped commit description (prefer a maximum 72 chars per line) Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/67261 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78ec6d28b4c5fc40bdade47489d58180a54dee4d Gerrit-Change-Number: 67261 Gerrit-PatchSet: 14 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Sun, 02 Oct 2022 22:16:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/(common,mendocino)/psp_verstage: Pass PSP FW hash table
by Martin Roth (Code Review) 03 Oct '22

03 Oct '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60291 ) ( 14 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/amd/(common,mendocino)/psp_verstage: Pass PSP FW hash table ...................................................................... soc/amd/(common,mendocino)/psp_verstage: Pass PSP FW hash table Copy AMD PSP fw hash table into memory, then pass it to the PSP. The PSP will use this hash to verify it's the correct firmware bundled with coreboot build and not replaced. BUG=b:203597980 TEST=Build Skyrim BIOS image with the hash table and boot to OS after PSP verified the binaries against the hash table. Change-Id: I84bea97c89620d0388b27891a898ffde77052239 Signed-off-by: Kangheui Won <khwon(a)chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60291 Reviewed-by: Tim Van Patten <timvp(a)google.com> Reviewed-by: Jon Murphy <jpmurphy(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/psp_verstage/include/psp_verstage.h M src/soc/amd/common/psp_verstage/psp_verstage.c M src/soc/amd/mendocino/psp_verstage/chipset.c 3 files changed, 89 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Jon Murphy: Looks good to me, approved Tim Van Patten: Looks good to me, but someone else must approve diff --git a/src/soc/amd/common/psp_verstage/include/psp_verstage.h b/src/soc/amd/common/psp_verstage/include/psp_verstage.h index 3b524c3..e740332 100644 --- a/src/soc/amd/common/psp_verstage/include/psp_verstage.h +++ b/src/soc/amd/common/psp_verstage/include/psp_verstage.h @@ -66,4 +66,6 @@ struct sha_generic_data *sha_op); void platform_report_mode(int developer_mode_enabled); +void update_psp_fw_hash_table(const char *fname); + #endif /* PSP_VERSTAGE_H */ diff --git a/src/soc/amd/common/psp_verstage/psp_verstage.c b/src/soc/amd/common/psp_verstage/psp_verstage.c index b928a27..0dc3314 100644 --- a/src/soc/amd/common/psp_verstage/psp_verstage.c +++ b/src/soc/amd/common/psp_verstage/psp_verstage.c @@ -74,6 +74,7 @@ uint32_t psp_dir_addr, bios_dir_addr; uint32_t *psp_dir_in_spi, *bios_dir_in_spi; const char *fname; + const char *hash_fname; void *amdfw_location; void *boot_dev_base = rdev_mmap_full(boot_device_ro()); @@ -85,8 +86,10 @@ if (vboot_is_firmware_slot_a(ctx)) { fname = "apu/amdfw_a"; + hash_fname = "apu/amdfw_a_hash"; } else { fname = "apu/amdfw_b"; + hash_fname = "apu/amdfw_b_hash"; } amdfw_location = cbfs_map(fname, NULL); @@ -130,6 +133,9 @@ return POSTCODE_UPDATE_PSP_BIOS_DIR_ERROR; } + if (CONFIG(SEPARATE_SIGNED_PSPFW)) + update_psp_fw_hash_table(hash_fname); + return 0; } diff --git a/src/soc/amd/mendocino/psp_verstage/chipset.c b/src/soc/amd/mendocino/psp_verstage/chipset.c index d4a33f0..b896279 100644 --- a/src/soc/amd/mendocino/psp_verstage/chipset.c +++ b/src/soc/amd/mendocino/psp_verstage/chipset.c @@ -3,9 +3,67 @@ /* TODO: Check if this is still correct */ #include <bl_uapp/bl_syscall_public.h> +#include <cbfs.h> #include <console/console.h> #include <psp_verstage.h> +/* + * We can't pass pointer to hash table in the SPI. + * The AMD PSP team specifically required that whole hash table + * should be copied into memory before passing them to the PSP + * to reduce window of TOCTOU. + */ +#define MAX_NUM_HASH_ENTRIES 128 +static struct psp_fw_hash_table hash_table; +static struct psp_fw_entry_hash_256 hash_256[MAX_NUM_HASH_ENTRIES]; +static struct psp_fw_entry_hash_384 hash_384[MAX_NUM_HASH_ENTRIES]; + +void update_psp_fw_hash_table(const char *fname) +{ + uint8_t *spi_ptr = (uint8_t *)cbfs_map(fname, NULL); + uint32_t len; + + if (!spi_ptr) { + printk(BIOS_ERR, "Error: AMD Firmware hash table %s not found\n", fname); + /* + * If we don't supply hash table, the PSP will refuse to boot. + * So returning here is safe to do. + */ + return; + } + + memcpy(&hash_table, spi_ptr, offsetof(struct psp_fw_hash_table, fw_hash_256)); + + if (hash_table.no_of_entries_256 > MAX_NUM_HASH_ENTRIES || + hash_table.no_of_entries_384 > MAX_NUM_HASH_ENTRIES) { + printk(BIOS_ERR, "Error: Too many entries in AMD Firmware hash table" + " (SHA256:%d, SHA384:%d)\n", + hash_table.no_of_entries_256, hash_table.no_of_entries_384); + return; + } + + if (hash_table.no_of_entries_256 == 0 && + hash_table.no_of_entries_384 == 0) { + printk(BIOS_ERR, "Error: No entries in AMD Firmware hash table" + " (SHA256:%d, SHA384:%d)\n", + hash_table.no_of_entries_256, hash_table.no_of_entries_384); + return; + } + + spi_ptr += offsetof(struct psp_fw_hash_table, fw_hash_256); + + hash_table.fw_hash_256 = hash_256; + hash_table.fw_hash_384 = hash_384; + len = sizeof(struct psp_fw_entry_hash_256) * hash_table.no_of_entries_256; + memcpy(hash_256, spi_ptr, len); + + spi_ptr += len; + len = sizeof(struct psp_fw_entry_hash_384) * hash_table.no_of_entries_384; + memcpy(hash_384, spi_ptr, len); + + svc_set_fw_hash_table(&hash_table); +} + uint32_t update_psp_bios_dir(uint32_t *psp_dir_offset, uint32_t *bios_dir_offset) { return svc_update_psp_bios_dir(psp_dir_offset, bios_dir_offset); -- To view, visit https://review.coreboot.org/c/coreboot/+/60291 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84bea97c89620d0388b27891a898ffde77052239 Gerrit-Change-Number: 60291 Gerrit-PatchSet: 16 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/amd/mendocino: Add build rules to separate signed PSP/AMDFW
by Martin Roth (Code Review) 03 Oct '22

03 Oct '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67260 ) ( 13 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/amd/mendocino: Add build rules to separate signed PSP/AMDFW ...................................................................... soc/amd/mendocino: Add build rules to separate signed PSP/AMDFW Add build rules to separate signed PSP/AMDFW. Also add build rules to add the generated hash table containing SHA digest of individual PSP FW components into CBFS. This will allow verified boot to load and verify less components from SPI rom which means faster boot time. BUG=b:206909680 TEST=Build Skyrim with modified fmap and Kconfig Change-Id: If54504add72b30805b6874bee562e0b9482782b9 Signed-off-by: Kangheui Won <khwon(a)chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67260 Reviewed-by: Jon Murphy <jpmurphy(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/mendocino/Makefile.inc 1 file changed, 53 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Jon Murphy: Looks good to me, approved diff --git a/src/soc/amd/mendocino/Makefile.inc b/src/soc/amd/mendocino/Makefile.inc index bdc1a7a..f8aa96f 100644 --- a/src/soc/amd/mendocino/Makefile.inc +++ b/src/soc/amd/mendocino/Makefile.inc @@ -161,6 +161,17 @@ PSP_VERSTAGE_SIG_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_SIGNING_TOKEN)) endif # CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK +ifeq ($(CONFIG_SEPARATE_SIGNED_PSPFW),y) +SIGNED_AMDFW_A_POSITION=$(call int-subtract, \ + $(shell awk '$$2 == "FMAP_SECTION_SIGNED_AMDFW_A_START" {print $$3}' $(obj)/fmap_config.h) \ + $(shell awk '$$2 == "FMAP_SECTION_FLASH_START" {print $$3}' $(obj)/fmap_config.h)) +SIGNED_AMDFW_B_POSITION=$(call int-subtract, \ + $(shell awk '$$2 == "FMAP_SECTION_SIGNED_AMDFW_B_START" {print $$3}' $(obj)/fmap_config.h) \ + $(shell awk '$$2 == "FMAP_SECTION_FLASH_START" {print $$3}' $(obj)/fmap_config.h)) +SIGNED_AMDFW_A_FILE=$(obj)/amdfw_a.rom.signed +SIGNED_AMDFW_B_FILE=$(obj)/amdfw_b.rom.signed +endif # CONFIG_SEPARATE_SIGNED_PSPFW + # Helper function to return a value with given bit set # Soft Fuse type = 0xb - See #55758 (NDA) for bit definitions. set-bit=$(call int-shift-left, 1 $(call _toint,$1)) @@ -194,6 +205,11 @@ OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed) OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag) +OPT_SIGNED_AMDFW_A_POSITION=$(call add_opt_prefix, $(SIGNED_AMDFW_A_POSITION), --signed-addr) +OPT_SIGNED_AMDFW_A_FILE=$(call add_opt_prefix, $(SIGNED_AMDFW_A_FILE), --signed-output) +OPT_SIGNED_AMDFW_B_POSITION=$(call add_opt_prefix, $(SIGNED_AMDFW_B_POSITION), --signed-addr) +OPT_SIGNED_AMDFW_B_FILE=$(call add_opt_prefix, $(SIGNED_AMDFW_B_FILE), --signed-output) + OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) @@ -260,6 +276,8 @@ $(OPT_APOB_NV_SIZE) \ $(OPT_APOB_NV_BASE) \ $(OPT_SPL_RW_AB_TABLE_FILE) \ + $(OPT_SIGNED_AMDFW_A_POSITION) \ + $(OPT_SIGNED_AMDFW_A_FILE) \ --location $(shell printf "%#x" $(MENDOCINO_FW_A_POSITION)) \ --anywhere \ --output $@ @@ -272,6 +290,8 @@ $(OPT_APOB_NV_SIZE) \ $(OPT_APOB_NV_BASE) \ $(OPT_SPL_RW_AB_TABLE_FILE) \ + $(OPT_SIGNED_AMDFW_B_POSITION) \ + $(OPT_SIGNED_AMDFW_B_FILE) \ --location $(shell printf "%#x" $(MENDOCINO_FW_B_POSITION)) \ --anywhere \ --output $@ @@ -292,6 +312,17 @@ apu/amdfw_b-file := $(obj)/amdfw_b.rom apu/amdfw_b-position := $(AMD_FW_AB_POSITION) apu/amdfw_b-type := raw + +ifeq ($(CONFIG_SEPARATE_SIGNED_PSPFW),y) +build_complete:: $(obj)/amdfw_a.rom $(obj)/amdfw_b.rom + @printf " Adding Signed ROM and HASH\n" + $(CBFSTOOL) $(obj)/coreboot.rom write -u -r SIGNED_AMDFW_A -i 0 -f $(obj)/amdfw_a.rom.signed + $(CBFSTOOL) $(obj)/coreboot.rom write -u -r SIGNED_AMDFW_B -i 0 -f $(obj)/amdfw_b.rom.signed + $(CBFSTOOL) $(obj)/coreboot.rom add -r FW_MAIN_A -f $(obj)/amdfw_a.rom.signed.hash \ + -n apu/amdfw_a_hash -t raw + $(CBFSTOOL) $(obj)/coreboot.rom add -r FW_MAIN_B -f $(obj)/amdfw_b.rom.signed.hash \ + -n apu/amdfw_b_hash -t raw +endif # CONFIG_SEPARATE_SIGNED_PSPFW endif endif # ($(CONFIG_SOC_AMD_MENDOCINO),y) -- To view, visit https://review.coreboot.org/c/coreboot/+/67260 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If54504add72b30805b6874bee562e0b9482782b9 Gerrit-Change-Number: 67260 Gerrit-PatchSet: 15 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[L] Change in coreboot[master]: util/amdfwtool: Generate hashes for signed AMDFW components
by Martin Roth (Code Review) 03 Oct '22

03 Oct '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60290 ) Change subject: util/amdfwtool: Generate hashes for signed AMDFW components ...................................................................... util/amdfwtool: Generate hashes for signed AMDFW components Generate SHA256/SHA384 hash of the signed firmware so that PSP verstage can pass it to PSP. The PSP will use these hashes to verify the integrity of those signed firmwares. BUG=b:203597980 TEST=Build Skyrim BIOS image. Change-Id: I50d278536ba1eac754eb8a39c4c2e428a2371c44 Signed-off-by: Kangheui Won <khwon(a)chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60290 Reviewed-by: Jon Murphy <jpmurphy(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/amdfwtool/Makefile M util/amdfwtool/Makefile.inc M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h 4 files changed, 254 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Jon Murphy: Looks good to me, approved diff --git a/util/amdfwtool/Makefile b/util/amdfwtool/Makefile index e0ce3b7..53dce4c 100644 --- a/util/amdfwtool/Makefile +++ b/util/amdfwtool/Makefile @@ -1,7 +1,11 @@ # SPDX-License-Identifier: BSD-3-Clause top ?= $(abspath ../..) +ifneq ($(CC),) +HOSTCC ?= $(CC) +else HOSTCC ?= cc +endif READ_SRC = amdfwread.c READ_OBJ = $(READ_SRC:%.c=%.o) @@ -13,16 +17,24 @@ CFLAGS=-O2 -Wall -Wextra -Wshadow ${WERROR} CFLAGS += -I $(top)/src/commonlib/bsd/include +ifneq ($(PKG_CONFIG),) +HOSTPKGCONFIG ?= $(PKG_CONFIG) +else +HOSTPKGCONFIG ?= pkg-config +endif +CFLAGS += $(shell $(HOSTPKGCONFIG) --cflags libcrypto) +LDFLAGS += $(shell $(HOSTPKGCONFIG) --libs libcrypto) + all: $(TARGETS) amdfwread: $(READ_OBJ) - $(CC) $(READ_OBJ) $(LDFLAGS) -o $@ + $(HOSTCC) $(READ_OBJ) $(LDFLAGS) -o $@ amdfwtool: $(TOOL_OBJ) - $(CC) $(TOOL_OBJ) $(LDFLAGS) -o $@ + $(HOSTCC) $(TOOL_OBJ) $(LDFLAGS) -o $@ %.o: %.c $(HEADER) - $(CC) $(CFLAGS) -c -o $@ $< + $(HOSTCC) $(CFLAGS) -c -o $@ $< clean: @rm -f $(TARGETS) $(READ_OBJ) $(TOOL_OBJ) diff --git a/util/amdfwtool/Makefile.inc b/util/amdfwtool/Makefile.inc index d45d273..b61f02c 100644 --- a/util/amdfwtool/Makefile.inc +++ b/util/amdfwtool/Makefile.inc @@ -5,9 +5,14 @@ AMDFWTOOLCFLAGS=-O2 -Wall -Wextra -Wshadow -Werror AMDFWTOOLCFLAGS += -I $(top)/src/commonlib/bsd/include +HOSTPKGCONFIG ?= pkg-config + +AMDFWTOOLCFLAGS += $(shell $(HOSTPKGCONFIG) --cflags libcrypto) +LDFLAGS += $(shell $(HOSTPKGCONFIG) --libs libcrypto) + $(objutil)/amdfwtool/%.o: $(top)/util/amdfwtool/%.c # $(HEADER) $(HOSTCC) $(AMDFWTOOLCFLAGS) $(HOSTCFLAGS) -c -o $@ $< $(objutil)/amdfwtool/amdfwtool: $(addprefix $(objutil)/amdfwtool/,$(amdfwtoolobj)) printf " AMDFWTOOL\n" - $(HOSTCC) $(addprefix $(objutil)/amdfwtool/,$(amdfwtoolobj)) -o $@ + $(HOSTCC) $(addprefix $(objutil)/amdfwtool/,$(amdfwtoolobj)) $(LDFLAGS) -o $@ diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index ff4b623..d5b8d92 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -48,6 +48,7 @@ #include <fcntl.h> #include <errno.h> +#include <openssl/sha.h> #include <stdbool.h> #include <stdio.h> #include <sys/stat.h> @@ -74,6 +75,17 @@ #define DEFAULT_SOFT_FUSE_CHAIN "0x1" +/* Defines related to hashing signed binaries */ +enum hash_header_ver { + HASH_HDR_V1 = 1, +}; +/* Signature ID enums are defined by PSP based on the algorithm used. */ +enum signature_id { + SIG_ID_RSA2048, + SIG_ID_RSA4096 = 2, +}; +#define HASH_FILE_SUFFIX ".hash" + /* * Beginning with Family 15h Models 70h-7F, a.k.a Stoney Ridge, the PSP * can support an optional "combo" implementation. If the PSP sees the @@ -655,6 +667,85 @@ } } +static int add_single_sha(amd_fw_entry_hash *entry, void *buf, enum platform soc_id) +{ + uint8_t hash[SHA384_DIGEST_LENGTH]; + struct amd_fw_header *header = (struct amd_fw_header *)buf; + /* Include only signed part for hash calculation. */ + size_t len = header->fw_size_signed + sizeof(struct amd_fw_header); + uint8_t *body = (uint8_t *)buf; + + if (len > header->size_total) + return -1; + + if (header->sig_id == SIG_ID_RSA4096) { + SHA384(body, len, hash); + entry->sha_len = SHA384_DIGEST_LENGTH; + } else if (header->sig_id == SIG_ID_RSA2048) { + SHA256(body, len, hash); + entry->sha_len = SHA256_DIGEST_LENGTH; + } else { + fprintf(stderr, "%s: Unknown signature id: 0x%08x\n", + __func__, header->sig_id); + return -1; + } + + memcpy(entry->sha, hash, entry->sha_len); + entry->fw_id = get_psp_fw_type(soc_id, header); + entry->subtype = header->fw_subtype; + + return 0; +} + +static int get_num_binaries(void *buf, size_t buf_size) +{ + struct amd_fw_header *header = (struct amd_fw_header *)buf; + size_t total_len = 0; + int num_binaries = 0; + + while (total_len < buf_size) { + num_binaries++; + total_len += header->size_total; + header = (struct amd_fw_header *)(buf + total_len); + } + + if (total_len != buf_size) { + fprintf(stderr, "Malformed binary\n"); + return -1; + } + return num_binaries; +} + +static int add_sha(amd_fw_entry *entry, void *buf, size_t buf_size, enum platform soc_id) +{ + struct amd_fw_header *header = (struct amd_fw_header *)buf; + /* Include only signed part for hash calculation. */ + size_t total_len = 0; + int num_binaries = get_num_binaries(buf, buf_size); + + if (num_binaries <= 0) + return num_binaries; + + entry->hash_entries = malloc(num_binaries * sizeof(amd_fw_entry_hash)); + if (!entry->hash_entries) { + fprintf(stderr, "Error allocating memory to add FW hash\n"); + return -1; + } + entry->num_hash_entries = num_binaries; + + /* Iterate through each binary */ + for (int i = 0; i < num_binaries; i++) { + if (add_single_sha(&entry->hash_entries[i], buf + total_len, soc_id)) { + free(entry->hash_entries); + return -1; + } + total_len += header->size_total; + header = (struct amd_fw_header *)(buf + total_len); + } + + return 0; +} + static void integrate_firmwares(context *ctx, embedded_firmware *romsig, amd_fw_entry *fw_table) @@ -747,6 +838,88 @@ } } +static void write_or_fail(int fd, void *ptr, size_t size) +{ + ssize_t written; + + written = write_from_buf_to_file(fd, ptr, size); + if (written < 0 || (size_t)written != size) { + fprintf(stderr, "%s: Error writing %zu bytes - written %zd bytes\n", + __func__, size, written); + exit(-1); + } +} + +static void write_one_psp_firmware_hash_entry(int fd, amd_fw_entry_hash *entry) +{ + uint16_t type = entry->fw_id; + uint16_t subtype = entry->subtype; + + write_or_fail(fd, &type, sizeof(type)); + write_or_fail(fd, &subtype, sizeof(subtype)); + write_or_fail(fd, entry->sha, entry->sha_len); +} + +static void write_psp_firmware_hash(const char *filename, + amd_fw_entry *fw_table) +{ + struct psp_fw_hash_table hash_header = {0}; + int fd = open(filename, O_RDWR | O_CREAT | O_TRUNC, 0666); + + if (fd < 0) { + fprintf(stderr, "Error opening file: %s: %s\n", + filename, strerror(errno)); + exit(-1); + } + + hash_header.version = HASH_HDR_V1; + for (unsigned int i = 0; fw_table[i].type != AMD_FW_INVALID; i++) { + for (unsigned int j = 0; j < fw_table[i].num_hash_entries; j++) { + if (fw_table[i].hash_entries[j].sha_len == SHA256_DIGEST_LENGTH) { + hash_header.no_of_entries_256++; + } else if (fw_table[i].hash_entries[j].sha_len == + SHA384_DIGEST_LENGTH) { + hash_header.no_of_entries_384++; + } else if (fw_table[i].hash_entries[j].sha_len) { + fprintf(stderr, "%s: Error invalid sha_len %d\n", + __func__, fw_table[i].hash_entries[j].sha_len); + exit(-1); + } + } + } + + write_or_fail(fd, &hash_header, sizeof(hash_header)); + + /* Add all the SHA256 hash entries first followed by SHA384 entries. PSP verstage + processes the table in that order. Mixing and matching SHA256 and SHA384 entries + will cause the hash verification failure at run-time. */ + for (unsigned int i = 0; fw_table[i].type != AMD_FW_INVALID; i++) { + for (unsigned int j = 0; j < fw_table[i].num_hash_entries; j++) { + if (fw_table[i].hash_entries[j].sha_len == SHA256_DIGEST_LENGTH) + write_one_psp_firmware_hash_entry(fd, + &fw_table[i].hash_entries[j]); + } + } + + for (unsigned int i = 0; fw_table[i].type != AMD_FW_INVALID; i++) { + for (unsigned int j = 0; j < fw_table[i].num_hash_entries; j++) { + if (fw_table[i].hash_entries[j].sha_len == SHA384_DIGEST_LENGTH) + write_one_psp_firmware_hash_entry(fd, + &fw_table[i].hash_entries[j]); + } + } + + close(fd); + for (unsigned int i = 0; fw_table[i].type != AMD_FW_INVALID; i++) { + if (!fw_table[i].num_hash_entries || !fw_table[i].hash_entries) + continue; + + free(fw_table[i].hash_entries); + fw_table[i].hash_entries = NULL; + fw_table[i].num_hash_entries = 0; + } +} + /** * process_signed_psp_firmwares() - Process the signed PSP binaries to keep them separate * @signed_rom: Output file path grouping all the signed PSP binaries. @@ -765,6 +938,8 @@ int signed_rom_fd; ssize_t bytes, align_bytes; uint8_t *buf; + char *signed_rom_hash; + size_t signed_rom_hash_strlen; struct amd_fw_header header; struct stat fd_stat; /* Every blob in amdfw*.rom has to start at address aligned to 0x100. Prepare an @@ -781,6 +956,9 @@ } for (i = 0; fw_table[i].type != AMD_FW_INVALID; i++) { + fw_table[i].num_hash_entries = 0; + fw_table[i].hash_entries = NULL; + if (!(fw_table[i].filename) || fw_table[i].skip_hashing) continue; @@ -818,10 +996,6 @@ continue; } - if (header.size_total != fd_stat.st_size) { - close(fd); - continue; - } /* PSP binary is not signed and should not be part of signed PSP binaries set. */ @@ -876,6 +1050,9 @@ } } + if (add_sha(&fw_table[i], buf, fd_stat.st_size, soc_id)) + exit(-1); + /* File is successfully processed and is part of signed PSP binaries set. */ fw_table[i].fw_id = get_psp_fw_type(soc_id, &header); fw_table[i].addr_signed = signed_start_addr; @@ -888,6 +1065,18 @@ } close(signed_rom_fd); + + /* signed_rom file name + ".hash" + '\0' */ + signed_rom_hash_strlen = strlen(signed_rom) + strlen(HASH_FILE_SUFFIX) + 1; + signed_rom_hash = malloc(signed_rom_hash_strlen); + if (!signed_rom_hash) { + fprintf(stderr, "malloc(%lu) failed\n", signed_rom_hash_strlen); + exit(-1); + } + strcpy(signed_rom_hash, signed_rom); + strcat(signed_rom_hash, HASH_FILE_SUFFIX); + write_psp_firmware_hash(signed_rom_hash, fw_table); + free(signed_rom_hash); } static void integrate_psp_ab(context *ctx, psp_directory_table *pspdir, diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h index fd04064..2a03a9a 100644 --- a/util/amdfwtool/amdfwtool.h +++ b/util/amdfwtool/amdfwtool.h @@ -4,6 +4,7 @@ #define _AMD_FW_TOOL_H_ #include <commonlib/bsd/compiler.h> +#include <openssl/sha.h> #include <stdint.h> #include <stdbool.h> @@ -273,6 +274,14 @@ #define PSP_LVL2_AB (1 << 3) #define PSP_BOTH (PSP_LVL1 | PSP_LVL2) #define PSP_BOTH_AB (PSP_LVL1_AB | PSP_LVL2_AB) + +typedef struct _amd_fw_entry_hash { + uint16_t fw_id; + uint16_t subtype; + uint32_t sha_len; + uint8_t sha[SHA384_DIGEST_LENGTH]; +} amd_fw_entry_hash; + typedef struct _amd_fw_entry { amd_fw_type type; /* Mendocino and later SoCs use fw_id instead of fw_type. fw_type is still around @@ -292,6 +301,8 @@ /* Some files that don't have amd_fw_header have to be skipped from hashing. These files include but not limited to: *iKek*, *.tkn, *.stkn */ bool skip_hashing; + uint32_t num_hash_entries; + amd_fw_entry_hash *hash_entries; } amd_fw_entry; /* Most PSP binaries, if not all, have the following header format. */ @@ -321,6 +332,14 @@ uint8_t reserved_80[128]; } __packed; +struct psp_fw_hash_table { + uint16_t version; + uint16_t no_of_entries_256; + uint16_t no_of_entries_384; + /* The next 2 elements are pointers to arrays of SHA256 and SHA384 entries. */ + /* It does not make sense to store pointers in the CBFS file */ +} __packed; + typedef struct _amd_cb_config { bool have_whitelist; bool unlock_secure; -- To view, visit https://review.coreboot.org/c/coreboot/+/60290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50d278536ba1eac754eb8a39c4c2e428a2371c44 Gerrit-Change-Number: 60290 Gerrit-PatchSet: 16 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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