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Change subject: mb/starlabs/lite: Add variant specific cmos.layout and cmos.default
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Change subject: mb/google/skyrim/var/winterhold: Enable DPTC support for Winterhold
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Patch Set 1: Code-Review+1
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Hello Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: mb/google/skyrim/var/winterhold: Expend EC share memory register define for Dynamic Thermal Table Switching Proposal
......................................................................
mb/google/skyrim/var/winterhold: Expend EC share memory
register define for Dynamic Thermal Table Switching Proposal
Define offset 0x09 bit 5 for temperature status of thermal
table switch
Define offset 0x09 bit 6 for body detection status of thermal
table switch
BUG=b:232946420
TEST=emerge-skyrim coreboot
Signed-off-by: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com>
Change-Id: I37b3a0d8f6546361c8d5501e98e3e1b0d814fce3
---
M src/ec/google/chromeec/acpi/ec.asl
1 file changed, 22 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/68077/2
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Change subject: smbios: Add API to generate SMIOS type 28 Temperature Probe
......................................................................
Patch Set 1: Code-Review+1
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/67926/comment/aa3ff2aa_72e9ed92
PS1, Line 7: SMIOS
typo: SM*B*IOS
Patchset:
PS1:
Right now this doesn't do anything new. Is there another patch that will make use of it?
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Change subject: mb/google/skyrim/var/winterhold: Expend EC share memory register define for Dynamic Thermal Table Switching Proposal.
......................................................................
Patch Set 1:
(3 comments)
Commit Message:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159580):
https://review.coreboot.org/c/coreboot/+/68077/comment/b3db6caf_93ae2fad
PS1, Line 6:
Possible long commit subject (prefer a maximum 65 characters)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159580):
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PS1, Line 6:
Subject line should not end with a period.
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159580):
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PS1, Line 10: Define offset 0x09 bit 5 for temperature status of thermal table switch
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Change subject: mb/google/skyrim/var/winterhold: Host event support of Dynamic Thermal Table Switching Proposal
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Change subject: mb/google/skyrim/var/winterhold: Expend EC share memory register define for Dynamic Thermal Table Switching Proposal.
......................................................................
mb/google/skyrim/var/winterhold: Expend EC share memory register define
for Dynamic Thermal Table Switching Proposal.
Define offset 0x09 bit 5 for temperature status of thermal table switch
Define offset 0x09 bit 6 for body detection status of thermal table switch
BUG=b:232946420
TEST=emerge-skyrim coreboot
Signed-off-by: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com>
Change-Id: I37b3a0d8f6546361c8d5501e98e3e1b0d814fce3
---
M src/ec/google/chromeec/acpi/ec.asl
1 file changed, 20 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/68077/1
diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl
index 70bb18d..0a73dd5 100644
--- a/src/ec/google/chromeec/acpi/ec.asl
+++ b/src/ec/google/chromeec/acpi/ec.asl
@@ -56,6 +56,9 @@
CHGL, 8, // Charger Current Limit
TBMD, 1, // Tablet mode
DDPN, 3, // Device DPTF Profile Number
+ RSV1, 1, // Reserved bit
+ STTT, 1, // Switch thermal table by temperature status
+ STTB, 1, // Switch thermal table by body detection status
// DFUD must be 0 for the other 31 values to be valid
Offset (0x0a),
DFUD, 1, // Device Features Undefined
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