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[M] Change in coreboot[master]: util/amdfwtool: Add new types
by Arthur Heymans (Code Review) 04 Oct '22

04 Oct '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68119 ) Change subject: util/amdfwtool: Add new types ...................................................................... util/amdfwtool: Add new types These are used on newer platforms. Change-Id: I20dc77fb6f83dc813e3da5fe30f8f52068fc4662 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h M util/amdfwtool/data_parse.c 3 files changed, 73 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/68119/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index d482fa4..76d24c1 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -246,6 +246,7 @@ { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 2, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_FW_PSP_SECURED_DEBUG, .level = PSP_LVL2 | PSP_LVL2_AB, .skip_hashing = true }, + { .type = AMD_FW_ABL_PUBKEY, .level = PSP_BOTH | PSP_BOTH_AB }, { .type = AMD_PSP_FUSE_CHAIN, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_PSP_TRUSTLETS, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_PSP_TRUSTLETKEY, .level = PSP_LVL2 | PSP_LVL2_AB }, @@ -264,6 +265,9 @@ { .type = AMD_MP2_FW, .subprog = 2, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_DRIVER_ENTRIES, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_KVM_IMAGE, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_MP5, .subprog = 0, .level = PSP_BOTH | PSP_BOTH_AB }, + { .type = AMD_FW_MP5, .subprog = 1, .level = PSP_BOTH | PSP_BOTH_AB }, + { .type = AMD_FW_MP5, .subprog = 2, .level = PSP_BOTH | PSP_BOTH_AB }, { .type = AMD_S0I3_DRIVER, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_ABL0, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_ABL1, .level = PSP_BOTH | PSP_LVL2_AB }, @@ -273,8 +277,11 @@ { .type = AMD_ABL5, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_ABL6, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_ABL7, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_SEV_DATA, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_SEV_CODE, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_PSP_WHITELIST, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_VBIOS_BTLOADER, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_DXIO, .level = PSP_BOTH | PSP_BOTH_AB }, { .type = AMD_FW_USB_PHY, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_TOS_SEC_POLICY, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_FW_DRTM_TA, .level = PSP_LVL2 | PSP_LVL2_AB }, @@ -288,10 +295,15 @@ { .type = AMD_FW_DMCU_ISR, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_MSMU, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_SPIROM_CFG, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_MPIO, .level = PSP_BOTH | PSP_BOTH_AB }, { .type = AMD_FW_PSP_SMUSCS, .level = PSP_BOTH }, { .type = AMD_FW_DMCUB, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_PSP_BOOTLOADER_AB, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_RIB, .level = PSP_BOTH | PSP_BOTH_AB }, + { .type = AMD_FW_MPDMA_TF, .level = PSP_BOTH | PSP_BOTH_AB }, { .type = AMD_TA_IKEK, .level = PSP_BOTH | PSP_LVL2_AB, .skip_hashing = true }, + { .type = AMD_FW_GMI3_PHY, .level = PSP_BOTH | PSP_BOTH_AB }, + { .type = AMD_FW_MPDMA_PM, .level = PSP_BOTH | PSP_BOTH_AB }, { .type = AMD_FW_INVALID }, }; diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h index 81f0bfb..cd36085 100644 --- a/util/amdfwtool/amdfwtool.h +++ b/util/amdfwtool/amdfwtool.h @@ -17,6 +17,7 @@ AMD_FW_PSP_RTM_PUBKEY = 0x05, AMD_FW_PSP_SMU_FIRMWARE = 0x08, AMD_FW_PSP_SECURED_DEBUG = 0x09, + AMD_FW_ABL_PUBKEY = 0x0a, AMD_PSP_FUSE_CHAIN = 0x0b, AMD_FW_PSP_TRUSTLETS = 0x0c, AMD_FW_PSP_TRUSTLETKEY = 0x0d, @@ -29,6 +30,7 @@ AMD_MP2_FW = 0x25, AMD_DRIVER_ENTRIES = 0x28, AMD_FW_KVM_IMAGE = 0x29, + AMD_FW_MP5 = 0x2a, AMD_S0I3_DRIVER = 0x2d, AMD_ABL0 = 0x30, AMD_ABL1 = 0x31, @@ -38,9 +40,12 @@ AMD_ABL5 = 0x35, AMD_ABL6 = 0x36, AMD_ABL7 = 0x37, + AMD_SEV_DATA = 0x38, + AMD_SEV_CODE = 0x39, AMD_FW_PSP_WHITELIST = 0x3a, AMD_VBIOS_BTLOADER = 0x3c, AMD_FW_L2_PTR = 0x40, + AMD_FW_DXIO = 0x42, AMD_FW_USB_PHY = 0x44, AMD_FW_TOS_SEC_POLICY = 0x45, AMD_FW_DRTM_TA = 0x47, @@ -57,10 +62,15 @@ AMD_FW_DMCU_ISR = 0x59, AMD_FW_MSMU = 0x5a, AMD_FW_SPIROM_CFG = 0x5c, + AMD_FW_MPIO = 0x5d, AMD_FW_PSP_SMUSCS = 0x5f, AMD_FW_DMCUB = 0x71, AMD_FW_PSP_BOOTLOADER_AB = 0x73, + AMD_RIB = 0x76, + AMD_FW_MPDMA_TF = 0x8c, AMD_TA_IKEK = 0x8d, + AMD_FW_GMI3_PHY = 0x91, + AMD_FW_MPDMA_PM = 0x92, AMD_FW_IMC = 0x200, /* Large enough to be larger than the top BHD entry type. */ AMD_FW_GEC, AMD_FW_XHCI, diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c index 424a68a..63ef923 100644 --- a/util/amdfwtool/data_parse.c +++ b/util/amdfwtool/data_parse.c @@ -331,6 +331,45 @@ } else if (strcmp(fw_name, "TA_IKEK_FILE") == 0) { fw_type = AMD_TA_IKEK; subprog = 0; + } else if (strcmp(fw_name, "PSP_OEM_ABL_KEY_FILE") == 0) { + fw_type = AMD_FW_ABL_PUBKEY; + subprog = 0; + } else if (strcmp(fw_name, "PSP_MP5FW_SUB0_FILE") == 0) { + fw_type = AMD_FW_MP5; + subprog = 0; + } else if (strcmp(fw_name, "PSP_MP5FW_SUB1_FILE") == 0) { + fw_type = AMD_FW_MP5; + subprog = 1; + } else if (strcmp(fw_name, "PSP_MP5FW_SUB2_FILE") == 0) { + fw_type = AMD_FW_MP5; + subprog = 2; + } else if (strcmp(fw_name, "PSP_DXIOFW_FILE") == 0) { + fw_type = AMD_FW_DXIO; + subprog = 0; + } else if (strcmp(fw_name, "PSP_MPIOFW_FILE") == 0) { + fw_type = AMD_FW_MPIO; + subprog = 0; + } else if (strcmp(fw_name, "PSP_RIB_FILE") == 0) { + fw_type = AMD_RIB; + subprog = 0; + } else if (strcmp(fw_name, "PSP_MPDMATFFW_FILE") == 0) { + fw_type = AMD_FW_MPDMA_TF; + subprog = 0; + } else if (strcmp(fw_name, "PSP_GMI3PHYFW_FILE") == 0) { + fw_type = AMD_FW_GMI3_PHY; + subprog = 0; + } else if (strcmp(fw_name, "PSP_MPDMAPMFW_FILE") == 0) { + fw_type = AMD_FW_MPDMA_PM; + subprog = 0; + } else if (strcmp(fw_name, "PSP_TOKEN_UNLOCK_FILE") == 0) { + fw_type =AMD_TOKEN_UNLOCK; + subprog = 0; + } else if (strcmp(fw_name, "SEV_DATA_FILE") == 0) { + fw_type = AMD_SEV_DATA; + subprog = 0; + } else if (strcmp(fw_name, "SEV_CODE_FILE") == 0) { + fw_type = AMD_SEV_CODE; + subprog = 0; } else { fw_type = AMD_FW_INVALID; /* TODO: Add more */ -- To view, visit https://review.coreboot.org/c/coreboot/+/68119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20dc77fb6f83dc813e3da5fe30f8f52068fc4662 Gerrit-Change-Number: 68119 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: util/amdfwutil: Order enum and use hex consistently
by Arthur Heymans (Code Review) 04 Oct '22

04 Oct '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68118 ) Change subject: util/amdfwutil: Order enum and use hex consistently ...................................................................... util/amdfwutil: Order enum and use hex consistently This makes it easier to match the code to the datasheet (55758, NDA only). This also removes the duplicate lines: "{ .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }," TESTED: google/vilboz still boots. Change-Id: I1c959a0fbbf16cc65be34b79f68ec7f92fd4368f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h 2 files changed, 60 insertions(+), 41 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/68118/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index d5b8d92..d482fa4 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -237,50 +237,34 @@ amd_fw_entry amd_psp_fw_table[] = { { .type = AMD_FW_PSP_PUBKEY, .level = PSP_BOTH | PSP_LVL2_AB, .skip_hashing = true }, { .type = AMD_FW_PSP_BOOTLOADER, .level = PSP_BOTH | PSP_LVL2_AB }, - { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 0, .level = PSP_BOTH | PSP_LVL2_AB }, - { .type = AMD_FW_PSP_RECOVERY, .level = PSP_LVL1 }, - { .type = AMD_FW_PSP_RTM_PUBKEY, .level = PSP_BOTH }, { .type = AMD_FW_PSP_SECURED_OS, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_RECOVERY, .level = PSP_LVL1 }, { .type = AMD_FW_PSP_NVRAM, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_RTM_PUBKEY, .level = PSP_BOTH }, + { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 0, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 2, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_FW_PSP_SECURED_DEBUG, .level = PSP_LVL2 | PSP_LVL2_AB, .skip_hashing = true }, + { .type = AMD_PSP_FUSE_CHAIN, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_PSP_TRUSTLETS, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_PSP_TRUSTLETKEY, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 2, .level = PSP_BOTH | PSP_LVL2_AB }, - { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, - { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_FW_PSP_SMU_FIRMWARE2, .level = PSP_BOTH | PSP_LVL2_AB }, - { .type = AMD_FW_PSP_SMUSCS, .level = PSP_BOTH }, - { .type = AMD_PSP_FUSE_CHAIN, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 2, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_DEBUG_UNLOCK, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_HW_IPCFG, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_WRAPPED_IKEK, .level = PSP_BOTH | PSP_LVL2_AB, .skip_hashing = true }, { .type = AMD_TOKEN_UNLOCK, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_SEC_GASKET, .subprog = 0, .level = PSP_BOTH | PSP_LVL2_AB }, - { .type = AMD_SEC_GASKET, .subprog = 2, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_SEC_GASKET, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, - { .type = AMD_MP2_FW, .subprog = 2, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_MP2_FW, .subprog = 1, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_SEC_GASKET, .subprog = 2, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_MP2_FW, .subprog = 0, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_MP2_FW, .subprog = 1, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_MP2_FW, .subprog = 2, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_DRIVER_ENTRIES, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_KVM_IMAGE, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_S0I3_DRIVER, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_VBIOS_BTLOADER, .level = PSP_BOTH | PSP_LVL2_AB }, - { .type = AMD_FW_TOS_SEC_POLICY, .level = PSP_BOTH | PSP_LVL2_AB }, - { .type = AMD_FW_USB_PHY, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_DRTM_TA, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_KEYDB_BL, .level = PSP_BOTH | PSP_LVL2_AB }, - { .type = AMD_FW_KEYDB_TOS, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_SPL, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_DMCU_ERAM, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_DMCU_ISR, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_MSMU, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_DMCUB, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_SPIROM_CFG, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_RPMC_NVRAM, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_PSP_BOOTLOADER_AB, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_TA_IKEK, .level = PSP_BOTH | PSP_LVL2_AB, .skip_hashing = true }, { .type = AMD_ABL0, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_ABL1, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_ABL2, .level = PSP_BOTH | PSP_LVL2_AB }, @@ -289,11 +273,25 @@ { .type = AMD_ABL5, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_ABL6, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_ABL7, .level = PSP_BOTH | PSP_LVL2_AB }, - { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, - { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_FW_PSP_WHITELIST, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_VBIOS_BTLOADER, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_USB_PHY, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_TOS_SEC_POLICY, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_DRTM_TA, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_KEYDB_BL, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_KEYDB_TOS, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_PSP_VERSTAGE, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_FW_VERSTAGE_SIG, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_RPMC_NVRAM, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_SPL, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_DMCU_ERAM, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_DMCU_ISR, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_MSMU, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_SPIROM_CFG, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_SMUSCS, .level = PSP_BOTH }, + { .type = AMD_FW_DMCUB, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_BOOTLOADER_AB, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_TA_IKEK, .level = PSP_BOTH | PSP_LVL2_AB, .skip_hashing = true }, { .type = AMD_FW_INVALID }, }; diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h index 2a03a9a..81f0bfb 100644 --- a/util/amdfwtool/amdfwtool.h +++ b/util/amdfwtool/amdfwtool.h @@ -9,19 +9,18 @@ #include <stdbool.h> typedef enum _amd_fw_type { - AMD_FW_PSP_PUBKEY = 0, - AMD_FW_PSP_BOOTLOADER = 1, - AMD_FW_PSP_SMU_FIRMWARE = 8, - AMD_FW_PSP_RECOVERY = 3, - AMD_FW_PSP_RTM_PUBKEY = 5, - AMD_FW_PSP_SECURED_OS = 2, - AMD_FW_PSP_NVRAM = 4, - AMD_FW_PSP_SECURED_DEBUG = 9, - AMD_FW_PSP_TRUSTLETS = 12, - AMD_FW_PSP_TRUSTLETKEY = 13, - AMD_FW_PSP_SMU_FIRMWARE2 = 18, - AMD_PSP_FUSE_CHAIN = 11, - AMD_FW_PSP_SMUSCS = 95, + AMD_FW_PSP_PUBKEY = 0x00, + AMD_FW_PSP_BOOTLOADER = 0x01, + AMD_FW_PSP_SECURED_OS = 0x02, + AMD_FW_PSP_RECOVERY = 0x03, + AMD_FW_PSP_NVRAM = 0x04, + AMD_FW_PSP_RTM_PUBKEY = 0x05, + AMD_FW_PSP_SMU_FIRMWARE = 0x08, + AMD_FW_PSP_SECURED_DEBUG = 0x09, + AMD_PSP_FUSE_CHAIN = 0x0b, + AMD_FW_PSP_TRUSTLETS = 0x0c, + AMD_FW_PSP_TRUSTLETKEY = 0x0d, + AMD_FW_PSP_SMU_FIRMWARE2 = 0x12, AMD_DEBUG_UNLOCK = 0x13, AMD_HW_IPCFG = 0x20, AMD_WRAPPED_IKEK = 0x21, @@ -58,6 +57,7 @@ AMD_FW_DMCU_ISR = 0x59, AMD_FW_MSMU = 0x5a, AMD_FW_SPIROM_CFG = 0x5c, + AMD_FW_PSP_SMUSCS = 0x5f, AMD_FW_DMCUB = 0x71, AMD_FW_PSP_BOOTLOADER_AB = 0x73, AMD_TA_IKEK = 0x8d, -- To view, visit https://review.coreboot.org/c/coreboot/+/68118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c959a0fbbf16cc65be34b79f68ec7f92fd4368f Gerrit-Change-Number: 68118 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/intel/alderlake: Fix UFS OCP fabric timeout
by Nick Vaccaro (Code Review) 04 Oct '22

04 Oct '22

Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67770 ) Change subject: soc/intel/alderlake: Fix UFS OCP fabric timeout ...................................................................... soc/intel/alderlake: Fix UFS OCP fabric timeout The delayed return of certain fetch instruction from memory to the UFS causes the OCP fabric to timeout on the transaction and become non-responsive. As recommended by the SoC and IP teams,program the OCP fabric register to avoid the timeout in the OCP fabric. This patch adds the following changes 1. Program the OCP fabric registers in the PS0 routine. 2. Move the ssdt contents of UFS to dsdt asl code to avoid duplication of UFS device creation BUG=b:240222922 TEST=Build and boot Nirwen UFS board, observe no system hang during Chrome PLT test. Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Change-Id: I949a4538ea5c5c378a4e8ff7bb88546db1412df2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67770 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/brya/Kconfig M src/soc/intel/alderlake/acpi/southbridge.asl A src/soc/intel/alderlake/acpi/ufs.asl M src/soc/intel/common/block/scs/Kconfig M src/soc/intel/common/block/scs/Makefile.inc D src/soc/intel/common/block/scs/ufs.c 6 files changed, 123 insertions(+), 56 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 9e41cad..c1acc37 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -67,7 +67,6 @@ select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS select MEMORY_SOLDERDOWN select SOC_INTEL_ALDERLAKE_PCH_N - select SOC_INTEL_COMMON_UFS_SUPPORT select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW select SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE select SYSTEM_TYPE_LAPTOP diff --git a/src/soc/intel/alderlake/acpi/southbridge.asl b/src/soc/intel/alderlake/acpi/southbridge.asl index 3c37d57..2e419b1 100644 --- a/src/soc/intel/alderlake/acpi/southbridge.asl +++ b/src/soc/intel/alderlake/acpi/southbridge.asl @@ -31,6 +31,9 @@ #include "scs.asl" #endif +/* UFS */ +#include "ufs.asl" + /* SMBus 0:1f.4 */ #include <soc/intel/common/block/acpi/acpi/smbus.asl> diff --git a/src/soc/intel/alderlake/acpi/ufs.asl b/src/soc/intel/alderlake/acpi/ufs.asl new file mode 100644 index 0000000..d6774f8 --- /dev/null +++ b/src/soc/intel/alderlake/acpi/ufs.asl @@ -0,0 +1,92 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/pcr_ids.h> + +#define R_SCS_CFG_PCS 0x84 +#define R_SCS_CFG_PG_CONFIG 0xA2 + +#define PID_UFSX2 0x50 + +#define R_SCS_PCR_1C20 0x1C20 +#define R_SCS_PCR_4820 0x4820 +#define R_SCS_PCR_4020 0x4020 +#define R_SCS_PCR_5820 0x5820 +#define R_SCS_PCR_5C20 0x5C20 +#define R_SCS_PCR_1078 0x1078 +#define R_PMC_PWRM_LTR_IGN 0x1B0C + +External(PCRA, MethodObj) + +Scope (\_SB.PCI0) +{ + Device (UFS) + { + Name (_ADR, 0x0000000000120007) // _ADR: Address + Name (_DDN, "UFS Controller") // _DDN: DOS Device Name + Name (_DSD, Package (0x02) // _DSD: Device-Specific Data + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, + Package (0x01) + { + Package (0x02) + { + "ref-clk-freq", + CONFIG_SOC_INTEL_UFS_CLK_FREQ_HZ + } + } + }) + + Method (OCPD, 0, Serialized) + { + + /* + * OCP Timer need to be disabled in SCS UFS IOSF Bridge to work around + * the Silicon Issue due to which LTR mechanism doest work Registers + * from the UFS OCP Fabric Register space that need to be programmed + * for the timeout are + * Upstream Initiator Port -- offset 0x4020 + * Downstream Target Port -- offset 0x4820 + * Downstream Target port at Controller -- offset 0x5c20 + * Upstream Initiator port at Controller -- offset 0x5820 + * Control over interconnect-wide functions -- offset 0x1078 + */ + PCRA (PID_UFSX2, R_SCS_PCR_4020, 0x0) + PCRA (PID_UFSX2, R_SCS_PCR_4820, 0x0) + PCRA (PID_UFSX2, R_SCS_PCR_5C20, 0x0) + PCRA (PID_UFSX2, R_SCS_PCR_5820, 0x0) + PCRA (PID_UFSX2, R_SCS_PCR_1078, 0x0) + } + + /* Memory Region to access to the UFS PCI Configuration Space */ + + OperationRegion(SCSR, PCI_Config, 0x00, 0x100) + Field (SCSR, ByteAcc, NoLock, Preserve) + { + Offset(R_SCS_CFG_PCS), /* 0x84, PMCSR - Power Management Control and Status*/ + PSTA,32, + Offset(R_SCS_CFG_PG_CONFIG),/* 0xA2, Device PG config */ + , 2, + PGEN, 1 /* [BIT2] PGE - PG Enable */ + } + + Method (_PS0, 0, Serialized) + { + Store(0, PGEN) /* Disable PG */ + + And(PSTA, 0xFFFFFFFC, PSTA) /* Set BIT[1:0] = 00b - Power State D0 */ + + /* Disable OCP Timer in SCS UFS IOSF Bridge */ + OCPD () + } + + Method (_PS3, 0, Serialized) + { + + Store(1, PGEN) /* Enable PG */ + } + Method (_INI) + { + OCPD () + } + } +} diff --git a/src/soc/intel/common/block/scs/Kconfig b/src/soc/intel/common/block/scs/Kconfig index 6b5f49e..192425c 100644 --- a/src/soc/intel/common/block/scs/Kconfig +++ b/src/soc/intel/common/block/scs/Kconfig @@ -19,10 +19,3 @@ help Override the MMC settings after FSP-S. It should be used only when there is no FSP UPDs for certain setting. - -config SOC_INTEL_COMMON_UFS_SUPPORT - bool - default n - help - Enable UFS support. Should be enabled when a particular SoC supports - boot from UFS. diff --git a/src/soc/intel/common/block/scs/Makefile.inc b/src/soc/intel/common/block/scs/Makefile.inc index aa5f2b5..0b77f5f 100644 --- a/src/soc/intel/common/block/scs/Makefile.inc +++ b/src/soc/intel/common/block/scs/Makefile.inc @@ -2,5 +2,4 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SCS) += sd.c endif ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SCS) += mmc.c -ramstage-$(CONFIG_SOC_INTEL_COMMON_UFS_SUPPORT) += ufs.c romstage-$(CONFIG_SOC_INTEL_COMMON_EARLY_MMC_WAKE) += early_mmc.c diff --git a/src/soc/intel/common/block/scs/ufs.c b/src/soc/intel/common/block/scs/ufs.c deleted file mode 100644 index e70c87b..0000000 --- a/src/soc/intel/common/block/scs/ufs.c +++ /dev/null @@ -1,47 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -#include <acpi/acpi_device.h> -#include <acpi/acpigen.h> -#include <acpi/acpigen_pci.h> -#include <device/pci.h> -#include <device/pci_ids.h> - -#if CONFIG(HAVE_ACPI_TABLES) -static void ufs_fill_ssdt(const struct device *dev) -{ - struct acpi_dp *dsd; - - const char *scope = acpi_device_scope(dev); - - acpigen_write_scope(scope); - acpigen_write_device("UFS"); - acpigen_write_ADR_pci_device(dev); - acpigen_write_name_string("_DDN", "UFS Controller"); - - dsd = acpi_dp_new_table("_DSD"); - acpi_dp_add_integer(dsd, "ref-clk-freq", CONFIG_SOC_INTEL_UFS_CLK_FREQ_HZ); - acpi_dp_write(dsd); - acpigen_write_device_end(); - acpigen_pop_len(); -} -#endif - -static struct device_operations dev_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, -#if CONFIG(HAVE_ACPI_TABLES) - .acpi_fill_ssdt = ufs_fill_ssdt, -#endif - .ops_pci = &pci_dev_ops_pci, -}; - -static const unsigned short pci_device_ids[] = { - PCI_DID_INTEL_ADP_UFS, - 0 -}; - -static const struct pci_driver pch_ufs __pci_driver = { - .ops = &dev_ops, - .vendor = PCI_VID_INTEL, - .devices = pci_device_ids -}; -- To view, visit https://review.coreboot.org/c/coreboot/+/67770 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I949a4538ea5c5c378a4e8ff7bb88546db1412df2 Gerrit-Change-Number: 67770 Gerrit-PatchSet: 4 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-Reviewer: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniil Lunev <dlunev(a)chromium.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/amd/*: Move emmc disabling to device ops
by Matt DeVillier (Code Review) 04 Oct '22

04 Oct '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Arthur Heymans, Fred Reitberger, Felix Held. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68113 ) Change subject: soc/amd/*: Move emmc disabling to device ops ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/68113 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4052438185e7861792733b96a1298201c73fc3ff Gerrit-Change-Number: 68113 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 04 Oct 2022 17:33:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: src/soc/intel/alderlake: Add HDA link enable parameter
by Gaggery Tsai (Code Review) 04 Oct '22

04 Oct '22

Attention is currently required from: Tim Wawrzynczak. Hello Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68117 to look at the new patch set (#2). Change subject: src/soc/intel/alderlake: Add HDA link enable parameter ...................................................................... src/soc/intel/alderlake: Add HDA link enable parameter This patch adds HDA link enable parameter. The PchHDaAudioLinkHdaEnable is required to be set for HDA link signals. The FSP uses it to enable HDA SDI signal wake/response through HDA PCR registers. Otherwise, the HDA link is not going to work even the HDA GPIO pins are configured properly. TEST=Add pch_hda_link_enable = "1" in devicetree & make & ensure the HDA ALC711 codec (HDA configured) is recognized on ADL-S RVP Signed-off-by: Gaggery Tsai <gaggery.tsai(a)intel.com> Change-Id: Id72cc9c3924250bd8f27174299a641c09c2dcad6 --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/romstage/fsp_params.c 2 files changed, 25 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/68117/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id72cc9c3924250bd8f27174299a641c09c2dcad6 Gerrit-Change-Number: 68117 Gerrit-PatchSet: 2 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: src/soc/intel/alderlake: Add HDA link enable parameter
by Gaggery Tsai (Code Review) 04 Oct '22

04 Oct '22

Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68117 ) Change subject: src/soc/intel/alderlake: Add HDA link enable parameter ...................................................................... src/soc/intel/alderlake: Add HDA link enable parameter This patch adds HDA link enable parameter. The PchHDaAudioLinkHdaEnable is required to be set for HDA link signals. The FSP uses it to enable HDA SDI signal wake/response through HDA PCR registers. Otherwise, the HDA link is not going to work even the HDA GPIO pins are configured properly. TEST=Add pch_hda_link_enable = "1" in devicetree & make & ensure the HDA ALC711 codec (HDA configured) is recognized on ADL-S RVP Signed-off-by: Gaggery Tsai <gaggery.tsai(a)intel.com> Change-Id: Id72cc9c3924250bd8f27174299a641c09c2dcad6 --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/romstage/fsp_params.c 2 files changed, 25 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/68117/1 diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 4cb6066..50de43c 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -323,6 +323,7 @@ /* Audio related */ uint8_t pch_hda_dsp_enable; + uint8_t pch_hda_link_enable; /* iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T */ enum { diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index c0bdb0d..d127f18 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -239,12 +239,12 @@ m_cfg->PchHdaIDispLinkFrequency = config->pch_hda_idisp_link_frequency; m_cfg->PchHdaIDispCodecDisconnect = !config->pch_hda_idisp_codec_enable; /* - * All the PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs are used by FSP only to - * configure GPIO pads for audio. Mainboard is expected to perform all GPIO - * configuration in coreboot and hence these UPDs are set to 0 to skip FSP GPIO - * configuration for audio pads. + * For HDA link, PchHdaAudioLinkHdaEnable needs to be set, FSP will set HDA PCR + * to activate SDI wake/response. For Non-HDA linkgit statu, Mainboard is expected + * to perform all GPIO configuration in coreboot and hence these UPDs are set + * to 0 to skip FSP GPIO configuration for audio pads. */ - m_cfg->PchHdaAudioLinkHdaEnable = 0; + m_cfg->PchHdaAudioLinkHdaEnable = config->pch_hda_link_enable; memset(m_cfg->PchHdaAudioLinkDmicEnable, 0, sizeof(m_cfg->PchHdaAudioLinkDmicEnable)); memset(m_cfg->PchHdaAudioLinkSspEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSspEnable)); memset(m_cfg->PchHdaAudioLinkSndwEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSndwEnable)); -- To view, visit https://review.coreboot.org/c/coreboot/+/68117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id72cc9c3924250bd8f27174299a641c09c2dcad6 Gerrit-Change-Number: 68117 Gerrit-PatchSet: 1 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/google/skyrim: Override SPI flash bus speed
by Karthik Ramasubramanian (Code Review) 04 Oct '22

04 Oct '22

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68116 ) Change subject: mb/google/skyrim: Override SPI flash bus speed ...................................................................... mb/google/skyrim: Override SPI flash bus speed Add configuration to bump up the SPI flash bus speed from 66 MHz to 100 MHz starting the board version where required schematics update is done. BUG=b:245949155 TEST=Build and boot to OS in Skyrim with 100 MHz SPI bus speed. Perform warm and cold reboot cycles for 100 iterations each. Observe that the boot time improved by ~115 ms compared to 66 MHz SPI flash bus speed. At 66 MHz: 508:finished loading body 538,319 (83,806) 11:start of bootblock 1,196,809 (624,777) 14:finished loading romstage 1,236,905 (39,163) 970:loading FSP-M 1,237,056 (37) 15:starting LZMA decompress (ignore for x86) 1,237,073 (17) 16:finished LZMA decompress (ignore for x86) 1,358,937 (121,864) 8:starting to load ramstage 2,010,304 (0) 15:starting LZMA decompress (ignore for x86) 2,010,312 (8) 16:finished LZMA decompress (ignore for x86) 2,067,181 (56,869) 971:loading FSP-S 2,078,232 (7,999) 17:starting LZ4 decompress (ignore for x86) 2,078,253 (21) 18:finished LZ4 decompress (ignore for x86) 2,084,297 (6,044) 90:starting to load payload 2,316,933 (5) 15:starting LZMA decompress (ignore for x86) 2,316,947 (14) 16:finished LZMA decompress (ignore for x86) 2,339,819 (22,872) Total Time: 2,464,338 At 100 MHz: 508:finished loading body 515,118 (59,364) 11:start of bootblock 1,115,043 (566,110) 14:finished loading romstage 1,146,713 (29,697) 970:loading FSP-M 1,146,865 (38) 15:starting LZMA decompress (ignore for x86) 1,146,881 (16) 16:finished LZMA decompress (ignore for x86) 1,249,351 (102,470) 8:starting to load ramstage 1,900,568 (1) 15:starting LZMA decompress (ignore for x86) 1,900,576 (8) 16:finished LZMA decompress (ignore for x86) 1,956,337 (55,761) 971:loading FSP-S 1,967,357 (7,930) 17:starting LZ4 decompress (ignore for x86) 1,967,377 (20) 18:finished LZ4 decompress (ignore for x86) 1,972,925 (5,548) 90:starting to load payload 2,205,300 (6) 15:starting LZMA decompress (ignore for x86) 2,205,313 (13) 16:finished LZMA decompress (ignore for x86) 2,227,087 (21,774) Total Time: 2,349,804 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: I5e8db22151fbc2db1f9e81b3644338348160736d --- M src/mainboard/google/skyrim/Kconfig M src/mainboard/google/skyrim/Makefile.inc A src/mainboard/google/skyrim/spi_speeds.c 3 files changed, 84 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/68116/1 diff --git a/src/mainboard/google/skyrim/Kconfig b/src/mainboard/google/skyrim/Kconfig index 87cf6e4..cfd640e 100644 --- a/src/mainboard/google/skyrim/Kconfig +++ b/src/mainboard/google/skyrim/Kconfig @@ -83,6 +83,22 @@ string default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" +config OVERRIDE_EFS_SPI_SPEED + int + default 3 if EM100 + default 4 # 100MHz + help + Override EFS SPI Speed Configuration to be applied based on certain + board version. + +config OVERRIDE_EFS_SPI_SPEED_MIN_BOARD + hex + default 0x5 if BOARD_GOOGLE_SKYRIM + default 0xffffffff + help + Minimum board version starting which the Override EFS SPI Speed + configuration has to be applied. + config VARIANT_DIR string default "skyrim" if BOARD_GOOGLE_SKYRIM diff --git a/src/mainboard/google/skyrim/Makefile.inc b/src/mainboard/google/skyrim/Makefile.inc index ba175a2..a594ceb 100644 --- a/src/mainboard/google/skyrim/Makefile.inc +++ b/src/mainboard/google/skyrim/Makefile.inc @@ -10,6 +10,8 @@ verstage-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += verstage.c +all-y += spi_speeds.c + subdirs-y += variants/baseboard subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/google/skyrim/spi_speeds.c b/src/mainboard/google/skyrim/spi_speeds.c new file mode 100644 index 0000000..857e02d --- /dev/null +++ b/src/mainboard/google/skyrim/spi_speeds.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <amdblocks/spi.h> +#include <boardid.h> +#include <stdint.h> + +void mainboard_spi_fast_speed_override(uint8_t *fast_speed) +{ + uint32_t board_ver = board_id(); + + if (board_ver >= CONFIG_OVERRIDE_EFS_SPI_SPEED_MIN_BOARD) + *fast_speed = CONFIG_OVERRIDE_EFS_SPI_SPEED; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/68116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e8db22151fbc2db1f9e81b3644338348160736d Gerrit-Change-Number: 68116 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: include/device/device_util.c: add helpers to check pci device enabled
by Angel Pons (Code Review) 04 Oct '22

04 Oct '22

Attention is currently required from: Fabio Aiuto, Paul Menzel, Tim Wawrzynczak, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68101 ) Change subject: include/device/device_util.c: add helpers to check pci device enabled ...................................................................... Patch Set 1: Code-Review-1 (1 comment) File src/device/device_util.c: https://review.coreboot.org/c/coreboot/+/68101/comment/a4da243b_45f69d50 PS1, Line 971: pci->bus->dev->path.type Why does this access the bus info? Can any of these pointers be NULL? The parameter itself can be NULL, too... -- To view, visit https://review.coreboot.org/c/coreboot/+/68101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3257c8404017372f6cdd9f6cf9453502447343a0 Gerrit-Change-Number: 68101 Gerrit-PatchSet: 1 Gerrit-Owner: Fabio Aiuto <fabioaiuto83(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Fabio Aiuto <fabioaiuto83(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 04 Oct 2022 16:27:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: treewide: use helpers to check for enabled pci devices
by Angel Pons (Code Review) 04 Oct '22

04 Oct '22

Attention is currently required from: Jeff Daly, Fabio Aiuto, Mariusz Szafrański, Suresh Bellampalli, Stefan Reinauer, Vanessa Eusebio. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68102 ) Change subject: treewide: use helpers to check for enabled pci devices ...................................................................... Patch Set 2: -Code-Review (1 comment) File src/southbridge/intel/lynxpoint/lpc.c: https://review.coreboot.org/c/coreboot/+/68102/comment/0682d4b6_717d2dff PS2, Line 123: if (!is_enabled_pci(irq_dev)) This is equivalent to: irq_dev->bus->dev->path.type != DEVICE_PATH_PCI || irq_dev->bus->secondary != 0 Whereas the original was: irq_dev->path.type != DEVICE_PATH_PCI || irq_dev->bus->secondary != 0 Why involve the bus? -- To view, visit https://review.coreboot.org/c/coreboot/+/68102 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb992904112db611119b2d33c8b1dd912b2c8539 Gerrit-Change-Number: 68102 Gerrit-PatchSet: 2 Gerrit-Owner: Fabio Aiuto <fabioaiuto83(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Fabio Aiuto <fabioaiuto83(a)gmail.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Comment-Date: Tue, 04 Oct 2022 16:27:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: treewide: use helper to check if pci device is on n-th bus
by Angel Pons (Code Review) 04 Oct '22

04 Oct '22

Attention is currently required from: Fabio Aiuto, Damien Zammit. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68103 ) Change subject: treewide: use helper to check if pci device is on n-th bus ...................................................................... Patch Set 2: (1 comment) File src/mainboard/emulation/qemu-i440fx/northbridge.c: https://review.coreboot.org/c/coreboot/+/68103/comment/76360c68_0a93f46b PS2, Line 222: if (!is_pci_dev_on_bus(dev, 0)) This is equivalent to: dev->bus->dev->path.type != DEVICE_PATH_PCI || dev->bus->secondary != 0 Whereas the original was: dev->path.type != DEVICE_PATH_PCI || dev->bus->secondary != 0 Why involve the bus? -- To view, visit https://review.coreboot.org/c/coreboot/+/68103 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a3e96381c29056de71953ea2c39cd540f3df191 Gerrit-Change-Number: 68103 Gerrit-PatchSet: 2 Gerrit-Owner: Fabio Aiuto <fabioaiuto83(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Fabio Aiuto <fabioaiuto83(a)gmail.com> Gerrit-Attention: Damien Zammit Gerrit-Comment-Date: Tue, 04 Oct 2022 16:26:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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