coreboot-gerrit October 2022

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[S] Change in coreboot[master]: mb/google/skyrim: Fix SMMSTORE size, alignment
by Matt DeVillier (Code Review) 04 Oct '22

04 Oct '22

Attention is currently required from: Jason Nien, Martin Roth. Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68124 ) Change subject: mb/google/skyrim: Fix SMMSTORE size, alignment ...................................................................... mb/google/skyrim: Fix SMMSTORE size, alignment SMMSTOREv2 requires 64k min size, 64k alignment. TEST=build skyrim with SMMSTOREv2 enabled Change-Id: I3501b6036df9ee1049a92e26a7b72e53b4604f60 Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/mainboard/google/skyrim/chromeos.fmd 1 file changed, 15 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/68124/1 diff --git a/src/mainboard/google/skyrim/chromeos.fmd b/src/mainboard/google/skyrim/chromeos.fmd index 670ac16..d9a4f8f 100644 --- a/src/mainboard/google/skyrim/chromeos.fmd +++ b/src/mainboard/google/skyrim/chromeos.fmd @@ -20,7 +20,7 @@ } RW_VPD(PRESERVE) 8K RW_NVRAM(PRESERVE) 20K - SMMSTORE(PRESERVE) 4K + SMMSTORE(PRESERVE)@0x630000 64K RW_LEGACY(CBFS) WP_RO@8M 8M { RO_VPD(PRESERVE) 16K -- To view, visit https://review.coreboot.org/c/coreboot/+/68124 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3501b6036df9ee1049a92e26a7b72e53b4604f60 Gerrit-Change-Number: 68124 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/guybrush: Fix SMMSTORE size, alignment
by Matt DeVillier (Code Review) 04 Oct '22

04 Oct '22

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68123 ) Change subject: mb/google/guybrush: Fix SMMSTORE size, alignment ...................................................................... mb/google/guybrush: Fix SMMSTORE size, alignment SMMSTOREv2 requires 64k min size, 64k alignment. TEST=build guybrush with SMMSTOREv2 enabled Change-Id: I78cb873a5634c659067367260cc7063fbd60d77a Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/mainboard/google/guybrush/chromeos.fmd 1 file changed, 15 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/68123/1 diff --git a/src/mainboard/google/guybrush/chromeos.fmd b/src/mainboard/google/guybrush/chromeos.fmd index 8b5b11a..225fe2a 100644 --- a/src/mainboard/google/guybrush/chromeos.fmd +++ b/src/mainboard/google/guybrush/chromeos.fmd @@ -18,7 +18,7 @@ } RW_VPD(PRESERVE) 8K RW_NVRAM(PRESERVE) 20K - SMMSTORE(PRESERVE) 4K + SMMSTORE(PRESERVE)@0x620000 64K RW_LEGACY(CBFS) WP_RO@8M 8M { RO_VPD(PRESERVE) 16K -- To view, visit https://review.coreboot.org/c/coreboot/+/68123 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78cb873a5634c659067367260cc7063fbd60d77a Gerrit-Change-Number: 68123 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/brya/var/brya0: use RPL FSP headers
by YH Lin (Code Review) 04 Oct '22

04 Oct '22

Attention is currently required from: Bora Guvendik, Tarun Tuli, Subrata Banik, Selma Bensaid, Tim Wawrzynczak, Nick Vaccaro. YH Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68094 ) Change subject: mb/google/brya/var/brya0: use RPL FSP headers ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/68094 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2dd84757532d734ad97b74ba960537d937fb313e Gerrit-Change-Number: 68094 Gerrit-PatchSet: 2 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 04 Oct 2022 20:23:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/var/brya0: add new THERMAL FW_CONFIG field
by YH Lin (Code Review) 04 Oct '22

04 Oct '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Nick Vaccaro. YH Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68025 ) Change subject: mb/google/brya/var/brya0: add new THERMAL FW_CONFIG field ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/68025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba3bd87abd4c112ceff4bbe51a7cf9eae3a694f2 Gerrit-Change-Number: 68025 Gerrit-PatchSet: 4 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 04 Oct 2022 20:23:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/brya/var/skolas: sync brya0 and skolas FW_CONFIG
by YH Lin (Code Review) 04 Oct '22

04 Oct '22

Attention is currently required from: Bora Guvendik, Varshit Pandya, Noga Smith, Subrata Banik, Selma Bensaid, Tim Wawrzynczak, Nick Vaccaro, AlanKY Lee. YH Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67929 ) Change subject: mb/google/brya/var/skolas: sync brya0 and skolas FW_CONFIG ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/67929 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3be26e0a05f4dc08e5dc3f6ef7b71bdd8fd4f859 Gerrit-Change-Number: 67929 Gerrit-PatchSet: 5 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: AlanKY Lee <alanky_lee(a)compal.corp-partner.google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Noga Smith <nogasmith(a)google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Noga Smith <nogasmith(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: AlanKY Lee <alanky_lee(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 04 Oct 2022 20:23:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/common/[,block/cpu/]Makefile.inc: Add support for sbin ucode ...
by Fred Reitberger (Code Review) 04 Oct '22

04 Oct '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Matt DeVillier, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68122 to look at the new patch set (#2). Change subject: soc/amd/common/[,block/cpu/]Makefile.inc: Add support for sbin ucode files ...................................................................... soc/amd/common/[,block/cpu/]Makefile.inc: Add support for sbin ucode files Recent PI releases have been distributing the ucode patch files as sbin files instead of bin files. The sbin uses a 256 byte amd_fw_header to wrap the bin file. Offset 0x14 of the header is the size field. The can be extracted with hexdump to get the size of the ucode bin file. The bin file can then be extracted with dd and placed in the build directory for inclusion as a cbfs file. In the case where both an sbin and bin ucode file are present, the sbin file will be added and a note will print at the start of the build about the bin file being skipped. TEST=chausie/morphius builds with only bin, only sbin, non-matching bin and sbin, matching bin and sbin files Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: I29768ea19543bdc76662e687f59bf31b76f555ae --- M src/soc/amd/common/Makefile.inc M src/soc/amd/common/block/cpu/Makefile.inc 2 files changed, 58 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/68122/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68122 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29768ea19543bdc76662e687f59bf31b76f555ae Gerrit-Change-Number: 68122 Gerrit-PatchSet: 2 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/amd/common/[,block/cpu/]Makefile.inc: Add support for sbin ucode ...
by Fred Reitberger (Code Review) 04 Oct '22

04 Oct '22

Fred Reitberger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68122 ) Change subject: soc/amd/common/[,block/cpu/]Makefile.inc: Add support for sbin ucode files ...................................................................... soc/amd/common/[,block/cpu/]Makefile.inc: Add support for sbin ucode files Recent PI releases have been distributing the ucode patch files as sbin files instead of bin files. The sbin uses a 256 byte amd_fw_header to wrap the bin file. Offset 0x14 of the header is the size field. The can be extracted with hexdump to get the size of the ucode bin file. The bin file can then be extracted with dd and placed in the build directory for inclusion as a cbfs file. In the case where both an sbin and bin ucode file are present, the sbin file will be added and a note will print at the start of the build about the bin file being skipped. TEST=chausie/morphius builds with only bin, only sbin, non-matching bin and sbin, matching bin and sbin files Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: I29768ea19543bdc76662e687f59bf31b76f555ae --- M src/soc/amd/common/Makefile.inc M src/soc/amd/common/block/cpu/Makefile.inc 2 files changed, 59 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/68122/1 diff --git a/src/soc/amd/common/Makefile.inc b/src/soc/amd/common/Makefile.inc index a935565..eeb68aa 100644 --- a/src/soc/amd/common/Makefile.inc +++ b/src/soc/amd/common/Makefile.inc @@ -13,5 +13,6 @@ DEP_FILES= $(patsubst %,$(FIRMWARE_LOCATION)/%, $(shell sed -e /^$(POUND_SIGN)/d -e /*/d -e /^FIRMWARE_LOCATION/d $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}' )) amd_microcode_bins += $(wildcard ${FIRMWARE_LOCATION}/*UcodePatch_*.bin) +amd_microcode_sbins += $(wildcard ${FIRMWARE_LOCATION}/*UcodePatch_*.sbin) endif diff --git a/src/soc/amd/common/block/cpu/Makefile.inc b/src/soc/amd/common/block/cpu/Makefile.inc index 7541a9b..174027b 100644 --- a/src/soc/amd/common/block/cpu/Makefile.inc +++ b/src/soc/amd/common/block/cpu/Makefile.inc @@ -16,5 +16,35 @@ endif endef -$(foreach ucode,$(amd_microcode_bins),$(eval $(call add-ucode-as-cbfs,$(ucode),$(shell hexdump -n 2 -s 0x18 -e '"%x"' $(ucode))))) -endif +# Function to grab bytes from a file and format them as desired +# $(call extract-bytes,filename,bytes-to-read,offset-to-bytes,output-format) +extract-bytes = $(shell hexdump -n $(2) -s $(3) -e '$(4)' $(1)) + +# Function to grab part of one file and put it into another +# $(call extract-to-file,input-filename,output-filename,offset-into-file,bytes-to-get) +extract-to-file = $(shell dd ibs=1 status=none skip=$(3) count=$(4) if=$(1) of=$(2)) + +# Standardize the name of the temp file created in the build directory +tmp-ucode-name = $(obj)/$(subst .sbin,.bin,$(notdir $(1))) + +# add-ucode-sbin-as-cbfs +# $(call add-ucode-sbin-as-cbfs,sbin-ucode-file) +# Convert the sbin to a bin file located at tmp-ucode-name, then add the bin file with add-ucode-as-cbfs +# The sbin header is 256 bytes, and the size of the unwrapped file is at offset 0x14 +define add-ucode-sbin-as-cbfs + $(eval $(call extract-to-file,$(1),$(call tmp-ucode-name,$(1)),256,$(call extract-bytes,$(1),4,0x14,"%d"))) + $(eval $(call add-ucode-as-cbfs,$(call tmp-ucode-name,$(1)),$(call extract-bytes,$(1),2,0x118,"%04x"))) +endef + +# check if there is already an sbin wrapped ucode file and only add if there is not +define add-ucode-if-not-sbin + $(if $(findstring $(call tmp-ucode-name,$(1)),$(call tmp-ucode-name,$(amd_microcode_sbins))),\ + $(info skipping $(1) due to .sbin),\ + $(call add-ucode-as-cbfs,$(1),$(call extract-bytes,$(1),2,0x18,"%04x"))) +endef + +$(foreach ucsbin,$(amd_microcode_sbins),$(eval $(call add-ucode-sbin-as-cbfs,$(ucsbin)))) +$(foreach ucode,$(amd_microcode_bins),$(eval $(call add-ucode-if-not-sbin,$(ucode)))) + +endif #ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_UCODE),y) + -- To view, visit https://review.coreboot.org/c/coreboot/+/68122 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29768ea19543bdc76662e687f59bf31b76f555ae Gerrit-Change-Number: 68122 Gerrit-PatchSet: 1 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: util/amdfwtool: Add new types
by build bot (Jenkins) (Code Review) 04 Oct '22

04 Oct '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68119 ) Change subject: util/amdfwtool: Add new types ...................................................................... Patch Set 1: (1 comment) File util/amdfwtool/data_parse.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159666): https://review.coreboot.org/c/coreboot/+/68119/comment/0a51266d_726b1bb6 PS1, Line 365: fw_type =AMD_TOKEN_UNLOCK; spaces required around that '=' (ctx:WxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/68119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20dc77fb6f83dc813e3da5fe30f8f52068fc4662 Gerrit-Change-Number: 68119 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 04 Oct 2022 18:39:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: util/amdfwtool: Add more instances some types in BDT
by Arthur Heymans (Code Review) 04 Oct '22

04 Oct '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68121 ) Change subject: util/amdfwtool: Add more instances some types in BDT ...................................................................... util/amdfwtool: Add more instances some types in BDT Some hardware uses more instances. Change-Id: Ie4ed2ce0d077013b450df99a88e904c8658cfc2d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/amdfwtool/amdfwtool.c 1 file changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/68121/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index a0a1050..18220a6 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -357,17 +357,33 @@ { .type = AMD_BIOS_PMUD, .inst = 1, .subpr = 0, .level = BDT_BOTH }, { .type = AMD_BIOS_PMUI, .inst = 2, .subpr = 0, .level = BDT_BOTH }, { .type = AMD_BIOS_PMUD, .inst = 2, .subpr = 0, .level = BDT_BOTH }, + { .type = AMD_BIOS_PMUI, .inst = 3, .subpr = 0, .level = BDT_BOTH }, + { .type = AMD_BIOS_PMUD, .inst = 3, .subpr = 0, .level = BDT_BOTH }, { .type = AMD_BIOS_PMUI, .inst = 4, .subpr = 0, .level = BDT_BOTH }, { .type = AMD_BIOS_PMUD, .inst = 4, .subpr = 0, .level = BDT_BOTH }, + { .type = AMD_BIOS_PMUI, .inst = 9, .subpr = 0, .level = BDT_BOTH }, + { .type = AMD_BIOS_PMUD, .inst = 9, .subpr = 0, .level = BDT_BOTH }, + { .type = AMD_BIOS_PMUI, .inst = 10, .subpr = 0, .level = BDT_BOTH }, + { .type = AMD_BIOS_PMUD, .inst = 10, .subpr = 0, .level = BDT_BOTH }, { .type = AMD_BIOS_PMUI, .inst = 1, .subpr = 1, .level = BDT_BOTH }, { .type = AMD_BIOS_PMUD, .inst = 1, .subpr = 1, .level = BDT_BOTH }, { .type = AMD_BIOS_PMUI, .inst = 2, .subpr = 1, .level = BDT_BOTH }, { .type = AMD_BIOS_PMUD, .inst = 2, .subpr = 1, .level = BDT_BOTH }, + { .type = AMD_BIOS_PMUI, .inst = 3, .subpr = 1, .level = BDT_BOTH }, + { .type = AMD_BIOS_PMUD, .inst = 3, .subpr = 1, .level = BDT_BOTH }, { .type = AMD_BIOS_PMUI, .inst = 4, .subpr = 1, .level = BDT_BOTH }, { .type = AMD_BIOS_PMUD, .inst = 4, .subpr = 1, .level = BDT_BOTH }, + { .type = AMD_BIOS_PMUI, .inst = 9, .subpr = 1, .level = BDT_BOTH }, + { .type = AMD_BIOS_PMUD, .inst = 9, .subpr = 1, .level = BDT_BOTH }, + { .type = AMD_BIOS_PMUI, .inst = 10, .subpr = 1, .level = BDT_BOTH }, + { .type = AMD_BIOS_PMUD, .inst = 10, .subpr = 1, .level = BDT_BOTH }, { .type = AMD_BIOS_UCODE, .inst = 0, .level = BDT_LVL2 }, { .type = AMD_BIOS_UCODE, .inst = 1, .level = BDT_LVL2 }, { .type = AMD_BIOS_UCODE, .inst = 2, .level = BDT_LVL2 }, + { .type = AMD_BIOS_UCODE, .inst = 3, .level = BDT_LVL2 }, + { .type = AMD_BIOS_UCODE, .inst = 4, .level = BDT_LVL2 }, + { .type = AMD_BIOS_UCODE, .inst = 5, .level = BDT_LVL2 }, + { .type = AMD_BIOS_UCODE, .inst = 6, .level = BDT_LVL2 }, { .type = AMD_BIOS_MP2_CFG, .level = BDT_LVL2 }, { .type = AMD_BIOS_PSP_SHARED_MEM, .inst = 0, .level = BDT_BOTH }, { .type = AMD_BIOS_INVALID }, -- To view, visit https://review.coreboot.org/c/coreboot/+/68121 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4ed2ce0d077013b450df99a88e904c8658cfc2d Gerrit-Change-Number: 68121 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: util/amdfwutil: Add some types to both LVL
by Arthur Heymans (Code Review) 04 Oct '22

04 Oct '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68120 ) Change subject: util/amdfwutil: Add some types to both LVL ...................................................................... util/amdfwutil: Add some types to both LVL Some hardware also needs those at LVL1. Change-Id: Icb838396baf79f32823ca271f55456570ba40c20 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/amdfwtool/amdfwtool.c 1 file changed, 17 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/68120/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 76d24c1..a0a1050 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -236,7 +236,7 @@ amd_fw_entry amd_psp_fw_table[] = { { .type = AMD_FW_PSP_PUBKEY, .level = PSP_BOTH | PSP_LVL2_AB, .skip_hashing = true }, - { .type = AMD_FW_PSP_BOOTLOADER, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_BOOTLOADER, .level = PSP_BOTH | PSP_BOTH_AB }, { .type = AMD_FW_PSP_SECURED_OS, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_PSP_RECOVERY, .level = PSP_LVL1 }, { .type = AMD_FW_PSP_NVRAM, .level = PSP_LVL2 | PSP_LVL2_AB }, @@ -247,13 +247,13 @@ { .type = AMD_FW_PSP_SECURED_DEBUG, .level = PSP_LVL2 | PSP_LVL2_AB, .skip_hashing = true }, { .type = AMD_FW_ABL_PUBKEY, .level = PSP_BOTH | PSP_BOTH_AB }, - { .type = AMD_PSP_FUSE_CHAIN, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_PSP_FUSE_CHAIN, .level = PSP_BOTH | PSP_BOTH_AB }, { .type = AMD_FW_PSP_TRUSTLETS, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_PSP_TRUSTLETKEY, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_PSP_SMU_FIRMWARE2, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 0, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 2, .level = PSP_BOTH | PSP_LVL2_AB }, - { .type = AMD_DEBUG_UNLOCK, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_DEBUG_UNLOCK, .level = PSP_BOTH | PSP_BOTH_AB }, { .type = AMD_HW_IPCFG, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_WRAPPED_IKEK, .level = PSP_BOTH | PSP_LVL2_AB, .skip_hashing = true }, { .type = AMD_TOKEN_UNLOCK, .level = PSP_BOTH | PSP_LVL2_AB }, @@ -290,7 +290,7 @@ { .type = AMD_FW_PSP_VERSTAGE, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_FW_VERSTAGE_SIG, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_RPMC_NVRAM, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_SPL, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_SPL, .level = PSP_BOTH | PSP_BOTH_AB }, { .type = AMD_FW_DMCU_ERAM, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_DMCU_ISR, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_MSMU, .level = PSP_LVL2 | PSP_LVL2_AB }, -- To view, visit https://review.coreboot.org/c/coreboot/+/68120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb838396baf79f32823ca271f55456570ba40c20 Gerrit-Change-Number: 68120 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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coreboot-gerrit October 2022