coreboot-gerrit October 2022

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[M] Change in coreboot[master]: mb/google/nissa/pujjo: Tuning eMMC DLL value for eMMC initialization ...
by Leo Chou (Code Review) 05 Oct '22

05 Oct '22

Attention is currently required from: Jamie Chen, Tim Wawrzynczak, Shou-Chieh Hsu, Leo Chou. Hello build bot (Jenkins), Jamie Chen, Reka Norman, Tim Wawrzynczak, Shou-Chieh Hsu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68095 to look at the new patch set (#3). Change subject: mb/google/nissa/pujjo: Tuning eMMC DLL value for eMMC initialization error ...................................................................... mb/google/nissa/pujjo: Tuning eMMC DLL value for eMMC initialization error Configure eMMC DLL tuning values for Pujjo board. BUG=b:241854926 TEST="Use the value to boot on Pujjo successfully." Signed-off-by: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Change-Id: Ic36c817fa546741e394668297ca43db3a45ee105 --- M src/mainboard/google/brya/variants/pujjo/overridetree.cb 1 file changed, 60 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/68095/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/68095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic36c817fa546741e394668297ca43db3a45ee105 Gerrit-Change-Number: 68095 Gerrit-PatchSet: 3 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-CC: Jynn Chen <jynn.chen(a)lcfc.corp-partner.google.com> Gerrit-CC: Leanne1 Chen <leanne1.chen(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/nissa/pujjo: Tuning eMMC DLL value for eMMC initialization ...
by Leo Chou (Code Review) 05 Oct '22

05 Oct '22

Attention is currently required from: Jamie Chen, Tim Wawrzynczak, Shou-Chieh Hsu, Leo Chou. Hello build bot (Jenkins), Jamie Chen, Reka Norman, Tim Wawrzynczak, Shou-Chieh Hsu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68095 to look at the new patch set (#2). Change subject: mb/google/nissa/pujjo: Tuning eMMC DLL value for eMMC initialization error ...................................................................... mb/google/nissa/pujjo: Tuning eMMC DLL value for eMMC initialization error Configure eMMC DLL tuning values for Pujjo board. BUG=b:241854926 TEST=Use the value to boot on Pujjo successfully. Signed-off-by: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Change-Id: Ic36c817fa546741e394668297ca43db3a45ee105 --- M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/variants/pujjo/overridetree.cb 2 files changed, 61 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/68095/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic36c817fa546741e394668297ca43db3a45ee105 Gerrit-Change-Number: 68095 Gerrit-PatchSet: 2 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-CC: Jynn Chen <jynn.chen(a)lcfc.corp-partner.google.com> Gerrit-CC: Leanne1 Chen <leanne1.chen(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/brya/var/brya0: use RPL FSP headers
by Bora Guvendik (Code Review) 04 Oct '22

04 Oct '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Selma Bensaid, Tim Wawrzynczak, Nick Vaccaro. Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68094 ) Change subject: mb/google/brya/var/brya0: use RPL FSP headers ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68094 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2dd84757532d734ad97b74ba960537d937fb313e Gerrit-Change-Number: 68094 Gerrit-PatchSet: 2 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 04 Oct 2022 23:42:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/var/brya0: add new THERMAL FW_CONFIG field
by Tarun Tuli (Code Review) 04 Oct '22

04 Oct '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Nick Vaccaro. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68025 ) Change subject: mb/google/brya/var/brya0: add new THERMAL FW_CONFIG field ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba3bd87abd4c112ceff4bbe51a7cf9eae3a694f2 Gerrit-Change-Number: 68025 Gerrit-PatchSet: 4 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 04 Oct 2022 22:59:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/nissa/pujjo: Tuning eMMC DLL value for eMMC initialization ...
by Reka Norman (Code Review) 04 Oct '22

04 Oct '22

Attention is currently required from: Jamie Chen, Tim Wawrzynczak, Shou-Chieh Hsu, Leo Chou. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68095 ) Change subject: mb/google/nissa/pujjo: Tuning eMMC DLL value for eMMC initialization error ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/68095/comment/de2d92e6_aab5505e PS1, Line 12: "Use the value to boot on Pujjo successfully." nti: remove the quotes File src/mainboard/google/brya/Kconfig.name: https://review.coreboot.org/c/coreboot/+/68095/comment/44270ea3_40eba404 PS1, Line 254: select SOC_INTEL_COMMON_MMC_OVERRIDE Don't need this because it's already selected for the baseboard. -- To view, visit https://review.coreboot.org/c/coreboot/+/68095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic36c817fa546741e394668297ca43db3a45ee105 Gerrit-Change-Number: 68095 Gerrit-PatchSet: 1 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-CC: Jynn Chen <jynn.chen(a)lcfc.corp-partner.google.com> Gerrit-CC: Leanne1 Chen <leanne1.chen(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Comment-Date: Tue, 04 Oct 2022 22:16:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/{stoney,picasso}/Kconfig: Fix guarding of amdfw
by Fred Reitberger (Code Review) 04 Oct '22

04 Oct '22

Attention is currently required from: Jason Glenesk, Matt DeVillier, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68125 ) Change subject: soc/amd/{stoney,picasso}/Kconfig: Fix guarding of amdfw ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/68125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32d7fa7a4b3d41107cfdba96128a4a75f7066c6f Gerrit-Change-Number: 68125 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 04 Oct 2022 22:03:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/{CZN,MDN,PCO}: Fix building with only single RW region
by Fred Reitberger (Code Review) 04 Oct '22

04 Oct '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68126 ) Change subject: soc/amd/{CZN,MDN,PCO}: Fix building with only single RW region ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/68126 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8048e869d7449eeb1ac10bfec4a5646b848d6a8 Gerrit-Change-Number: 68126 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 04 Oct 2022 22:01:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/nissa/pujjo: Change TPM I2C freqeuncy to 1 MHz
by Reka Norman (Code Review) 04 Oct '22

04 Oct '22

Attention is currently required from: Tim Wawrzynczak, Shou-Chieh Hsu, Leo Chou. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68098 ) Change subject: mb/google/nissa/pujjo: Change TPM I2C freqeuncy to 1 MHz ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/68098/comment/7653c81a_a4d62d81 PS1, Line 12: TEST=On pujjo, all timing requirements in the spec are met. Could you please add the measured frequency here for reference? -- To view, visit https://review.coreboot.org/c/coreboot/+/68098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If99b5022a9b67e9c63c440a1e398d56bb2c467e2 Gerrit-Change-Number: 68098 Gerrit-PatchSet: 1 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-CC: Jynn Chen <jynn.chen(a)lcfc.corp-partner.google.com> Gerrit-CC: Leanne1 Chen <leanne1.chen(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Comment-Date: Tue, 04 Oct 2022 21:57:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/{CZN,MDN,PCO}: Fix building with only single RW region
by Matt DeVillier (Code Review) 04 Oct '22

04 Oct '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Fred Reitberger, Felix Held. Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68126 ) Change subject: soc/amd/{CZN,MDN,PCO}: Fix building with only single RW region ...................................................................... soc/amd/{CZN,MDN,PCO}: Fix building with only single RW region apu/amdfw_a was only getting added to CBFS when VBOOT_SLOTS_RW_AB was selected, but needs to be added in the RW_A only case as well (VBOOT_SLOTS_RW_A). Since VBOOT_SLOTS_RW_AB selects VBOOT_SLOTS_RW_A, we can guard amdfw_a and _b separately and both will be added in the RW_AB case. TEST=build google/zork with VBOOT_SLOTS_RW_A or VBOOT_SLOTS_RW_AB selected, ensure amdfw_a and amdfw_b are added to correct CBFS regions as appropriate. Change-Id: Ic8048e869d7449eeb1ac10bfec4a5646b848d6a8 Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/mendocino/Kconfig M src/soc/amd/mendocino/Makefile.inc M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc 6 files changed, 46 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/68126/1 diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 43c83bf..35b9215 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -484,7 +484,7 @@ This is the byte before the default first byte used by VBNV (0x26 + 0x0E - 1) -if VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK +if VBOOT_SLOTS_RW_A && VBOOT_STARTS_BEFORE_BOOTBLOCK config RWA_REGION_ONLY string @@ -493,6 +493,10 @@ Add a space-delimited list of filenames that should only be in the RW-A section. +endif # VBOOT_SLOTS_RW_A && VBOOT_STARTS_BEFORE_BOOTBLOCK + +if VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK + config RWB_REGION_ONLY string default "apu/amdfw_b" diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 205b349..dc97c1f 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -280,13 +280,15 @@ apu/amdfw-position := $(CEZANNE_FWM_POSITION) apu/amdfw-type := raw -ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) +ifeq ($(CONFIG_VBOOT_SLOTS_RW_A)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) cbfs-files-y += apu/amdfw_a apu/amdfw_a-file := $(obj)/amdfw_a.rom # Ensure this ends up at the beginning of the FW_MAIN_A fmap region apu/amdfw_a-position := $(AMD_FW_AB_POSITION) apu/amdfw_a-type := raw +endif +ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) cbfs-files-y += apu/amdfw_b apu/amdfw_b-file := $(obj)/amdfw_b.rom # Ensure this ends up at the beginning of the FW_MAIN_B fmap region diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig index d7c5372..9608e41 100644 --- a/src/soc/amd/mendocino/Kconfig +++ b/src/soc/amd/mendocino/Kconfig @@ -506,7 +506,7 @@ This is the byte before the default first byte used by VBNV (0x26 + 0x0E - 1) -if VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK +if VBOOT_SLOTS_RW_A && VBOOT_STARTS_BEFORE_BOOTBLOCK config RWA_REGION_ONLY string @@ -515,6 +515,10 @@ Add a space-delimited list of filenames that should only be in the RW-A section. +endif # VBOOT_SLOTS_RW_A && VBOOT_STARTS_BEFORE_BOOTBLOCK + +if VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK + config RWB_REGION_ONLY string default "apu/amdfw_b" diff --git a/src/soc/amd/mendocino/Makefile.inc b/src/soc/amd/mendocino/Makefile.inc index f8aa96f..9549426 100644 --- a/src/soc/amd/mendocino/Makefile.inc +++ b/src/soc/amd/mendocino/Makefile.inc @@ -302,18 +302,21 @@ apu/amdfw-position := $(MENDOCINO_FWM_POSITION) apu/amdfw-type := raw -ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) +ifeq ($(CONFIG_VBOOT_SLOTS_RW_A)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) cbfs-files-y += apu/amdfw_a apu/amdfw_a-file := $(obj)/amdfw_a.rom apu/amdfw_a-position := $(AMD_FW_AB_POSITION) apu/amdfw_a-type := raw +endif +ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) cbfs-files-y += apu/amdfw_b apu/amdfw_b-file := $(obj)/amdfw_b.rom apu/amdfw_b-position := $(AMD_FW_AB_POSITION) apu/amdfw_b-type := raw +endif -ifeq ($(CONFIG_SEPARATE_SIGNED_PSPFW),y) +ifeq ($(CONFIG_SEPARATE_SIGNED_PSPFW)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) build_complete:: $(obj)/amdfw_a.rom $(obj)/amdfw_b.rom @printf " Adding Signed ROM and HASH\n" $(CBFSTOOL) $(obj)/coreboot.rom write -u -r SIGNED_AMDFW_A -i 0 -f $(obj)/amdfw_a.rom.signed @@ -322,7 +325,6 @@ -n apu/amdfw_a_hash -t raw $(CBFSTOOL) $(obj)/coreboot.rom add -r FW_MAIN_B -f $(obj)/amdfw_b.rom.signed.hash \ -n apu/amdfw_b_hash -t raw -endif # CONFIG_SEPARATE_SIGNED_PSPFW endif endif # ($(CONFIG_SOC_AMD_MENDOCINO),y) diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 6b8b910..f3b982d 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -500,7 +500,7 @@ This is the byte before the default first byte used by VBNV (0x26 + 0x0E - 1) -if VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK +if VBOOT_SLOTS_RW_A && VBOOT_STARTS_BEFORE_BOOTBLOCK config RWA_REGION_ONLY string @@ -509,6 +509,10 @@ Add a space-delimited list of filenames that should only be in the RW-A section. +endif # VBOOT_SLOTS_RW_A && VBOOT_STARTS_BEFORE_BOOTBLOCK + +if VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK + config RWB_REGION_ONLY string default "apu/amdfw_b" diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index d909b2c..3e43a3d 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -292,12 +292,14 @@ apu/amdfw-position := $(PICASSO_FWM_POSITION) apu/amdfw-type := raw -ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) +ifeq ($(CONFIG_VBOOT_SLOTS_RW_A)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) cbfs-files-y += apu/amdfw_a apu/amdfw_a-file := $(obj)/amdfw_a.rom apu/amdfw_a-position := $(AMD_FW_AB_POSITION) apu/amdfw_a-type := raw +endif +ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) cbfs-files-y += apu/amdfw_b apu/amdfw_b-file := $(obj)/amdfw_b.rom apu/amdfw_b-position := $(AMD_FW_AB_POSITION) -- To view, visit https://review.coreboot.org/c/coreboot/+/68126 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8048e869d7449eeb1ac10bfec4a5646b848d6a8 Gerrit-Change-Number: 68126 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/{stoney,picasso}/Kconfig: Fix guarding of amdfw
by Matt DeVillier (Code Review) 04 Oct '22

04 Oct '22

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68125 ) Change subject: soc/amd/{stoney,picasso}/Kconfig: Fix guarding of amdfw ...................................................................... soc/amd/{stoney,picasso}/Kconfig: Fix guarding of amdfw apu/amdfw should be restricted to the RO region only when building with VBOOT + any RW region (RW_A or RW_A + RW_B); it is not tied to ChromeOS in any way. Fix guarding to match newer AMD platforms (eg, CZN/MDN). TEST=build google/zork without CHROMEOS, with VBOOT_SLOTS_RW_A Change-Id: I32d7fa7a4b3d41107cfdba96128a4a75f7066c6f Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/soc/amd/picasso/Kconfig M src/soc/amd/stoneyridge/Kconfig 2 files changed, 18 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/68125/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 30ca132..6b8b910 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -330,7 +330,7 @@ config RO_REGION_ONLY string - depends on CHROMEOS + depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A default "apu/amdfw" config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 2517e44..26dca89 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -357,7 +357,7 @@ config RO_REGION_ONLY string - depends on CHROMEOS + depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A default "apu/amdfw" config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ -- To view, visit https://review.coreboot.org/c/coreboot/+/68125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32d7fa7a4b3d41107cfdba96128a4a75f7066c6f Gerrit-Change-Number: 68125 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2022