coreboot-gerrit September 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: drivers/intel/fsp2_0/Kconfig: select HAVE_DISPLAY_MTRRS
by Angel Pons (Code Review) 05 Sep '21

05 Sep '21

Attention is currently required from: Raul Rangel, Martin Roth, Furquan Shaikh, Marshall Dawson, Andrey Petrov, Patrick Rudolph, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51575 ) Change subject: drivers/intel/fsp2_0/Kconfig: select HAVE_DISPLAY_MTRRS ...................................................................... Patch Set 2: (1 comment) File src/drivers/intel/fsp2_0/Kconfig: https://review.coreboot.org/c/coreboot/+/51575/comment/a2dcade9_ceb11413 PS2, Line 6: select HAVE_DISPLAY_MTRRS > no, a depends on isn't the right thing to do here, since the fsp driver itself provides some functionality to print the mtrrs, so we can unhide the option to print the mtrrs with selecting this option in the fsp driver's Kconfig. if some component provides certain functionality that has a kconfig option to show that the is implemented, that component needs to select that option Um, sorry, I don't follow. `HAVE_DISPLAY_MTRRS` is used to show/hide `DISPLAY_MTRRS`, Where exactly does the FSP driver provide functionality to print the MSRs? -- To view, visit https://review.coreboot.org/c/coreboot/+/51575 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2894689ce58e7404d9d5a894f3c288bc4016ea19 Gerrit-Change-Number: 51575 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 05 Sep 2021 23:10:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: Rename MMCONF Kconfigs to ECAM_MMCONF
by Furquan Shaikh (Code Review) 05 Sep '21

05 Sep '21

Attention is currently required from: Raul Rangel, Mariusz Szafrański, Jonathan Zhang, Paul Menzel, Stefan Reinauer, Kyösti Mälkki, Andrey Petrov, Patrick Rudolph, Nico Huber, Anjaneya "Reddy" Chagam, Johnny Lin, Suresh Bellampalli, Morgan Jang, Michal Motyl, Alexander Couzens, Felix Held, Shelley Chen, Lance Zhao, Jason Glenesk, Martin Roth, Damien Zammit, Lee Leahy, Marshall Dawson, Tim Wawrzynczak, Vanessa Eusebio, Huang Jin. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57333 ) Change subject: Rename MMCONF Kconfigs to ECAM_MMCONF ...................................................................... Patch Set 5: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/57333/comment/aa444f1b_5c470e16 PS4, Line 9: the MMCONF Kconfigs only use the Enhanced Configuration : Access mechanism (ECAM) method > The IO/MMIO distinction seems x86 specific to me, where we have two mechanisms concurrently. Agreed. > I'd say all other platforms simply need to implement some PCI OPS, without any special notion. They can use `device/pci_mmio_ops.h` for this, but don't have to. All other platforms need (some kind of) MMIO ops. How the config window mapping works is specific to the platform. If the platform follows PCI spec, then it uses ECAM and hence has the config window mapping all devices. Other platforms might have some kind of translation unit to setup the decoding for the required device and then access that at maybe some fixed address. So at the top-level the MMIO ops can stay the same, but they can allow the platforms to map and provide the address to use for performing read/write config. Patchset: PS5: > Can we please back up a little and discuss this on the mailing list first? […] +1. I think it would be good to outline the entire effort required for enabling PCI config access for non-x86 platforms and solidify on the design. It can act as good reference for both the author and the reviewers. I had talked to Shelley about this last week and she was planning to upload something to gerrit for this. -- To view, visit https://review.coreboot.org/c/coreboot/+/57333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2 Gerrit-Change-Number: 57333 Gerrit-PatchSet: 5 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Lance Zhao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Damien Zammit Gerrit-Attention: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Huang Jin <huang.jin(a)intel.com> Gerrit-Comment-Date: Sun, 05 Sep 2021 22:47:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard: Drop invalid `VGA_BIOS_FILE` defaults
by Michael Niewöhner (Code Review) 05 Sep '21

05 Sep '21

Attention is currently required from: Nico Huber, Martin Roth, Angel Pons, Arthur Heymans. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51340 ) Change subject: mainboard: Drop invalid `VGA_BIOS_FILE` defaults ...................................................................... Patch Set 4: (1 comment) Patchset: PS2: > There's also the question why the upstream community should maintain things that only work in combination with downstream additions, your overlays for instance. Full ACK. When stuff is only for downstream, then I see no reason to have it upstream. -- To view, visit https://review.coreboot.org/c/coreboot/+/51340 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b5dfba035a42d7943f270f95fb7d32b285584d2 Gerrit-Change-Number: 51340 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sun, 05 Sep 2021 21:12:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: Doc/Intel: Remove out-of-date documentation
by Michael Niewöhner (Code Review) 05 Sep '21

05 Sep '21

Attention is currently required from: Nico Huber, Angel Pons, Arthur Heymans, Patrick Rudolph. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57400 ) Change subject: Doc/Intel: Remove out-of-date documentation ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: +2 but let others have a look, too -- To view, visit https://review.coreboot.org/c/coreboot/+/57400 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If359f554e85d32cdb65c3d928b5155db30bc40a5 Gerrit-Change-Number: 57400 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 05 Sep 2021 21:09:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/supermicro: Add X9SAE and X9SAE-V
by Felix Held (Code Review) 05 Sep '21

05 Sep '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57191 ) Change subject: mb/supermicro: Add X9SAE and X9SAE-V ...................................................................... mb/supermicro: Add X9SAE and X9SAE-V Mainboard information can be found in the included documentation. Change-Id: I9dfc58bb99e14cd9dac2ac53afc0ea11d2252aa9 Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57191 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- A Documentation/mainboard/supermicro/x9sae.jpg A Documentation/mainboard/supermicro/x9sae.md A src/mainboard/supermicro/x9sae/Kconfig A src/mainboard/supermicro/x9sae/Kconfig.name A src/mainboard/supermicro/x9sae/Makefile.inc A src/mainboard/supermicro/x9sae/acpi/ec.asl A src/mainboard/supermicro/x9sae/acpi/pci.asl A src/mainboard/supermicro/x9sae/acpi/platform.asl A src/mainboard/supermicro/x9sae/acpi/superio.asl A src/mainboard/supermicro/x9sae/board_info.txt A src/mainboard/supermicro/x9sae/cmos.default A src/mainboard/supermicro/x9sae/cmos.layout A src/mainboard/supermicro/x9sae/data.vbt A src/mainboard/supermicro/x9sae/devicetree.cb A src/mainboard/supermicro/x9sae/dsdt.asl A src/mainboard/supermicro/x9sae/early_init.c A src/mainboard/supermicro/x9sae/gma-mainboard.ads A src/mainboard/supermicro/x9sae/gpio.c A src/mainboard/supermicro/x9sae/hda_verb.c A src/mainboard/supermicro/x9sae/mainboard.c 20 files changed, 786 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/Documentation/mainboard/supermicro/x9sae.jpg b/Documentation/mainboard/supermicro/x9sae.jpg new file mode 100644 index 0000000..def99e1 --- /dev/null +++ b/Documentation/mainboard/supermicro/x9sae.jpg Binary files differ diff --git a/Documentation/mainboard/supermicro/x9sae.md b/Documentation/mainboard/supermicro/x9sae.md new file mode 100644 index 0000000..ddc5ac7 --- /dev/null +++ b/Documentation/mainboard/supermicro/x9sae.md @@ -0,0 +1,108 @@ +# Supermicro X9SAE and X9SAE-V + +This page describes how to run coreboot on the Supermicro [X9SAE] and [X9SAE-V] + +## Flashing coreboot + +```eval_rst ++---------------------+----------------+ +| Type | Value | ++=====================+================+ +| Socketed flash | occasionally | ++---------------------+----------------+ +| Model | W25Q128FVSG | ++---------------------+----------------+ +| Size | 16 MiB | ++---------------------+----------------+ +| Package | SOIC-8 | ++---------------------+----------------+ +| Write protection | no | ++---------------------+----------------+ +| Dual BIOS feature | no | ++---------------------+----------------+ +| Internal flashing | yes | ++---------------------+----------------+ +``` + +The flash IC is located between the PCH and the front panel connector, +(circled) sometimes it is socketed. +![](x9sae.jpg) + +### How to flash + +Unlike ordinary desktop boards, the BIOS version 2.00 of X9SAE-V does not +apply any write protection, so the main SPI flash can be accessed using +[flashrom], and the whole flash is writable. + +Note: If you are going to modify the ME region via internal programming, you had +better disable ME functionalities as much as possible in the vendor firmware +first, otherwise ME may write something back and break the firmware you write. + +The following command may be used to flash coreboot. (To do so, linux kernel +could be started with `iomem=relaxed` or unload the `lpc_ich` kernel module) + +Now you can [flash internally](/flash_tutorial/int_flashrom.md). It is +recommended to flash only the `bios` region (use `--ifd -i bios -N` flashrom +arguments), in order to minimize the chances of messing something up in the +beginning. + +The flash chip is a SOIC-8 SPI flash, and may be socketed, so it's also easy +to do in-system programming, or remove and flash externally if it is socketed. + +## Difference between X9SAE and X9SAE-V +On X9SAE PCI-E slot 4 is absent. Lane 9~16 of PCI-E slot 6 on X9SAE are wired +to slot 4 on X9SAE-V. Unlike ASUS P8C WS, there is no dynamic switch on X9SAE-V, +so on X9SAE-V slot 6 can work as x8 at most. + +On X9SAE-V device pci 01.1 appears even if not defined in devicetree.cb, so it +seems that it shall not appear on X9SAE even if it is defined. + +## Working (on my X9SAE-V) +- Intel Xeon E3-1225 V2 with 4 M391B1G73BH0-YK0 UDIMMs, ECC confirmed active +- PS/2 keyboard with SeaBIOS 1.14.0 and Debian GNU/Linux with kernel 5.10.46 +- Use PS/2 keyboard and mouse simutaneously with a PS/2 Y-cable +- Both Onboard NIC +- S3 Suspend to RAM +- USB2 on rear and front panel connectors +- USB3 +- Integrated SATA +- CPU Temp sensors (tested PSensor on GNU/Linux) +- LPC TPM on TPM-header (tested tpm-tools with TPM 1.2 Infineon SLB9635TT12) +- Native raminit +- Integrated graphics with libgfxinit +- Nvidia Quadro 600 in all PCIe-16x slots +- Compex WLM200NX (Qualcomm Atheros AR9220) in PCI slot +- Debug output from serial port + +## Untested + +- EHCI debugging +- S/PDIF audio +- PS/2 mouse + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | ++------------------+--------------------------------------------------+ +| Southbridge | bd82x6x | ++------------------+--------------------------------------------------+ +| CPU | model_206ax | ++------------------+--------------------------------------------------+ +| Super I/O | Nuvoton NCT6776F | ++------------------+--------------------------------------------------+ +| EC | None | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+--------------------------------------------------+ +``` + +## Extra resources + +- [Flash chip datasheet][W25Q128FVSG] + +[X9SAE]: https://www.supermicro.com/products/motherboard/xeon/c216/x9sae.cfm +[X9SAE-V]: https://www.supermicro.com/products/motherboard/xeon/c216/x9sae-v.cfm +[W25Q128FVSG]: https://static.chipdip.ru/lib/093/DOC001093213.pdf +[flashrom]: https://flashrom.org/Flashrom diff --git a/src/mainboard/supermicro/x9sae/Kconfig b/src/mainboard/supermicro/x9sae/Kconfig new file mode 100644 index 0000000..4afe85e --- /dev/null +++ b/src/mainboard/supermicro/x9sae/Kconfig @@ -0,0 +1,31 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_SUPERMICRO_X9SAE + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_USES_IFD_GBE_REGION + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select SUPERIO_NUVOTON_NCT6776 + select USE_NATIVE_RAMINIT + +config MAINBOARD_DIR + string + default "supermicro/x9sae" + +config MAINBOARD_PART_NUMBER + string + default "X9SAE" + +endif diff --git a/src/mainboard/supermicro/x9sae/Kconfig.name b/src/mainboard/supermicro/x9sae/Kconfig.name new file mode 100644 index 0000000..566dce8 --- /dev/null +++ b/src/mainboard/supermicro/x9sae/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_SUPERMICRO_X9SAE + bool "X9SAE" diff --git a/src/mainboard/supermicro/x9sae/Makefile.inc b/src/mainboard/supermicro/x9sae/Makefile.inc new file mode 100644 index 0000000..5310efd --- /dev/null +++ b/src/mainboard/supermicro/x9sae/Makefile.inc @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += early_init.c +bootblock-y += gpio.c +romstage-y += early_init.c +romstage-y += gpio.c +ramstage-y += hda_verb.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/supermicro/x9sae/acpi/ec.asl b/src/mainboard/supermicro/x9sae/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/supermicro/x9sae/acpi/ec.asl diff --git a/src/mainboard/supermicro/x9sae/acpi/pci.asl b/src/mainboard/supermicro/x9sae/acpi/pci.asl new file mode 100644 index 0000000..72b497c --- /dev/null +++ b/src/mainboard/supermicro/x9sae/acpi/pci.asl @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +// Intel PCI to PCI bridge 0:1e.0 + +Device (PCIB) +{ + Name (_ADR, 0x001E0000) // _ADR: Address + Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake + + Method (_PRT) // _PRT: PCI Interrupt Routing Table + { + If (PICM) { + Return (Package() { + Package() { 0x0001ffff, 0, 0, 0x16 }, + Package() { 0x0001ffff, 1, 0, 0x15 }, + Package() { 0x0001ffff, 2, 0, 0x14 }, + Package() { 0x0001ffff, 3, 0, 0x13 }, + Package() { 0x0002ffff, 0, 0, 0x12 }, + Package() { 0x0002ffff, 1, 0, 0x13 }, + Package() { 0x0002ffff, 2, 0, 0x11 }, + Package() { 0x0002ffff, 3, 0, 0x10 }, + Package() { 0x0003ffff, 0, 0, 0x13 }, + Package() { 0x0003ffff, 1, 0, 0x12 }, + Package() { 0x0003ffff, 2, 0, 0x15 }, + Package() { 0x0003ffff, 3, 0, 0x16 }, + Package() { 0x0000ffff, 0, 0, 0x10 }, + Package() { 0x0000ffff, 1, 0, 0x11 }, + Package() { 0x0000ffff, 2, 0, 0x12 }, + Package() { 0x0000ffff, 3, 0, 0x13 }, + }) + } + Return (Package() { + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, + Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKE, 0 }, + Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x0003ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0003ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x0003ffff, 3, \_SB.PCI0.LPCB.LNKG, 0 }, + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + }) + } +} diff --git a/src/mainboard/supermicro/x9sae/acpi/platform.asl b/src/mainboard/supermicro/x9sae/acpi/platform.asl new file mode 100644 index 0000000..aff432b --- /dev/null +++ b/src/mainboard/supermicro/x9sae/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/supermicro/x9sae/acpi/superio.asl b/src/mainboard/supermicro/x9sae/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/supermicro/x9sae/acpi/superio.asl diff --git a/src/mainboard/supermicro/x9sae/board_info.txt b/src/mainboard/supermicro/x9sae/board_info.txt new file mode 100644 index 0000000..3ff778f --- /dev/null +++ b/src/mainboard/supermicro/x9sae/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.supermicro.com/products/motherboard/xeon/c216/x9sae.cfm +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: Occasionally +Flashrom support: y +Release year: 2012 diff --git a/src/mainboard/supermicro/x9sae/cmos.default b/src/mainboard/supermicro/x9sae/cmos.default new file mode 100644 index 0000000..c7aa620 --- /dev/null +++ b/src/mainboard/supermicro/x9sae/cmos.default @@ -0,0 +1,6 @@ +boot_option=Fallback +debug_level=Debug +nmi=Disable +power_on_after_fail=Disable +sata_mode=AHCI +gfx_uma_size=64M diff --git a/src/mainboard/supermicro/x9sae/cmos.layout b/src/mainboard/supermicro/x9sae/cmos.layout new file mode 100644 index 0000000..0f9de5e --- /dev/null +++ b/src/mainboard/supermicro/x9sae/cmos.layout @@ -0,0 +1,86 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 2 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 3 debug_level + +# coreboot config options: southbridge +408 1 e 1 nmi + +409 2 e 4 power_on_after_fail +411 2 e 5 sata_mode + +# coreboot config options: northbridge +416 5 e 6 gfx_uma_size + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations +#ID value text + +# Generic on/off enum +1 0 Disable +1 1 Enable + +# boot_option +2 0 Fallback +2 1 Normal + +# debug_level +3 0 Emergency +3 1 Alert +3 2 Critical +3 3 Error +3 4 Warning +3 5 Notice +3 6 Info +3 7 Debug +3 8 Spew + +# power_on_after_fail +4 0 Disable +4 1 Enable +4 2 Keep + +# sata_mode +5 0 AHCI +5 1 Compatible +5 2 Legacy + +# gfx_uma_size (Intel IGP Video RAM size) +6 0 32M +6 1 64M +6 2 96M +6 3 128M +6 4 160M +6 5 192M +6 6 224M +6 7 256M +6 8 288M +6 9 320M +6 10 352M +6 11 384M +6 12 416M +6 13 448M +6 14 480M +6 15 512M +6 16 1024M + +# ----------------------------------------------------------------- +checksums + +checksum 392 423 984 diff --git a/src/mainboard/supermicro/x9sae/data.vbt b/src/mainboard/supermicro/x9sae/data.vbt new file mode 100644 index 0000000..1a0d233 --- /dev/null +++ b/src/mainboard/supermicro/x9sae/data.vbt Binary files differ diff --git a/src/mainboard/supermicro/x9sae/devicetree.cb b/src/mainboard/supermicro/x9sae/devicetree.cb new file mode 100644 index 0000000..05a187e --- /dev/null +++ b/src/mainboard/supermicro/x9sae/devicetree.cb @@ -0,0 +1,125 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/sandybridge + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_power_cycle_delay" = "4" + device cpu_cluster 0 on + chip cpu/intel/model_206ax + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" + device lapic 0 on end + device lapic 0xacac off end + end + end + device domain 0 on + subsystemid 0x15d9 0x0644 inherit + + device pci 00.0 on end # Host bridge + device pci 01.0 on end # CPU1 SLOT6 (x8 or x16) + device pci 01.1 on end # CPU1 SLOT4 (electrical x8 in x16 if present) + device pci 02.0 on end # iGPU + device pci 06.0 on end # CPU1 SLOT7 (electrical x4 in x8) + + chip southbridge/intel/bd82x6x + register "gen1_dec" = "0x00fc0a01" # NCT6776 SuperIO (0x0a00-0aff) + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x3f" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" + + device pci 14.0 on end # xHCI + device pci 16.0 on end # MEI #1 + device pci 16.1 off end # MEI #2 + device pci 16.2 off end # ME IDE-R + device pci 16.3 off end # ME KT + device pci 19.0 on end # Intel GbE LAN1 + device pci 1a.0 on end # EHCI #2 + device pci 1b.0 on end # HD Audio + + device pci 1c.0 on end # RP #1 PCH SLOT2 + device pci 1c.1 off end # RP #2 + device pci 1c.2 off end # RP #3 + device pci 1c.3 off end # RP #4 + device pci 1c.4 on end # RP #5 PCH SLOT3 + device pci 1c.5 off end # RP #6 + device pci 1c.6 on end # RP #7 PCH SLOT5 + device pci 1c.7 on # RP #8 + device pci 00.0 on end # 574 GbE LAN2 + end + + device pci 1d.0 on end # EHCI #1 + device pci 1e.0 on end # PCI bridge + device pci 1f.0 on # LPC bridge + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # Parallel port + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # COM2, IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x060 + io 0x62 = 0x064 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6 + device pnp 2e.107 off end # GPIO7 + device pnp 2e.207 off end # GPIO8 + device pnp 2e.307 off end # GPIO9 + device pnp 2e.8 off end # WDT + device pnp 2e.108 on end # GPIO0 + device pnp 2e.208 off end # GPIOA + device pnp 2e.308 on # GPIOBASE + io 0x60 = 0xa00 + end + device pnp 2e.109 off end # GPIO1 + device pnp 2e.209 on end # GPIO2 + device pnp 2e.309 off end # GPIO3 + device pnp 2e.409 off end # GPIO4 + device pnp 2e.509 off end # GPIO5 + device pnp 2e.609 off end # GPIO6 + device pnp 2e.709 off end # GPIO7 + device pnp 2e.a on # ACPI + irq 0xe0 = 0 + irq 0xe4 = 0x60 + irq 0xe6 = 0x4c + irq 0xe7 = 0x10 + irq 0xf2 = 0x5d + end + device pnp 2e.b on # HWM, front panel LED + io 0x60 = 0xa30 + io 0x62 = 0xa80 + irq 0x70 = 0 + irq 0xf8 = 0x43 + end + device pnp 2e.d off end # VID + device pnp 2e.e off end # CIR WAKE-UP + device pnp 2e.f off end # GPIO + device pnp 2e.14 off end # SVID + device pnp 2e.16 off end # Deep sleep + device pnp 2e.17 off end # GPIOA + end + chip drivers/pc80/tpm + device pnp c31.0 on end # TPM + end + end + device pci 1f.2 on end # SATA (AHCI) + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/supermicro/x9sae/dsdt.asl b/src/mainboard/supermicro/x9sae/dsdt.asl new file mode 100644 index 0000000..77577de --- /dev/null +++ b/src/mainboard/supermicro/x9sae/dsdt.asl @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include <acpi/dsdt_top.asl> + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + #include "acpi/pci.asl" + } +} diff --git a/src/mainboard/supermicro/x9sae/early_init.c b/src/mainboard/supermicro/x9sae/early_init.c new file mode 100644 index 0000000..7e03212 --- /dev/null +++ b/src/mainboard/supermicro/x9sae/early_init.c @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <device/pnp_ops.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) +#define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI) + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin states */ + pnp_write_config(GLOBAL_DEV, 0x1a, 0xc8); + pnp_write_config(GLOBAL_DEV, 0x1b, 0x6d); + pnp_write_config(GLOBAL_DEV, 0x1c, 0x83); + pnp_write_config(GLOBAL_DEV, 0x24, 0x24); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x00); + pnp_write_config(GLOBAL_DEV, 0x2b, 0x02); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x80); + + /* Power RAM in S3 */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x10); + + pnp_set_logical_device(SERIAL_DEV); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + /* Enable UART */ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} diff --git a/src/mainboard/supermicro/x9sae/gma-mainboard.ads b/src/mainboard/supermicro/x9sae/gma-mainboard.ads new file mode 100644 index 0000000..8b07c07 --- /dev/null +++ b/src/mainboard/supermicro/x9sae/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + HDMI2, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/supermicro/x9sae/gpio.c b/src/mainboard/supermicro/x9sae/gpio.c new file mode 100644 index 0000000..6cb163f --- /dev/null +++ b/src/mainboard/supermicro/x9sae/gpio.c @@ -0,0 +1,190 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_OUTPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio14 = GPIO_LEVEL_LOW, + .gpio21 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio1 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio44 = GPIO_DIR_OUTPUT, + .gpio45 = GPIO_DIR_OUTPUT, + .gpio46 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_HIGH, + .gpio44 = GPIO_LEVEL_HIGH, + .gpio45 = GPIO_LEVEL_HIGH, + .gpio46 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/supermicro/x9sae/hda_verb.c b/src/mainboard/supermicro/x9sae/hda_verb.c new file mode 100644 index 0000000..5feb741 --- /dev/null +++ b/src/mainboard/supermicro/x9sae/hda_verb.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0889, /* Codec Vendor / Device ID: Realtek */ + 0x15d90644, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x15d90644), + AZALIA_PIN_CFG(0, 0x11, 0x18561120), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x01011012), + AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19840), + AZALIA_PIN_CFG(0, 0x19, 0x02a19841), + AZALIA_PIN_CFG(0, 0x1a, 0x0181344f), + AZALIA_PIN_CFG(0, 0x1b, 0x0221401f), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4007e619), + AZALIA_PIN_CFG(0, 0x1e, 0x01452130), + AZALIA_PIN_CFG(0, 0x1f, 0x01c41150), + + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x58560010), + AZALIA_PIN_CFG(3, 0x06, 0x18560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/supermicro/x9sae/mainboard.c b/src/mainboard/supermicro/x9sae/mainboard.c new file mode 100644 index 0000000..4322c1e --- /dev/null +++ b/src/mainboard/supermicro/x9sae/mainboard.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> + +static void mainboard_enable(struct device *dev) +{ + /* FIXME: fix these values. */ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/57191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9dfc58bb99e14cd9dac2ac53afc0ea11d2252aa9 Gerrit-Change-Number: 57191 Gerrit-PatchSet: 15 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jonathan Kollasch <jakllsch(a)kollasch.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/supermicro: Add X9SAE and X9SAE-V
by Felix Held (Code Review) 05 Sep '21

05 Sep '21

Attention is currently required from: Bill XIE, Jonathan Kollasch, Paul Menzel, Angel Pons. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57191 ) Change subject: mb/supermicro: Add X9SAE and X9SAE-V ...................................................................... Patch Set 14: Code-Review+2 (1 comment) Patchset: PS14: looks good to me and i'd say that this is sufficiently different to the other supermicro board from the same generation to not make this a variant -- To view, visit https://review.coreboot.org/c/coreboot/+/57191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9dfc58bb99e14cd9dac2ac53afc0ea11d2252aa9 Gerrit-Change-Number: 57191 Gerrit-PatchSet: 14 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jonathan Kollasch <jakllsch(a)kollasch.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Jonathan Kollasch <jakllsch(a)kollasch.net> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sun, 05 Sep 2021 20:37:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: guybrush/variants/baseboard/devicetree.cb
by Felix Held (Code Review) 05 Sep '21

05 Sep '21

Attention is currently required from: Angel Pons, Name of user not set #1003801, Julian Schroeder. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57215 ) Change subject: guybrush/variants/baseboard/devicetree.cb ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > yeah, since that's needed for every mainboard that has usb_phy_custom set to 1, we should set those […] i would also be ok with submitting this patch for now, but opening an internal ticket to rework this to have this set in the soc code -- To view, visit https://review.coreboot.org/c/coreboot/+/57215 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4fdb5af1cbc3c70cc113ef6f0fd9332e1a27f142 Gerrit-Change-Number: 57215 Gerrit-PatchSet: 2 Gerrit-Owner: Name of user not set #1003801 Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Name of user not set #1003801 Gerrit-Attention: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Comment-Date: Sun, 05 Sep 2021 20:25:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: guybrush/variants/baseboard/devicetree.cb
by Felix Held (Code Review) 05 Sep '21

05 Sep '21

Attention is currently required from: Angel Pons, Name of user not set #1003801, Julian Schroeder. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57215 ) Change subject: guybrush/variants/baseboard/devicetree.cb ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Patchset: PS2: > Why are these IDs not programmed in SoC code? yeah, since that's needed for every mainboard that has usb_phy_custom set to 1, we should set those values in the soc code instead to not have to specify those same constants in every mainboard -- To view, visit https://review.coreboot.org/c/coreboot/+/57215 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4fdb5af1cbc3c70cc113ef6f0fd9332e1a27f142 Gerrit-Change-Number: 57215 Gerrit-PatchSet: 2 Gerrit-Owner: Name of user not set #1003801 Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Name of user not set #1003801 Gerrit-Attention: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Comment-Date: Sun, 05 Sep 2021 20:20:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/include/lpc: add definitions for LPC LDRQ control bits
by Felix Held (Code Review) 05 Sep '21

05 Sep '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55294 ) Change subject: soc/amd/common/include/lpc: add definitions for LPC LDRQ control bits ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/common/block/include/amdblocks/lpc.h: https://review.coreboot.org/c/coreboot/+/55294/comment/fb0a05c5_6c0b30a6 PS1, Line 108: LPC_LDRQ0_PD_EN > most likely scenario is that the cezanne ppr is wrong on those two bits; at least what the reference […] i was told that the cezanne ppr matches what's in the cezanne hardware design. not sure yet if the picasso ppr is wrong on this -- To view, visit https://review.coreboot.org/c/coreboot/+/55294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a033d63eeb06eed6783e4c3797ad8dea490db8d Gerrit-Change-Number: 55294 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Sun, 05 Sep 2021 20:17:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/drawcia: change LTE reset pin to GPP_H17
by 9elements QA (Code Review) 05 Sep '21

05 Sep '21

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57204 ) Change subject: mb/google/dedede/var/drawcia: change LTE reset pin to GPP_H17 ...................................................................... Patch Set 5: Automatic boot test returned (PASS/FAIL/TOTAL): 12 / 1 / 13 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/76112 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/76111 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/76110 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/76109 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/76108 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/76107 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/76106 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/76105 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/76104 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/76103 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/76102 FAIL: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/76101 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/76100 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/57204 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib65580babf7d21535df2bd8d33bb19261bebfe15 Gerrit-Change-Number: 57204 Gerrit-PatchSet: 5 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Sun, 05 Sep 2021 20:16:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit September 2021