coreboot-gerrit September 2021

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Change in coreboot[master]: soc/intel/alderlake: Enable Irms UPD for ADL
by V Sowmya (Code Review) 06 Sep '21

06 Sep '21

Attention is currently required from: Maulik V Vaghela, Paul Menzel, Tim Wawrzynczak, Subrata Banik, Vinay Kumar, Balaji Manigandan, Kane Chen, Ronak Kanabar, Srinidhi N Kaushik, Patrick Rudolph. V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56330 ) Change subject: soc/intel/alderlake: Enable Irms UPD for ADL ...................................................................... Patch Set 14: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56330 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice5c775ef9560503109957a1ed994af1d287aafc Gerrit-Change-Number: 56330 Gerrit-PatchSet: 14 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 06 Sep 2021 09:31:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: kontron/mal10: Set up GPIOs in CPLD/EC
by Nico Huber (Code Review) 06 Sep '21

06 Sep '21

Attention is currently required from: Maxim Polyakov, Paul Menzel. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54380 ) Change subject: kontron/mal10: Set up GPIOs in CPLD/EC ...................................................................... Patch Set 14: Code-Review+2 (1 comment) Patchset: PS14: Not sure anymore why I only gave a +1... -- To view, visit https://review.coreboot.org/c/coreboot/+/54380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d354aa32ac8c64f54b2bcbdb4f1b8915f55264e Gerrit-Change-Number: 54380 Gerrit-PatchSet: 14 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 06 Sep 2021 09:25:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Enable Irms UPD for ADL
by Ronak Kanabar (Code Review) 06 Sep '21

06 Sep '21

Attention is currently required from: V Sowmya, Maulik V Vaghela, Paul Menzel, Tim Wawrzynczak, Subrata Banik, Vinay Kumar, Balaji Manigandan, Kane Chen, Srinidhi N Kaushik, Patrick Rudolph. Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56330 ) Change subject: soc/intel/alderlake: Enable Irms UPD for ADL ...................................................................... Patch Set 14: (1 comment) File src/soc/intel/alderlake/vr_config.c: https://review.coreboot.org/c/coreboot/+/56330/comment/cd02ebdb_88cbbd05 PS13, Line 118: s_cfg->Irms[domain] = 1; > Can we update this with same logic as TdcEnable since this is also related to updating of TdcTimeWin […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/56330 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice5c775ef9560503109957a1ed994af1d287aafc Gerrit-Change-Number: 56330 Gerrit-PatchSet: 14 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 06 Sep 2021 09:17:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: V Sowmya <v.sowmya(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Enable Irms UPD for ADL
by Ronak Kanabar (Code Review) 06 Sep '21

06 Sep '21

Attention is currently required from: Maulik V Vaghela, Paul Menzel, Tim Wawrzynczak, Subrata Banik, Vinay Kumar, Balaji Manigandan, Kane Chen, Ronak Kanabar, Srinidhi N Kaushik, Patrick Rudolph. Hello V Sowmya, build bot (Jenkins), Maulik V Vaghela, Tim Wawrzynczak, Sridhar Siricilla, Vinay Kumar, Subrata Banik, Balaji Manigandan, Kane Chen, Srinidhi N Kaushik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56330 to look at the new patch set (#14). Change subject: soc/intel/alderlake: Enable Irms UPD for ADL ...................................................................... soc/intel/alderlake: Enable Irms UPD for ADL This change sets Irms config in FSP if TdcTimeWindow and TdcCurrentLimit is set to non zero. It results VR TDC Input current to be treated as it is root mean square. This change also optimize the check of TdcTimeWindow and TdcCurrentLimit for TdcEnable UPD. BRANCH=None TEST=Build and boot brya with debug FSP and verify Irms UPD value from logs Change-Id: Ice5c775ef9560503109957a1ed994af1d287aafc Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/soc/intel/alderlake/vr_config.c 1 file changed, 8 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/56330/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/56330 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice5c775ef9560503109957a1ed994af1d287aafc Gerrit-Change-Number: 56330 Gerrit-PatchSet: 14 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: arch/x86: Refactor the SMBIOS type 17 write function
by Subrata Banik (Code Review) 06 Sep '21

06 Sep '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Tim Wawrzynczak, Subrata Banik, Angel Pons, Patrick Rudolph, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Furquan Shaikh, Marshall Dawson, Tim Wawrzynczak, Angel Pons, Patrick Rudolph, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56628 to look at the new patch set (#13). Change subject: arch/x86: Refactor the SMBIOS type 17 write function ...................................................................... arch/x86: Refactor the SMBIOS type 17 write function List of changes: 1. Create Module Type macros as per Memory Type (i.e. DDR2/DDR3/DDR4/DDR5/LPDDR4/LPDDR5) and fix compilation issue due to renaming of existing macros due to scoping the Memory Type. 2. Skip fixed module type to form factor conversion using DDR2 SPD4 specification (inside dimm_info_fill()). 3. Use dedicated Memory Type and Module type for `Form Factor` conversion using `get_spd_info()` function. 4. Use dedicated Memory Type and Module type for `TypeDetail` conversion using `get_spd_info()` function. 5. Create a new API (convert_form_factor_to_module_type()) for `Form Factor` to 'Module type' conversion as per `Memory Type`. 6. Add DDR5 and LPDDR5 memory technology into the SMBIOS Memory Type table. 7. Add new argument as `Memory Type` smbios_form_factor_to_spd_mod_type(). 8. smbios_form_factor_to_spd_mod_type() internally calls convert_form_factor_to_module_type() for `Module Type` conversion. 9. Update `test_smbios_form_factor_to_spd_mod_type()` to accommodate different memory types. Refer to datasheet SPD4.1.2.M-1 for LPDDRx and SPD4.1.2.L-3 for DDRx. BUG=b:194659789 TEST=Refer to dmidecode -t 17 output as below: Without this code change: Handle 0x0012, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 16 bits Data Width: 16 bits Size: 2048 MB Form Factor: Unknown .... With this code change: Handle 0x0012, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 16 bits Data Width: 16 bits Size: 2048 MB Form Factor: Row Of Chips .... Change-Id: Ia337ac8f50b61ae78d86a07c7a86aa9c248bad50 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/arch/x86/smbios.c M src/device/dram/ddr3.c M src/device/dram/ddr4.c M src/device/dram/spd.c M src/include/device/dram/spd.h M src/include/dimm_info_util.h M src/include/smbios.h M src/include/spd.h M src/lib/dimm_info_util.c M src/mainboard/scaleway/tagada/ramstage.c M src/northbridge/intel/haswell/haswell_mrc/raminit.c M src/soc/amd/common/block/pi/amd_late_init.c M src/soc/amd/common/fsp/dmi.c M src/soc/intel/common/smbios.c M tests/lib/dimm_info_util-test.c 15 files changed, 441 insertions(+), 111 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/56628/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/56628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia337ac8f50b61ae78d86a07c7a86aa9c248bad50 Gerrit-Change-Number: 56628 Gerrit-PatchSet: 13 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Enable Irms UPD for ADL
by V Sowmya (Code Review) 06 Sep '21

06 Sep '21

Attention is currently required from: Maulik V Vaghela, Paul Menzel, Tim Wawrzynczak, Subrata Banik, Vinay Kumar, Balaji Manigandan, Kane Chen, Ronak Kanabar, Srinidhi N Kaushik, Patrick Rudolph. V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56330 ) Change subject: soc/intel/alderlake: Enable Irms UPD for ADL ...................................................................... Patch Set 13: (1 comment) File src/soc/intel/alderlake/vr_config.c: https://review.coreboot.org/c/coreboot/+/56330/comment/09be8d8d_445a46fd PS13, Line 118: s_cfg->Irms[domain] = 1; Can we update this with same logic as TdcEnable since this is also related to updating of TdcTimeWindow and TdcCurrentLimit? -- To view, visit https://review.coreboot.org/c/coreboot/+/56330 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice5c775ef9560503109957a1ed994af1d287aafc Gerrit-Change-Number: 56330 Gerrit-PatchSet: 13 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 06 Sep 2021 08:38:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/cret: Update DPTF parameters
by Dtrain Hsu (Code Review) 06 Sep '21

06 Sep '21

Dtrain Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/57404 ) Change subject: mb/google/dedede/var/cret: Update DPTF parameters ...................................................................... mb/google/dedede/var/cret: Update DPTF parameters Update DPTF parameters from internal thermal team and Intel suggestion. BUG=b:198249129 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: I25d3909144d6e38d7a6eb859d33585c319a84b04 --- M src/mainboard/google/dedede/variants/cret/overridetree.cb 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/57404/1 diff --git a/src/mainboard/google/dedede/variants/cret/overridetree.cb b/src/mainboard/google/dedede/variants/cret/overridetree.cb index 9dba696..dc22d67 100644 --- a/src/mainboard/google/dedede/variants/cret/overridetree.cb +++ b/src/mainboard/google/dedede/variants/cret/overridetree.cb @@ -76,9 +76,9 @@ ## Critical Policy register "policies.critical" = "{ - [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), - [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN), - [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN) + [0] = DPTF_CRITICAL(CPU, 120, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 120, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 120, SHUTDOWN) }" ## Power Limits Control -- To view, visit https://review.coreboot.org/c/coreboot/+/57404 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25d3909144d6e38d7a6eb859d33585c319a84b04 Gerrit-Change-Number: 57404 Gerrit-PatchSet: 1 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: documentation: add a section on devicetree refs
by Angel Pons (Code Review) 06 Sep '21

06 Sep '21

Attention is currently required from: Peter Marheine. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57354 ) Change subject: documentation: add a section on devicetree refs ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57354 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b30f7d531cfc3453d6523a76084f1969125b4bf Gerrit-Change-Number: 57354 Gerrit-PatchSet: 3 Gerrit-Owner: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Comment-Date: Mon, 06 Sep 2021 07:52:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Change VBOOT_HASH_BLOCK_SIZE to 4 KiB
by Maulik V Vaghela (Code Review) 06 Sep '21

06 Sep '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Ronak Kanabar, Patrick Rudolph. Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57141 ) Change subject: soc/intel/alderlake: Change VBOOT_HASH_BLOCK_SIZE to 4 KiB ...................................................................... Patch Set 5: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/57141/comment/b538cd21_58832bdd PS3, Line 13: Increasing it over 4 KiB doesn't result in significant improvement, > Sorry Furquan, I was on leave so couldn't update. […] Done https://review.coreboot.org/c/coreboot/+/57141/comment/84466ef7_4cb1fecf PS3, Line 16: None > Probably add the boot time bug here? It would be helpful when looking at all the optimizations that […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/57141 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9222761c7d58e4a370d3a41c651b6c169599d792 Gerrit-Change-Number: 57141 Gerrit-PatchSet: 5 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 06 Sep 2021 06:34:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Change VBOOT_HASH_BLOCK_SIZE to 4 KiB
by Maulik V Vaghela (Code Review) 06 Sep '21

06 Sep '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Ronak Kanabar, Patrick Rudolph. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Ronak Kanabar, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57141 to look at the new patch set (#5). Change subject: soc/intel/alderlake: Change VBOOT_HASH_BLOCK_SIZE to 4 KiB ...................................................................... soc/intel/alderlake: Change VBOOT_HASH_BLOCK_SIZE to 4 KiB Default VBOOT_HASH_BLOCK_SIZE is 1 KiB and increasing it to 4 KiB helps in improving overall boot time since it reduces hashing and body loading time. Increasing it over 4 KiB doesn't result in significant improvement, thus keeping the value at 4 KiB as of now. Timing data: Note that before Data is with 1 KiB block size. |------------------------------------------------------| | Stage | Block Size | Before | After | |finished loading body| 4 KiB | 205,187 | 189,947 | |finished loading body| 8 KiB | 205,187 | 188,708 | |finished loading body| 16 KiB | 205,187 | 188,085 | |finished loading body| 32 KiB | 205,187 | 187,793 | |------------------------------------------------------| BUG=b:188577893 BRANCH=None TEST=Boot time for Brya improves by 20 - 25 msec Change-Id: I9222761c7d58e4a370d3a41c651b6c169599d792 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/alderlake/Kconfig 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/57141/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/57141 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9222761c7d58e4a370d3a41c651b6c169599d792 Gerrit-Change-Number: 57141 Gerrit-PatchSet: 5 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit September 2021