coreboot-gerrit September 2021

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Change in coreboot[master]: mb/google/volteer: Modify APIs for USB-C DP alternate mode support sr...
by Curtis Chen (Code Review) 05 Sep '21

05 Sep '21

Curtis Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/57402 ) Change subject: mb/google/volteer: Modify APIs for USB-C DP alternate mode support src/ec/google/chromeec: Modify APIs for USB-C DP ALT mode ...................................................................... mb/google/volteer: Modify APIs for USB-C DP alternate mode support src/ec/google/chromeec: Modify APIs for USB-C DP ALT mode 1. The API now would delay N seconds if N ports are connected with non-DP mode device. Let them wait in parrlel in 1 second. 2. Get the DP mode port directly. 3. Keep the original API format, no need to modify old project. BUG=b:192947843 TEST=select ENABLE_TCSS_DISPLAY_DETECTION in Kconfig.name. Build coreboot and update your system. Boot the system, external display connected on USB-C port should show screen in developer mode or recovery mode Change-Id: If2a49336754648ecb2f62d26e68ce04a367adc39 Signed-off-by: Curtis Chen <curtis.chen(a)intel.com> --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h M src/mainboard/google/fizz/mainboard.c M src/mainboard/google/hatch/variants/baseboard/mainboard.c M src/mainboard/google/volteer/mainboard.c M src/soc/intel/common/block/tcss/tcss.c 6 files changed, 38 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/57402/1 diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index ce6d559..91c9692 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -1564,10 +1564,9 @@ * Check if EC/TCPM is in an alternate mode or not. * * @param svid SVID of the alternate mode to check - * @param port port number to check, -1 means check all port * @return 0: Not in the mode. -1: Error. 1: Yes. */ -int google_chromeec_pd_get_amode(uint16_t svid, int port) +int google_chromeec_pd_get_amode(uint16_t svid) { struct ec_response_usb_pd_ports resp; struct chromeec_command cmd = { @@ -1589,8 +1588,6 @@ struct ec_params_usb_pd_get_mode_response resp2; int svid_idx = 0; - if (port >= 0 && i != port) - continue; do { /* Reset cmd in each iteration in case google_chromeec_command changes it. */ @@ -1607,7 +1604,7 @@ if (google_chromeec_command(&cmd) < 0) return -1; if (resp2.svid == svid) - return 1; + return (1 << i); svid_idx++; } while (resp2.svid); } @@ -1621,16 +1618,20 @@ * Wait for DisplayPort to be ready * * @param timeout Wait aborts after <timeout> ms. - * @param port Wait for the specific port, -1 means wait for all ports * @return 1: Success or 0: Timeout. */ -int google_chromeec_wait_for_displayport(long timeout, int port) +int google_chromeec_wait_for_displayport(long timeout) { struct stopwatch sw; + int ret = 0; printk(BIOS_INFO, "Waiting for DisplayPort\n"); stopwatch_init_msecs_expire(&sw, timeout); - while (google_chromeec_pd_get_amode(USB_SID_DISPLAYPORT, port) != 1) { + while (1) { + ret = google_chromeec_pd_get_amode(USB_SID_DISPLAYPORT); + if (ret > 0) + break; + if (stopwatch_expired(&sw)) { printk(BIOS_WARNING, "DisplayPort not ready after %ldms. Abort.\n", @@ -1642,7 +1643,7 @@ printk(BIOS_INFO, "DisplayPort ready after %lu ms\n", stopwatch_duration_msecs(&sw)); - return 1; + return ret; } int google_chromeec_get_keybd_config(struct ec_response_keybd_config *keybd) diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 6170810..e4b8234 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -26,7 +26,7 @@ int google_ec_running_ro(void); enum ec_image google_chromeec_get_current_image(void); void google_chromeec_init(void); -int google_chromeec_pd_get_amode(uint16_t svid, int port); +int google_chromeec_pd_get_amode(uint16_t svid); /* Check for the current mux state in EC * in: int port physical port number of the type-c port * out: uint8_t flags representing the status of the mux such as @@ -36,7 +36,7 @@ /* Returns data role and type of device connected */ int google_chromeec_usb_pd_control(int port, bool *ufp, bool *dbg_acc, uint8_t *dp_mode); -int google_chromeec_wait_for_displayport(long timeout, int port); +int google_chromeec_wait_for_displayport(long timeout); int google_chromeec_typec_control_enter_dp_mode(int port); /* Device events */ diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index 74bca2b..0945b9c 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -259,7 +259,7 @@ gpio_input(GPIO_HDMI_HPD); if (display_init_required() && !gpio_get(GPIO_HDMI_HPD)) { /* This has to be done before FSP-S runs. */ - if (google_chromeec_wait_for_displayport(display_timeout_ms, -1)) + if (google_chromeec_wait_for_displayport(display_timeout_ms)) wait_for_hpd(GPIO_DP_HPD, display_timeout_ms); } } diff --git a/src/mainboard/google/hatch/variants/baseboard/mainboard.c b/src/mainboard/google/hatch/variants/baseboard/mainboard.c index eaf34b7..d641405 100644 --- a/src/mainboard/google/hatch/variants/baseboard/mainboard.c +++ b/src/mainboard/google/hatch/variants/baseboard/mainboard.c @@ -161,7 +161,7 @@ && !gpio_get(GPIO_HDMI_HPD) && !gpio_get(GPIO_DP_HPD)) { /* This has to be done before FSP-S runs. */ - if (google_chromeec_wait_for_displayport(display_timeout_ms, -1)) + if (google_chromeec_wait_for_displayport(display_timeout_ms)) wait_for_hpd(GPIO_DP_HPD, display_timeout_ms); } /* Psys_pmax needs to be setup before FSP-S */ diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index 4192da3..d8285f8 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -147,24 +147,30 @@ } } -const int mainboard_tcss_wait_for_displayport(int port, long timeout) +const int mainboard_tcss_wait_for_displayport(int num_ports, long timeout) { - int ret; + int ret = 0, i; uint8_t mux_flags; - if ((ret = google_chromeec_usb_get_pd_mux_info(port, &mux_flags)) < 0) { - printk(BIOS_ERR, "port C%d: get_pd_mux_info failed\n", port); - return ret; + for (i = 0; i < num_ports; i++) { + if ((ret = google_chromeec_usb_get_pd_mux_info(i, &mux_flags)) < 0) { + printk(BIOS_ERR, "port C%d: get_pd_mux_info failed\n", i); + continue; + } + + if (mux_flags) /* If port is connected */ + break; } - ret = 0; - if (mux_flags) /* If port is connected */ - if ((ret = google_chromeec_wait_for_displayport(timeout, port))) - printk(BIOS_INFO, "port C%d: DispalyPort detected\n", port); + + if (i != num_ports) {/* If port is connected */ + ret = google_chromeec_wait_for_displayport(timeout); + if (ret < 1) + printk(BIOS_INFO, "No DisplayPort detected\n"); else - printk(BIOS_INFO, "port C%d: No DisplayPort detected\n", port); - else - printk(BIOS_INFO, "port C%d: Nothing is connected\n", port); + printk(BIOS_INFO, "port index 0x%x: DispalyPort detected\n", ret); + } else + printk(BIOS_INFO, "Nothing is connected\n"); return ret; } diff --git a/src/soc/intel/common/block/tcss/tcss.c b/src/soc/intel/common/block/tcss/tcss.c index 40ab418..ab73265 100644 --- a/src/soc/intel/common/block/tcss/tcss.c +++ b/src/soc/intel/common/block/tcss/tcss.c @@ -284,7 +284,7 @@ static void tcss_configure_dp_mode(const struct tcss_port_map *port_map, size_t num_ports) { - int ret; + int ret, alt_ret; size_t i; const struct tcss_mux_info *mux_info; const struct tcss_port_map *port_info; @@ -292,8 +292,12 @@ if (!display_init_required()) return; + alt_ret = mainboard_tcss_wait_for_displayport(num_ports, WAIT_FOR_DISPLAYPORT_TIMEOUT); + if (!alt_ret) + return; + for (i = 0; i < num_ports; i++) { - if (mainboard_tcss_wait_for_displayport(i, WAIT_FOR_DISPLAYPORT_TIMEOUT) == 0) + if (!(alt_ret & 1 << i)) continue; mainboard_tcss_enter_dp_mode(i); if (mainboard_tcss_wait_for_hpd(i, WAIT_FOR_HPD_TIMEOUT) == 0) -- To view, visit https://review.coreboot.org/c/coreboot/+/57402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2a49336754648ecb2f62d26e68ce04a367adc39 Gerrit-Change-Number: 57402 Gerrit-PatchSet: 1 Gerrit-Owner: Curtis Chen <curtis.chen(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/ec/google/chromeec: Add and modify APIs for USB-C DP ALT mode
by Curtis Chen (Code Review) 05 Sep '21

05 Sep '21

Attention is currently required from: Furquan Shaikh, Derek Huang, Brandon Breitenstein, Curtis Chen. Curtis Chen has uploaded a new patch set (#8) to the change originally created by Derek Huang. ( https://review.coreboot.org/c/coreboot/+/57138 ) Change subject: src/ec/google/chromeec: Add and modify APIs for USB-C DP ALT mode ...................................................................... src/ec/google/chromeec: Add and modify APIs for USB-C DP ALT mode Add API to allow AP to send the direction to EC to enter DP ALT mode when EC supports EC_FEATURE_TYPEC_REQUIRE_AP_MODE_ENTRY. Add API to clear PD_STATUS_EVENT event. Modify some APIs to get information for specified port. BUG=b:192947843 Signed-off-by: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Change-Id: Id11510c1ff58579ae2cddfe5a4d69646fd84f5c3 --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h M src/mainboard/google/fizz/mainboard.c M src/mainboard/google/hatch/variants/baseboard/mainboard.c 4 files changed, 36 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/57138/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/57138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id11510c1ff58579ae2cddfe5a4d69646fd84f5c3 Gerrit-Change-Number: 57138 Gerrit-PatchSet: 8 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Curtis Chen <curtis.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Attention: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/volteer/var/chronicler: change GPP_A8 pin define
by Sheng-Liang Pan (Code Review) 05 Sep '21

05 Sep '21

Attention is currently required from: YH Lin, Furquan Shaikh, Isaac Lee, Tim Wawrzynczak, Paul Menzel, Nick Vaccaro. Sheng-Liang Pan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57103 ) Change subject: mb/google/volteer/var/chronicler: change GPP_A8 pin define ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/57103/comment/7c3d6efe_8d8b6fcc PS3, Line 14: no corrupt with touchscreen. > Sorry, I don't understand what this means? see b:197668845 -- To view, visit https://review.coreboot.org/c/coreboot/+/57103 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a0c1d0afafb2c446fcb3d18e1a67573218614e8 Gerrit-Change-Number: 57103 Gerrit-PatchSet: 4 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Isaac Lee <isaaclee(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 06 Sep 2021 02:39:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/gimble: Enable SaGv support
by Mark Hsieh (Code Review) 05 Sep '21

05 Sep '21

Attention is currently required from: YH Lin, Tim Wawrzynczak, Paul Menzel, Kane Chen, Felix Held. Mark Hsieh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57357 ) Change subject: mb/google/brya/variants/gimble: Enable SaGv support ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/57357/comment/6813f86f_34ff13c5 PS2, Line 9: This patch enables SaGv support for gimble. > Have you boot tested it? Hi Tim, Yes, we have tested RMT, the test results all passed. https://partnerissuetracker.corp.google.com/issues/190688567#comment28 -- To view, visit https://review.coreboot.org/c/coreboot/+/57357 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29887418827614afb10558c6958c9c5e9667079e Gerrit-Change-Number: 57357 Gerrit-PatchSet: 2 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Marx Wang <marx.wang(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 06 Sep 2021 02:37:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: lib/edid_fill_fb: Make framebuffer orientation to be configurable
by shkim (Code Review) 05 Sep '21

05 Sep '21

Attention is currently required from: Nico Huber, Paul Menzel, SH Kim, Julius Werner, Yu-Ping Wu, Karthik Ramasubramanian. shkim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57327 ) Change subject: lib/edid_fill_fb: Make framebuffer orientation to be configurable ...................................................................... Patch Set 4: (1 comment) Patchset: PS2: > I agree the existing API was better. I think we can have two mechanisms […] Okay guys. I don't have DUT in my hand now, I'll try and verify your suggestion in a few days.. Thanks. - Adding lb_get_first_framebuffer() into lib/edid_fill_fb.c - Adding adjusting orientation in mainboard_dev->final() using lb_get_first_framebuffer() -- To view, visit https://review.coreboot.org/c/coreboot/+/57327 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice7f7ab66e40d19c76fbf5876e7d4d3e3b2088fa Gerrit-Change-Number: 57327 Gerrit-PatchSet: 4 Gerrit-Owner: shkim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 06 Sep 2021 01:49:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: shkim <sh_.kim(a)samsung.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: documentation: add a section on devicetree refs
by Edward O'Callaghan (Code Review) 05 Sep '21

05 Sep '21

Attention is currently required from: Angel Pons, Peter Marheine. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57354 ) Change subject: documentation: add a section on devicetree refs ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57354 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b30f7d531cfc3453d6523a76084f1969125b4bf Gerrit-Change-Number: 57354 Gerrit-PatchSet: 3 Gerrit-Owner: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Comment-Date: Mon, 06 Sep 2021 01:37:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: documentation: add a section on devicetree refs
by Peter Marheine (Code Review) 05 Sep '21

05 Sep '21

Attention is currently required from: Edward O'Callaghan, Angel Pons. Peter Marheine has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57354 ) Change subject: documentation: add a section on devicetree refs ...................................................................... Patch Set 3: (1 comment) File Documentation/acpi/devicetree.md: https://review.coreboot.org/c/coreboot/+/57354/comment/ed107567_5823e15f PS2, Line 23: & > I'd much prefer to spell out `and` here. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/57354 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b30f7d531cfc3453d6523a76084f1969125b4bf Gerrit-Change-Number: 57354 Gerrit-PatchSet: 3 Gerrit-Owner: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 06 Sep 2021 01:12:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: documentation: add a section on devicetree refs
by Peter Marheine (Code Review) 05 Sep '21

05 Sep '21

Attention is currently required from: Edward O'Callaghan, Peter Marheine. Hello build bot (Jenkins), Furquan Shaikh, Edward O'Callaghan, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57354 to look at the new patch set (#3). Change subject: documentation: add a section on devicetree refs ...................................................................... documentation: add a section on devicetree refs There is no existing documentation on how `device ref` and aliases work in the devicetree, and the behavior around devices not being in the same location is difficult to discern as well as somewhat unexpected. This should help prevent confusion leading to bugs such as the one fixed by https://review.coreboot.org/c/coreboot/+/57298 Change-Id: I4b30f7d531cfc3453d6523a76084f1969125b4bf Signed-off-by: Peter Marheine <pmarheine(a)chromium.org> --- M Documentation/acpi/devicetree.md 1 file changed, 56 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/57354/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/57354 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b30f7d531cfc3453d6523a76084f1969125b4bf Gerrit-Change-Number: 57354 Gerrit-PatchSet: 3 Gerrit-Owner: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: guybrush/variants/baseboard/devicetree.cb
by Angel Pons (Code Review) 05 Sep '21

05 Sep '21

Attention is currently required from: Name of user not set #1003801, Julian Schroeder, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57215 ) Change subject: guybrush/variants/baseboard/devicetree.cb ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > i would also be ok with submitting this patch for now, but opening an internal ticket to rework this […] SGTM -- To view, visit https://review.coreboot.org/c/coreboot/+/57215 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4fdb5af1cbc3c70cc113ef6f0fd9332e1a27f142 Gerrit-Change-Number: 57215 Gerrit-PatchSet: 2 Gerrit-Owner: Name of user not set #1003801 Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Name of user not set #1003801 Gerrit-Attention: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 05 Sep 2021 23:11:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/asrock/e350m1: Enable USB on mPCIe
by Angel Pons (Code Review) 05 Sep '21

05 Sep '21

Attention is currently required from: Swift Geek (Sebastian Grzywna). Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57307 ) Change subject: mb/asrock/e350m1: Enable USB on mPCIe ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57307 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ee7e3679c9cd87b81f955c68ec89db1dda30aec Gerrit-Change-Number: 57307 Gerrit-PatchSet: 1 Gerrit-Owner: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Comment-Date: Sun, 05 Sep 2021 23:10:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit September 2021