coreboot-gerrit September 2021

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Change in coreboot[master]: soc/intel/common/cse: Add argument for CSE fixed client addr
by Felix Held (Code Review) 05 Sep '21

05 Sep '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57295 ) Change subject: soc/intel/common/cse: Add argument for CSE fixed client addr ...................................................................... soc/intel/common/cse: Add argument for CSE fixed client addr There are multiple HECI clients in the CSE. heci_send_receive() is sending HECI messages to only the MKHI client. Add an argument to heci_send_receive() function to provide flexibility to the caller to select the client for which the message is intended. With the above change heci_send() and heci_receive() functions are no longer required to be exposed. In the follow-up patches there will be messages sent to one other client. BUG=None BRANCH=None TEST=Build and boot brya. HECI message send and receive to MKHI client is working. Also, MEI BUS message to disable bus is working. Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Change-Id: Icde6d0155b62472b6a7caadc5fc8ea2e2ba6eb0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/57295 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/apollolake/cse.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/cse/cse_eop.c M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h 5 files changed, 38 insertions(+), 49 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/apollolake/cse.c b/src/soc/intel/apollolake/cse.c index 1558d38..24fb417 100644 --- a/src/soc/intel/apollolake/cse.c +++ b/src/soc/intel/apollolake/cse.c @@ -44,7 +44,6 @@ static int read_cse_file(const char *path, void *buff, size_t *size, size_t offset, uint32_t flags) { - int res; size_t reply_size; struct mca_command { @@ -77,18 +76,10 @@ msg.data_size = *size; msg.offset = offset; - res = heci_send(&msg, sizeof(msg), BIOS_HOST_ADDR, HECI_MKHI_ADDR); - - if (!res) { - printk(BIOS_ERR, "failed to send HECI message\n"); - return 0; - } - reply_size = sizeof(rmsg); - res = heci_receive(&rmsg, &reply_size); - if (!res) { - printk(BIOS_ERR, "failed to receive HECI reply\n"); + if (!heci_send_receive(&msg, sizeof(msg), &rmsg, &reply_size, HECI_MKHI_ADDR)) { + printk(BIOS_ERR, "HECI: Failed to read file\n"); return 0; } diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 7708c1b..1cea7d9 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -384,7 +384,12 @@ return pend_len; } -int +/* + * Send message msg of size len to host from host_addr to cse_addr. + * Returns 1 on success and 0 otherwise. + * In case of error heci_reset() may be required. + */ +static int heci_send(const void *msg, size_t len, uint8_t host_addr, uint8_t client_addr) { uint8_t retry; @@ -487,7 +492,15 @@ return recv_len; } -int heci_receive(void *buff, size_t *maxlen) +/* + * Receive message into buff not exceeding maxlen. Message is considered + * successfully received if a 'complete' indication is read from ME side + * and there was enough space in the buffer to fit that message. maxlen + * is updated with size of message that was received. Returns 0 on failure + * and 1 on success. + * In case of error heci_reset() may be required. + */ +static int heci_receive(void *buff, size_t *maxlen) { uint8_t retry; size_t left, received; @@ -533,9 +546,10 @@ return 0; } -int heci_send_receive(const void *snd_msg, size_t snd_sz, void *rcv_msg, size_t *rcv_sz) +int heci_send_receive(const void *snd_msg, size_t snd_sz, void *rcv_msg, size_t *rcv_sz, + uint8_t cse_addr) { - if (!heci_send(snd_msg, snd_sz, BIOS_HOST_ADDR, HECI_MKHI_ADDR)) { + if (!heci_send(snd_msg, snd_sz, BIOS_HOST_ADDR, cse_addr)) { printk(BIOS_ERR, "HECI: send Failed\n"); return 0; } @@ -663,7 +677,8 @@ if (rst_type == CSE_RESET_ONLY) status = heci_send(&msg, sizeof(msg), BIOS_HOST_ADDR, HECI_MKHI_ADDR); else - status = heci_send_receive(&msg, sizeof(msg), &reply, &reply_size); + status = heci_send_receive(&msg, sizeof(msg), &reply, &reply_size, + HECI_MKHI_ADDR); printk(BIOS_DEBUG, "HECI: Global Reset %s!\n", status ? "success" : "failure"); return status; @@ -733,7 +748,7 @@ } if (!heci_send_receive(&msg, sizeof(struct hmrfpo_enable_msg), - &resp, &resp_size)) + &resp, &resp_size, HECI_MKHI_ADDR)) return 0; if (resp.hdr.result) { @@ -782,7 +797,7 @@ } if (!heci_send_receive(&msg, sizeof(struct hmrfpo_get_status_msg), - &resp, &resp_size)) { + &resp, &resp_size, HECI_MKHI_ADDR)) { printk(BIOS_ERR, "HECI: HMRFPO send/receive fail\n"); return -1; } @@ -847,7 +862,8 @@ heci_reset(); - if (!heci_send_receive(&fw_ver_msg, sizeof(fw_ver_msg), &resp, &resp_size)) + if (!heci_send_receive(&fw_ver_msg, sizeof(fw_ver_msg), &resp, &resp_size, + HECI_MKHI_ADDR)) goto fail; if (resp.hdr.result) diff --git a/src/soc/intel/common/block/cse/cse_eop.c b/src/soc/intel/common/block/cse/cse_eop.c index 6e57439..d8c6430 100644 --- a/src/soc/intel/common/block/cse/cse_eop.c +++ b/src/soc/intel/common/block/cse/cse_eop.c @@ -33,16 +33,10 @@ uint8_t reserved[2]; } __packed reply = {}; - /* This is sent to the MEI client endpoint, not the MKHI endpoint */ - int ret = heci_send(&msg, sizeof(msg), BIOS_HOST_ADDR, HECI_MEI_ADDR); - if (!ret) { - printk(BIOS_ERR, "HECI: Failed to send MEI bus disable command!\n"); - return false; - } - size_t reply_sz = sizeof(reply); - if (!heci_receive(&reply, &reply_sz)) { - printk(BIOS_ERR, "HECI: Failed to receive a reply from CSE\n"); + + if (!heci_send_receive(&msg, sizeof(msg), &reply, &reply_sz, HECI_MEI_ADDR)) { + printk(BIOS_ERR, "HECI: Failed to Disable MEI bus\n"); return false; } @@ -112,7 +106,7 @@ printk(BIOS_INFO, "HECI: Sending End-of-Post\n"); - if (!heci_send_receive(&msg, sizeof(msg), &resp, &resp_size)) { + if (!heci_send_receive(&msg, sizeof(msg), &resp, &resp_size, HECI_MKHI_ADDR)) { printk(BIOS_ERR, "HECI: EOP send/receive fail\n"); return CSE_EOP_RESULT_ERROR; } diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 15d585d..762de2a 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -202,7 +202,8 @@ size_t resp_size = sizeof(struct get_bp_info_rsp); - if (!heci_send_receive(&info_req, sizeof(info_req), bp_info_rsp, &resp_size)) { + if (!heci_send_receive(&info_req, sizeof(info_req), bp_info_rsp, &resp_size, + HECI_MKHI_ADDR)) { printk(BIOS_ERR, "cse_lite: Could not get partition info\n"); return false; } @@ -254,7 +255,8 @@ struct mkhi_hdr switch_resp; size_t sw_resp_sz = sizeof(struct mkhi_hdr); - if (!heci_send_receive(&switch_req, sizeof(switch_req), &switch_resp, &sw_resp_sz)) + if (!heci_send_receive(&switch_req, sizeof(switch_req), &switch_resp, &sw_resp_sz, + HECI_MKHI_ADDR)) return false; if (switch_resp.result) { @@ -291,7 +293,7 @@ size_t data_clr_rsp_sz = sizeof(data_clr_rsp); if (!heci_send_receive(&data_clr_rq, sizeof(data_clr_rq), &data_clr_rsp, - &data_clr_rsp_sz)) { + &data_clr_rsp_sz, HECI_MKHI_ADDR)) { return false; } diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 153cb22..9753798 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -130,29 +130,15 @@ /* set up device for use in early boot enviroument with temp bar */ void heci_init(uintptr_t bar); -/* - * Receive message into buff not exceeding maxlen. Message is considered - * successfully received if a 'complete' indication is read from ME side - * and there was enough space in the buffer to fit that message. maxlen - * is updated with size of message that was received. Returns 0 on failure - * and 1 on success. - * In case of error heci_reset() may be requiered. - */ -int heci_receive(void *buff, size_t *maxlen); -/* - * Send message msg of size len to host from host_addr to cse_addr. - * Returns 1 on success and 0 otherwise. - * In case of error heci_reset() may be requiered. - */ -int -heci_send(const void *msg, size_t len, uint8_t host_addr, uint8_t cse_addr); /* + * Send message from BIOS_HOST_ADDR to cse_addr. * Sends snd_msg of size snd_sz, and reads message into buffer pointed by * rcv_msg of size rcv_sz * Returns 0 on failure and 1 on success. */ -int heci_send_receive(const void *snd_msg, size_t snd_sz, void *rcv_msg, size_t *rcv_sz); +int heci_send_receive(const void *snd_msg, size_t snd_sz, void *rcv_msg, size_t *rcv_sz, + uint8_t cse_addr); /* * Attempt device reset. This is useful and perhaps only thing left to do when -- To view, visit https://review.coreboot.org/c/coreboot/+/57295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icde6d0155b62472b6a7caadc5fc8ea2e2ba6eb0c Gerrit-Change-Number: 57295 Gerrit-PatchSet: 11 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Add tpch device information under dptf
by Felix Held (Code Review) 05 Sep '21

05 Sep '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57097 ) Change subject: soc/intel/alderlake: Add tpch device information under dptf ...................................................................... soc/intel/alderlake: Add tpch device information under dptf Add tpch device information for thermal functionality under dptf for alderlake soc based platform. BUG=b:198582766 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: Iad8e8bc0b7a104bbe582bc477936d0d00087f1d1 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57097 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/alderlake/dptf.c 1 file changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/dptf.c b/src/soc/intel/alderlake/dptf.c index 2af96df..ba604ca 100644 --- a/src/soc/intel/alderlake/dptf.c +++ b/src/soc/intel/alderlake/dptf.c @@ -10,6 +10,12 @@ .generic_hid = "INTC1046", /* _HID for Intel DPTF Fan Device */ .fan_hid = "INTC1048", + /* _HID for the toplevel TPCH device, typically \_SB.TPCH */ + .tpch_device_hid = "INTC1049", + /* RFC0 method name */ + .tpch_rfc0_method = "RFC0", + /* RFC1 method name */ + .tpch_rfc1_method = "RFC1", }; const struct dptf_platform_info *get_dptf_platform_info(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/57097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad8e8bc0b7a104bbe582bc477936d0d00087f1d1 Gerrit-Change-Number: 57097 Gerrit-PatchSet: 8 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/intel/dptf: Add new thermal control mechanism for pch device
by Felix Held (Code Review) 05 Sep '21

05 Sep '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57096 ) Change subject: drivers/intel/dptf: Add new thermal control mechanism for pch device ...................................................................... drivers/intel/dptf: Add new thermal control mechanism for pch device Add new thermal control mechanism for pch device under dptf driver. This provides support of different control knobs for FIVR. BUG=b:198582766 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: I035d2844b9ba6a9532ae006fc1c43e34cb94328a Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57096 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/drivers/intel/dptf/Kconfig M src/drivers/intel/dptf/dptf.c M src/drivers/intel/dptf/dptf.h 3 files changed, 58 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/drivers/intel/dptf/Kconfig b/src/drivers/intel/dptf/Kconfig index ebdb650..6f590b9 100644 --- a/src/drivers/intel/dptf/Kconfig +++ b/src/drivers/intel/dptf/Kconfig @@ -5,3 +5,10 @@ help When enabled, entries in the devicetree are used to generate Intel DPTF Tables at runtime in the SSDT. + +config DRIVERS_INTEL_DPTF_SUPPORTS_TPCH + def_bool n + depends on HAVE_ACPI_TABLES && PMC_IPC_ACPI_INTERFACE + help + When enabled, chip driver/intel/dptf will publish information to the + SSDT for the TPCH device. diff --git a/src/drivers/intel/dptf/dptf.c b/src/drivers/intel/dptf/dptf.c index 24a371d..a202a27 100644 --- a/src/drivers/intel/dptf/dptf.c +++ b/src/drivers/intel/dptf/dptf.c @@ -4,6 +4,7 @@ #include <acpi/acpigen_pci.h> #include <console/console.h> #include <device/device.h> +#include <intelblocks/pmc_ipc.h> #include "chip.h" #include "dptf.h" @@ -194,7 +195,50 @@ } } -/* \_SB.DPTF - note: leaves the Scope open for child devices*/ +/* \_SB.DPTF.TPCH.RFC methods */ +static void write_tpch_rfc_methods(const char *tpch_rfc_method_name, + unsigned int ipc_subcmd_ctrl_value) +{ + acpigen_write_method_serialized(tpch_rfc_method_name, 1); + acpigen_emit_namestring("IPCS"); + acpigen_write_integer(PMC_IPC_CMD_COMMAND_FIVR); + acpigen_write_integer(PMC_IPC_CMD_CMD_ID_FIVR_WRITE); + acpigen_write_integer(0x8); + acpigen_write_integer(ipc_subcmd_ctrl_value); + acpigen_emit_byte(ARG0_OP); + acpigen_write_dword(0); + acpigen_write_dword(0); + /* The reason for returning a value here is a W/A for the ESIF shell */ + acpigen_emit_byte(RETURN_OP); + acpigen_write_package(0); + acpigen_write_package_end(); + acpigen_write_method_end(); +} + +static void write_create_tpch(const struct dptf_platform_info *platform_info) +{ + acpigen_write_device("TPCH"); + acpigen_write_name("_HID"); + dptf_write_hid(platform_info->use_eisa_hids, platform_info->tpch_device_hid); + acpigen_write_name_integer("_UID", 0); + acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); +} + +static void write_tpch_methods(const struct dptf_platform_info *platform_info) +{ + write_create_tpch(platform_info); + + /* Create RFC0 method */ + write_tpch_rfc_methods(platform_info->tpch_rfc0_method, + PMC_IPC_SUBCMD_RFI_CTRL0_LOGIC); + /* Create RFC1 method */ + write_tpch_rfc_methods(platform_info->tpch_rfc1_method, + PMC_IPC_SUBCMD_RFI_CTRL4_LOGIC); + + acpigen_write_device_end(); /* TPCH Device */ +} + +/* \_SB.DPTF - note: leaves the Scope open for child devices */ static void write_open_dptf_device(const struct device *dev, const struct dptf_platform_info *platform_info) { @@ -229,6 +273,9 @@ write_imok(); write_generic_devices(config, platform_info); + if (CONFIG(DRIVERS_INTEL_DPTF_SUPPORTS_TPCH)) + write_tpch_methods(platform_info); + acpigen_pop_len(); /* DPTF Device (write_open_dptf_device) */ acpigen_pop_len(); /* Scope */ } diff --git a/src/drivers/intel/dptf/dptf.h b/src/drivers/intel/dptf/dptf.h index 2eeec7b..f23ae25 100644 --- a/src/drivers/intel/dptf/dptf.h +++ b/src/drivers/intel/dptf/dptf.h @@ -14,6 +14,9 @@ const char *dptf_device_hid; const char *generic_hid; const char *fan_hid; + const char *tpch_device_hid; + const char *tpch_rfc0_method; + const char *tpch_rfc1_method; }; const struct dptf_platform_info *get_dptf_platform_info(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/57096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I035d2844b9ba6a9532ae006fc1c43e34cb94328a Gerrit-Change-Number: 57096 Gerrit-PatchSet: 8 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/var/gooey: Configure I2C times for I2C devices
by Felix Held (Code Review) 05 Sep '21

05 Sep '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57297 ) Change subject: mb/google/dedede/var/gooey: Configure I2C times for I2C devices ...................................................................... mb/google/dedede/var/gooey: Configure I2C times for I2C devices Configure I2C high / low time in device tree to ensure I2C CLK runs under I2C_SPEED_FAST (400 kHz). Measured I2C frequency just as below after tuning: Touchpad: 386.7kHz Touchscreen: 387.4kHz Audio: 385.7kHz P-sensor: 378.1kHz BaUG=b:197247706 BRANCH=dedede TEST=Build and check I2C clock is under 400kHz Signed-off-by: stanley.wu <stanley1.wu(a)lcfc.corp-partner.google.com> Change-Id: Ic5d5660181f36f161ae04cbf5003f6d7ad4bc16f Reviewed-on: https://review.coreboot.org/c/coreboot/+/57297 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Henry Sun <henrysun(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/variants/gooey/overridetree.cb 1 file changed, 8 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Karthik Ramasubramanian: Looks good to me, approved Henry Sun: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/dedede/variants/gooey/overridetree.cb b/src/mainboard/google/dedede/variants/gooey/overridetree.cb index 9b291fb..ab0e410 100644 --- a/src/mainboard/google/dedede/variants/gooey/overridetree.cb +++ b/src/mainboard/google/dedede/variants/gooey/overridetree.cb @@ -13,18 +13,26 @@ register "common_soc_config" = "{ .i2c[0] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 212, + .fall_time_ns = 38, }, .i2c[1] = { .speed = I2C_SPEED_FAST, }, .i2c[2] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 212, + .fall_time_ns = 38, }, .i2c[4] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 212, + .fall_time_ns = 38, }, .i2c[5] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 212, + .fall_time_ns = 38, }, }" -- To view, visit https://review.coreboot.org/c/coreboot/+/57297 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5d5660181f36f161ae04cbf5003f6d7ad4bc16f Gerrit-Change-Number: 57297 Gerrit-PatchSet: 2 Gerrit-Owner: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/var/gooey: Add MT53E512M32D1NP-046 as supported mem ...
by Felix Held (Code Review) 05 Sep '21

05 Sep '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57310 ) Change subject: mb/google/dedede/var/gooey: Add MT53E512M32D1NP-046 as supported mem module ...................................................................... mb/google/dedede/var/gooey: Add MT53E512M32D1NP-046 as supported mem module Add MT53E512M32D1NP-046 WT:B supported memory part in the mem_parts_used.txt and generate the SPD ID for the part. Manufacturer is Micron, and the memory part is 1anm Tech, difference to 1xnm Tech on MT53E512M32D2NP-046. BUG=b:194223174 BRANCH=dedede TEST=Build the gooey board. Change-Id: I7b83126a2bf98bb9d0ca05d397c288e0d99ed781 Signed-off-by: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57310 Reviewed-by: Paul Fagerburg <pfagerburg(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/dedede/variants/gooey/memory/Makefile.inc M src/mainboard/google/dedede/variants/gooey/memory/dram_id.generated.txt M src/mainboard/google/dedede/variants/gooey/memory/mem_list_variant.txt 3 files changed, 3 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Paul Fagerburg: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/gooey/memory/Makefile.inc b/src/mainboard/google/dedede/variants/gooey/memory/Makefile.inc index d0960c7..c0c0902 100644 --- a/src/mainboard/google/dedede/variants/gooey/memory/Makefile.inc +++ b/src/mainboard/google/dedede/variants/gooey/memory/Makefile.inc @@ -2,4 +2,4 @@ ## This is an auto-generated file. Do not edit!! SPD_SOURCES = -SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, H9HCNNNBKMMLXR-NEE +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, H9HCNNNBKMMLXR-NEE, MT53E512M32D1NP-046 WT:B diff --git a/src/mainboard/google/dedede/variants/gooey/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/gooey/memory/dram_id.generated.txt index 0df7bfc..7576d17 100644 --- a/src/mainboard/google/dedede/variants/gooey/memory/dram_id.generated.txt +++ b/src/mainboard/google/dedede/variants/gooey/memory/dram_id.generated.txt @@ -2,3 +2,4 @@ MT53E512M32D2NP-046 WT:E 0 (0000) K4U6E3S4AA-MGCR 0 (0000) H9HCNNNBKMMLXR-NEE 0 (0000) +MT53E512M32D1NP-046 WT:B 0 (0000) diff --git a/src/mainboard/google/dedede/variants/gooey/memory/mem_list_variant.txt b/src/mainboard/google/dedede/variants/gooey/memory/mem_list_variant.txt index 47159f8..04f01b3 100644 --- a/src/mainboard/google/dedede/variants/gooey/memory/mem_list_variant.txt +++ b/src/mainboard/google/dedede/variants/gooey/memory/mem_list_variant.txt @@ -1,3 +1,4 @@ MT53E512M32D2NP-046 WT:E K4U6E3S4AA-MGCR H9HCNNNBKMMLXR-NEE +MT53E512M32D1NP-046 WT:B 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/57310 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b83126a2bf98bb9d0ca05d397c288e0d99ed781 Gerrit-Change-Number: 57310 Gerrit-PatchSet: 4 Gerrit-Owner: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common: Add PMC IPC commands for FIVR
by Felix Held (Code Review) 05 Sep '21

05 Sep '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57095 ) Change subject: soc/intel/common: Add PMC IPC commands for FIVR ...................................................................... soc/intel/common: Add PMC IPC commands for FIVR Add PMC IPC commands information for FIVR control functionality. BUG=b:198582766 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: Iccb43b7ba4f0765499bf1844efbbb526bd671a8f Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57095 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/common/block/include/intelblocks/pmc_ipc.h 1 file changed, 9 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h b/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h index b67abc0..fb33a07 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h +++ b/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h @@ -16,6 +16,15 @@ #define PMC_IPC_CMD_SIZE_SHIFT 16 #define PMC_IPC_CMD_SIZE_MASK 0xff +/* IPC command to control FIVR Configuration */ +#define PMC_IPC_CMD_COMMAND_FIVR 0xA3 +/* IPC subcommand to write FIVR Register */ +#define PMC_IPC_CMD_CMD_ID_FIVR_WRITE 0x01 +/* IPC subcommand to control RFI Control 0 register logic write */ +#define PMC_IPC_SUBCMD_RFI_CTRL0_LOGIC 0x00 +/* IPC subcommand to control RFI Control 4 register logic write */ +#define PMC_IPC_SUBCMD_RFI_CTRL4_LOGIC 0x01 + #define PMC_IPC_CMD_FIELD(name, val) \ ((((val) & PMC_IPC_CMD_##name##_MASK) << PMC_IPC_CMD_##name##_SHIFT)) -- To view, visit https://review.coreboot.org/c/coreboot/+/57095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccb43b7ba4f0765499bf1844efbbb526bd671a8f Gerrit-Change-Number: 57095 Gerrit-PatchSet: 6 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/jasperlake: Utilize vbt data size Kconfig option
by Felix Held (Code Review) 05 Sep '21

05 Sep '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57201 ) Change subject: soc/intel/jasperlake: Utilize vbt data size Kconfig option ...................................................................... soc/intel/jasperlake: Utilize vbt data size Kconfig option Currently maximum VBT data size for Jasper Lake is 8KB, but Bugzzy would use VBT data over 8KB. This change makes use of Kconfig option to increase the maximum VBT data size to 9KB for Jasper Lake. BUG=b:194029827 BRANCH=dedede TEST=build and boot bugzzy and verify fw screen is loaded Change-Id: I0abe1ba5609b48a8a8b15f88bec28342ce26c78f Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57201 Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/jasperlake/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index fa26a54..c40c153 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -174,6 +174,10 @@ hex default 0xc35 +config VBT_DATA_SIZE_KB + int + default 9 + config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_MUST_REQUEST_DISPLAY -- To view, visit https://review.coreboot.org/c/coreboot/+/57201 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0abe1ba5609b48a8a8b15f88bec28342ce26c78f Gerrit-Change-Number: 57201 Gerrit-PatchSet: 10 Gerrit-Owner: shkim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/var/drawcia: change LTE reset pin to GPP_H17
by Felix Held (Code Review) 05 Sep '21

05 Sep '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57204 ) Change subject: mb/google/dedede/var/drawcia: change LTE reset pin to GPP_H17 ...................................................................... mb/google/dedede/var/drawcia: change LTE reset pin to GPP_H17 Drawper change LTE reset pin from GPP_H0 to GPP_H17 from DVT phase. BUG=b:198117092 TEST=emerge-dedede coreboot Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Change-Id: Ib65580babf7d21535df2bd8d33bb19261bebfe15 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57204 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Henry Sun <henrysun(a)google.com> --- M src/mainboard/google/dedede/variants/drawcia/gpio.c M src/mainboard/google/dedede/variants/drawcia/ramstage.c M src/mainboard/google/dedede/variants/drawcia/variant.c 3 files changed, 13 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Henry Sun: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/dedede/variants/drawcia/gpio.c b/src/mainboard/google/dedede/variants/drawcia/gpio.c index 955d9a0..97865474 100644 --- a/src/mainboard/google/dedede/variants/drawcia/gpio.c +++ b/src/mainboard/google/dedede/variants/drawcia/gpio.c @@ -31,6 +31,7 @@ /* H0 : WWAN_PERST */ PAD_CFG_GPO(GPP_H0, 0, PLTRST), + PAD_CFG_GPO(GPP_H17, 0, PLTRST), }; static const struct pad_config lte_disable_pads[] = { @@ -38,6 +39,7 @@ PAD_NC(GPP_B7, NONE), PAD_NC(GPP_D0, NONE), PAD_NC(GPP_H0, NONE), + PAD_NC(GPP_H17, NONE), }; const struct pad_config *variant_override_gpio_table(size_t *num) diff --git a/src/mainboard/google/dedede/variants/drawcia/ramstage.c b/src/mainboard/google/dedede/variants/drawcia/ramstage.c index 5acc033..2500b96 100644 --- a/src/mainboard/google/dedede/variants/drawcia/ramstage.c +++ b/src/mainboard/google/dedede/variants/drawcia/ramstage.c @@ -1,11 +1,20 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <baseboard/variants.h> +#include <boardid.h> static struct acpi_gpio lte_reset_gpio = ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0); static struct acpi_gpio lte_enable_gpio = ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10); +/* New lte reset for drapwer DVT*/ +static struct acpi_gpio lte_new_reset_gpio = ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H17); void variant_devtree_update(void) { - update_lte_device(&lte_reset_gpio, &lte_enable_gpio); + + uint32_t board_version = board_id(); + + if (board_version <= 9) /* board version 9 is drawper EVT */ + update_lte_device(&lte_reset_gpio, &lte_enable_gpio); + else + update_lte_device(&lte_new_reset_gpio, &lte_enable_gpio); } diff --git a/src/mainboard/google/dedede/variants/drawcia/variant.c b/src/mainboard/google/dedede/variants/drawcia/variant.c index c557fe0..a8ec581 100644 --- a/src/mainboard/google/dedede/variants/drawcia/variant.c +++ b/src/mainboard/google/dedede/variants/drawcia/variant.c @@ -29,6 +29,7 @@ static void power_off_lte_module(void) { gpio_output(GPP_H0, 0); + gpio_output(GPP_H17, 0); mdelay(20); gpio_output(GPP_A10, 0); } -- To view, visit https://review.coreboot.org/c/coreboot/+/57204 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib65580babf7d21535df2bd8d33bb19261bebfe15 Gerrit-Change-Number: 57204 Gerrit-PatchSet: 5 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/intel/adlrvp: Clean up the print message
by Felix Held (Code Review) 05 Sep '21

05 Sep '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57389 ) Change subject: mb/intel/adlrvp: Clean up the print message ...................................................................... mb/intel/adlrvp: Clean up the print message TEST=none Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> Change-Id: I6346b087543217c78f87751051a4f38b23c566d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57389 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/intel/adlrvp/ramstage.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Sumeet R Pawnikar: Looks good to me, approved diff --git a/src/mainboard/intel/adlrvp/ramstage.c b/src/mainboard/intel/adlrvp/ramstage.c index 25a7c5b..e1f4401 100644 --- a/src/mainboard/intel/adlrvp/ramstage.c +++ b/src/mainboard/intel/adlrvp/ramstage.c @@ -40,7 +40,7 @@ settings->pl1.max_power = limits[i].pl1_max_power; settings->pl2.min_power = limits[i].pl2_min_power; settings->pl2.max_power = limits[i].pl2_max_power; - printk(BIOS_INFO, "sumeet: Overriding DPTF power limits PL1 (%u, %u) PL2 (%u, %u)\n", + printk(BIOS_INFO, "Overriding DPTF power limits PL1 (%u, %u) PL2 (%u, %u)\n", limits[i].pl1_min_power, limits[i].pl1_max_power, limits[i].pl2_min_power, -- To view, visit https://review.coreboot.org/c/coreboot/+/57389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6346b087543217c78f87751051a4f38b23c566d2 Gerrit-Change-Number: 57389 Gerrit-PatchSet: 2 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/guybrush: Set eSPI alert as dedicated open drain
by Felix Held (Code Review) 05 Sep '21

05 Sep '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57313 ) Change subject: mb/google/guybrush: Set eSPI alert as dedicated open drain ...................................................................... mb/google/guybrush: Set eSPI alert as dedicated open drain Guybrush based boards must usa a dedicated eSPI alert#. Must be open drain to prevent power leaks. Keep guybrush reference board in-band since alert# may not be connected. BUG=b:198409370 TEST=Build guybrush and nipperkin, boot guybrush BRANCH=None Change-Id: I4b23bfc6a1167aebfde5acd524fda043b63163dc Signed-off-by: Rob Barnes <robbarnes(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57313 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb M src/mainboard/google/guybrush/variants/guybrush/overridetree.cb 2 files changed, 4 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index df8bd2a..a0d5114 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -36,7 +36,7 @@ .io_mode = ESPI_IO_MODE_QUAD, .op_freq_mhz = ESPI_OP_FREQ_33_MHZ, .crc_check_enable = 1, - .alert_pin = ESPI_ALERT_PIN_IN_BAND, + .alert_pin = ESPI_ALERT_PIN_OPEN_DRAIN, .periph_ch_en = 1, .vw_ch_en = 1, .oob_ch_en = 0, diff --git a/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb b/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb index 88c7d42..e732917 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb @@ -168,4 +168,7 @@ end end + # TODO(b/198596430): Disable in-band alerts after majority boards are reworked + register "common_config.espi_config.alert_pin" = "ESPI_ALERT_PIN_IN_BAND" + end # chip soc/amd/cezanne -- To view, visit https://review.coreboot.org/c/coreboot/+/57313 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b23bfc6a1167aebfde5acd524fda043b63163dc Gerrit-Change-Number: 57313 Gerrit-PatchSet: 3 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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