coreboot-gerrit July 2021

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Change in coreboot[master]: arch/x86: Save resume vector to stack in x86_64 mode
by Iru Cai (vimacs) (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Iru Cai. Hello build bot (Jenkins), Iru Cai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55947 to look at the new patch set (#2). Change subject: arch/x86: Save resume vector to stack in x86_64 mode ...................................................................... arch/x86: Save resume vector to stack in x86_64 mode In x86_64, the first function parameter is passed in rdi register, and the 32-bit code after exiting long mode reads the resume vector in 4(%esp), so it's needed to save the resume vector from rdi to 4(%rsp). Also note that the function attribute "regparm" only works on x86-32 targets according to the GCC manual, so "asmlinkage" doesn't change the ABI of an x86_64 function. Tested on HP EliteBook 2560p. The laptop can resume from S3 in x86_64 mode after this change. Change-Id: I45f2678071b2511c0af5dce9d9b73ac70dfd7252 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M src/arch/x86/wakeup.S 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/55947/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45f2678071b2511c0af5dce9d9b73ac70dfd7252 Gerrit-Change-Number: 55947 Gerrit-PatchSet: 2 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/intel/usb4/retimer: Update code to assign correct port number
by build bot (Jenkins) (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Tim Wawrzynczak. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55945 ) Change subject: drivers/intel/usb4/retimer: Update code to assign correct port number ...................................................................... Patch Set 2: (2 comments) File src/drivers/intel/usb4/retimer/retimer.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123128): https://review.coreboot.org/c/coreboot/+/55945/comment/26c28ac7_68b8fe4c PS2, Line 359: "%s: No DFP%1d power GPIO for %s \n", __func__, trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123128): https://review.coreboot.org/c/coreboot/+/55945/comment/11baaf21_41eefdc3 PS2, Line 359: "%s: No DFP%1d power GPIO for %s \n", __func__, unnecessary whitespace before a quoted newline -- To view, visit https://review.coreboot.org/c/coreboot/+/55945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib11637ae39046e0afdacd33bc34e8a59e6f2bfb1 Gerrit-Change-Number: 55945 Gerrit-PatchSet: 2 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Abhijeet Rao <abhijeet.rao(a)intel.corp-partner.google.com> Gerrit-CC: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 01 Jul 2021 10:28:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: Remove KASAN from the project ideas list
by Paul Menzel (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Werner Zeh. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55991 ) Change subject: Documentation: Remove KASAN from the project ideas list ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/55991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38c6e274e416b98485943d36536a57a14743945b Gerrit-Change-Number: 55991 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Thu, 01 Jul 2021 10:12:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/usb4/retimer: Update code to assign correct port number
by Paul Menzel (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Tim Wawrzynczak. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55945 ) Change subject: drivers/intel/usb4/retimer: Update code to assign correct port number ...................................................................... Patch Set 2: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/55945/comment/f1d3d43a_dce7a7a9 PS2, Line 19: where even Only one space. https://review.coreboot.org/c/coreboot/+/55945/comment/896dfadf_2daffd9c PS2, Line 23: Updated Update https://review.coreboot.org/c/coreboot/+/55945/comment/fe7e9b66_a55e97ea PS2, Line 25: get Get File src/drivers/intel/usb4/retimer/retimer.c: https://review.coreboot.org/c/coreboot/+/55945/comment/706ab000_d4374989 PS2, Line 359: %s \n Please remove the space before the line break. https://review.coreboot.org/c/coreboot/+/55945/comment/6b6ce6e6_1ef79194 PS2, Line 363: /* Get USB port number */ Should be clear from `usb.port_id`. -- To view, visit https://review.coreboot.org/c/coreboot/+/55945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib11637ae39046e0afdacd33bc34e8a59e6f2bfb1 Gerrit-Change-Number: 55945 Gerrit-PatchSet: 2 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Abhijeet Rao <abhijeet.rao(a)intel.corp-partner.google.com> Gerrit-CC: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 01 Jul 2021 10:11:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Update controller field for tbt_dma entries
by Maulik V Vaghela (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak. Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55946 ) Change subject: mb/google/brya: Update controller field for tbt_dma entries ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/brya/variants/brya0/overridetree.cb: https://review.coreboot.org/c/coreboot/+/55946/comment/7eb02ca1_1e5536f3 PS1, Line 145: .group = ACPI_PLD_GROUP(1, 1), : .controller = 0, > Good call, that makes for a better interface. […] Ack Yes Tim, we were supposed to give DMA controller number but that was just to get correct port number. Thank you Tim and Furquan for review. Interface is better now 😊 -- To view, visit https://review.coreboot.org/c/coreboot/+/55946 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20c088ee81610155067abad086eba8d72f73ad60 Gerrit-Change-Number: 55946 Gerrit-PatchSet: 2 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Abhijeet Rao <abhijeet.rao(a)intel.corp-partner.google.com> Gerrit-CC: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 01 Jul 2021 09:52:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: device: Clean up resource utility function signatures
by Patrick Georgi (Code Review) 01 Jul '21

01 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55475 ) Change subject: device: Clean up resource utility function signatures ...................................................................... device: Clean up resource utility function signatures Drop extern declarations from functions. Declare resource arguments as const. Change-Id: I7684cc7813bad805c39a762892636818279ac134 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55475 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/device/device_util.c M src/include/device/resource.h 2 files changed, 20 insertions(+), 24 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/device/device_util.c b/src/device/device_util.c index f05f71d..a5d1860 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -450,7 +450,7 @@ * @param resource The resource whose limit is desired. * @return The end. */ -resource_t resource_end(struct resource *resource) +resource_t resource_end(const struct resource *resource) { resource_t base, end; @@ -476,7 +476,7 @@ * @param resource The resource whose maximum is desired. * @return The maximum. */ -resource_t resource_max(struct resource *resource) +resource_t resource_max(const struct resource *resource) { resource_t max; @@ -491,7 +491,7 @@ * @param resource The resource type to decode. * @return TODO. */ -const char *resource_type(struct resource *resource) +const char *resource_type(const struct resource *resource) { static char buffer[RESOURCE_TYPE_MAX]; snprintf(buffer, sizeof(buffer), "%s%s%s%s", @@ -513,7 +513,7 @@ * @param resource The resource that was just stored. * @param comment TODO */ -void report_resource_stored(struct device *dev, struct resource *resource, +void report_resource_stored(struct device *dev, const struct resource *resource, const char *comment) { char buf[10]; diff --git a/src/include/device/resource.h b/src/include/device/resource.h index 3a7ccf0..098d0b6 100644 --- a/src/include/device/resource.h +++ b/src/include/device/resource.h @@ -63,31 +63,27 @@ /* Generic resource helper functions */ struct device; struct bus; -extern void compact_resources(struct device *dev); -extern struct resource *probe_resource(const struct device *dev, - unsigned int index); -extern struct resource *new_resource(struct device *dev, unsigned int index); -extern struct resource *find_resource(const struct device *dev, - unsigned int index); -extern resource_t resource_end(struct resource *resource); -extern resource_t resource_max(struct resource *resource); -extern void report_resource_stored(struct device *dev, - struct resource *resource, const char *comment); +void compact_resources(struct device *dev); +struct resource *probe_resource(const struct device *dev, unsigned int index); +struct resource *new_resource(struct device *dev, unsigned int index); +struct resource *find_resource(const struct device *dev, unsigned int index); +resource_t resource_end(const struct resource *resource); +resource_t resource_max(const struct resource *resource); +void report_resource_stored(struct device *dev, const struct resource *resource, + const char *comment); -typedef void (*resource_search_t)(void *gp, struct device *dev, - struct resource *res); -extern void search_bus_resources(struct bus *bus, - unsigned long type_mask, unsigned long type, - resource_search_t search, void *gp); +typedef void (*resource_search_t)(void *gp, struct device *dev, struct resource *res); -extern void search_global_resources( - unsigned long type_mask, unsigned long type, - resource_search_t search, void *gp); +void search_bus_resources(struct bus *bus, unsigned long type_mask, unsigned long type, + resource_search_t search, void *gp); + +void search_global_resources(unsigned long type_mask, unsigned long type, + resource_search_t search, void *gp); #define RESOURCE_TYPE_MAX 20 -extern const char *resource_type(struct resource *resource); +const char *resource_type(const struct resource *resource); -static inline void *res2mmio(struct resource *res, unsigned long offset, +static inline void *res2mmio(const struct resource *res, unsigned long offset, unsigned long mask) { return (void *)(uintptr_t)((res->base + offset) & ~mask); -- To view, visit https://review.coreboot.org/c/coreboot/+/55475 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7684cc7813bad805c39a762892636818279ac134 Gerrit-Change-Number: 55475 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: toolchain.inc: copy architecture specific CFLAGS to GCC_ADAFLAGS
by Patrick Georgi (Code Review) 01 Jul '21

01 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55549 ) Change subject: toolchain.inc: copy architecture specific CFLAGS to GCC_ADAFLAGS ...................................................................... toolchain.inc: copy architecture specific CFLAGS to GCC_ADAFLAGS This fixes building with libgfxinit in x86_64 mode, which can generates unsupported R_X86_64_32S relocations without -mcmodel=large. Change-Id: If5162fae475f3e70c856d9664a8cfc6a89d82283 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55549 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M toolchain.inc 1 file changed, 7 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Arthur Heymans: Looks good to me, but someone else must approve diff --git a/toolchain.inc b/toolchain.inc index 18c6ab2..80dab78 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -50,6 +50,13 @@ CFLAGS_x86_64 += -mcmodel=large -mno-red-zone CFLAGS_ppc64 += +GCC_ADAFLAGS_arm += +GCC_ADAFLAGS_arm64 += -mgeneral-regs-only +GCC_ADAFLAGS_riscv += +GCC_ADAFLAGS_x86_32 += +GCC_ADAFLAGS_x86_64 += -mcmodel=large -mno-red-zone +GCC_ADAFLAGS_ppc64 += + # Some boards only provide 2K stacks, so storing lots of data there leads to # problems. Since C rules don't allow us to statically determine the maximum # stack use, we use 1.5K as heuristic, assuming that we typically have lots -- To view, visit https://review.coreboot.org/c/coreboot/+/55549 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5162fae475f3e70c856d9664a8cfc6a89d82283 Gerrit-Change-Number: 55549 Gerrit-PatchSet: 4 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: QEMU: Only call `pci_assign_irqs` with non-NULL dev
by Patrick Georgi (Code Review) 01 Jul '21

01 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55900 ) Change subject: QEMU: Only call `pci_assign_irqs` with non-NULL dev ...................................................................... QEMU: Only call `pci_assign_irqs` with non-NULL dev Do not call `pci_assign_irqs` with a NULL device pointer. Change-Id: Ide9ae38dedd881ed673ba1838a1e29529b306937 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55900 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/emulation/qemu-i440fx/mainboard.c M src/mainboard/emulation/qemu-q35/mainboard.c 2 files changed, 15 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/mainboard/emulation/qemu-i440fx/mainboard.c b/src/mainboard/emulation/qemu-i440fx/mainboard.c index 218c47f..a7c6b32 100644 --- a/src/mainboard/emulation/qemu-i440fx/mainboard.c +++ b/src/mainboard/emulation/qemu-i440fx/mainboard.c @@ -24,8 +24,11 @@ pc_keyboard_init(NO_AUX_DEVICE); /* setup IRQ routing */ - for (i = 0; i < 32; i++) - pci_assign_irqs(pcidev_on_root(i, 0), qemu_i440fx_irqs + (i % 4)); + for (i = 0; i < 32; i++) { + struct device *d = pcidev_on_root(i, 0); + if (d) + pci_assign_irqs(d, qemu_i440fx_irqs + (i % 4)); + } } static void qemu_nb_read_resources(struct device *dev) diff --git a/src/mainboard/emulation/qemu-q35/mainboard.c b/src/mainboard/emulation/qemu-q35/mainboard.c index e53404d..534f606 100644 --- a/src/mainboard/emulation/qemu-q35/mainboard.c +++ b/src/mainboard/emulation/qemu-q35/mainboard.c @@ -31,11 +31,17 @@ pc_keyboard_init(NO_AUX_DEVICE); /* setup IRQ routing for pci slots */ - for (i = 0; i < 25; i++) - pci_assign_irqs(pcidev_on_root(i, 0), qemu_q35_irqs + (i % 4)); + for (i = 0; i < 25; i++) { + struct device *d = pcidev_on_root(i, 0); + if (d) + pci_assign_irqs(d, qemu_q35_irqs + (i % 4)); + } /* setup IRQ routing southbridge devices */ - for (i = 25; i < 32; i++) - pci_assign_irqs(pcidev_on_root(i, 0), qemu_q35_irqs); + for (i = 25; i < 32; i++) { + struct device *d = pcidev_on_root(i, 0); + if (d) + pci_assign_irqs(d, qemu_q35_irqs); + } } static void qemu_nb_read_resources(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/55900 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide9ae38dedd881ed673ba1838a1e29529b306937 Gerrit-Change-Number: 55900 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/emulation/qemu-i440fx: Tidy up PAM register writes
by Patrick Georgi (Code Review) 01 Jul '21

01 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55899 ) Change subject: mb/emulation/qemu-i440fx: Tidy up PAM register writes ...................................................................... mb/emulation/qemu-i440fx: Tidy up PAM register writes Tidy up the code that programs the PAM (Programmable Attribute Map) registers. Introduce the `D0F0_PAM` macro and use it to replace the magic `0x59` and `0x5a` values in the code. Adjust the range of the for-loop to work with the `D0F0_PAM` macro, and properly indent the loop's body. Change-Id: I9036425d726ffb69737ea6ed36c7a8f61d9d040a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55899 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/emulation/qemu-i440fx/mainboard.c 1 file changed, 5 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve diff --git a/src/mainboard/emulation/qemu-i440fx/mainboard.c b/src/mainboard/emulation/qemu-i440fx/mainboard.c index bc97554..218c47f 100644 --- a/src/mainboard/emulation/qemu-i440fx/mainboard.c +++ b/src/mainboard/emulation/qemu-i440fx/mainboard.c @@ -10,15 +10,15 @@ 11, 10, 10, 11, }; +#define D0F0_PAM(x) (0x59 + (x)) /* 0-6 */ + static void qemu_nb_init(struct device *dev) { /* Map memory at 0xc0000 - 0xfffff */ int i; - uint8_t v = pci_read_config8(dev, 0x59); - v |= 0x30; - pci_write_config8(dev, 0x59, v); - for (i = 0; i < 6; i++) - pci_write_config8(dev, 0x5a + i, 0x33); + pci_or_config8(dev, D0F0_PAM(0), 0x30); + for (i = 1; i <= 6; i++) + pci_write_config8(dev, D0F0_PAM(i), 0x33); /* This sneaked in here, because Qemu does not emulate a SuperIO chip. */ pc_keyboard_init(NO_AUX_DEVICE); -- To view, visit https://review.coreboot.org/c/coreboot/+/55899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9036425d726ffb69737ea6ed36c7a8f61d9d040a Gerrit-Change-Number: 55899 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/asus/p8x7x-series: Add P8C WS as a variant of P8X7X series
by Patrick Georgi (Code Review) 01 Jul '21

01 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55850 ) Change subject: mb/asus/p8x7x-series: Add P8C WS as a variant of P8X7X series ...................................................................... mb/asus/p8x7x-series: Add P8C WS as a variant of P8X7X series Mainboard information can be found in the included documentation. Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> Change-Id: Idb696193e5a67c42adf45e54d455d2dff7681ca7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55850 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- A Documentation/mainboard/asus/p8c_ws.jpg A Documentation/mainboard/asus/p8c_ws.md M Documentation/mainboard/index.md M src/mainboard/asus/p8x7x-series/Kconfig M src/mainboard/asus/p8x7x-series/Kconfig.name M src/mainboard/asus/p8x7x-series/dsdt.asl A src/mainboard/asus/p8x7x-series/variants/p8c_ws/board_info.txt A src/mainboard/asus/p8x7x-series/variants/p8c_ws/cmos.default A src/mainboard/asus/p8x7x-series/variants/p8c_ws/cmos.layout A src/mainboard/asus/p8x7x-series/variants/p8c_ws/data.vbt A src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c A src/mainboard/asus/p8x7x-series/variants/p8c_ws/gma-mainboard.ads A src/mainboard/asus/p8x7x-series/variants/p8c_ws/gpio.c A src/mainboard/asus/p8x7x-series/variants/p8c_ws/hda_verb.c A src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb A src/mainboard/asus/p8x7x-series/variants/p8c_ws/pci.asl 16 files changed, 613 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/Documentation/mainboard/asus/p8c_ws.jpg b/Documentation/mainboard/asus/p8c_ws.jpg new file mode 100644 index 0000000..06bb8b8 --- /dev/null +++ b/Documentation/mainboard/asus/p8c_ws.jpg Binary files differ diff --git a/Documentation/mainboard/asus/p8c_ws.md b/Documentation/mainboard/asus/p8c_ws.md new file mode 100644 index 0000000..a9aa589 --- /dev/null +++ b/Documentation/mainboard/asus/p8c_ws.md @@ -0,0 +1,94 @@ +# ASUS P8C WS + +This page describes how to run coreboot on the [ASUS P8H77-V]. + +## Flashing coreboot + +```eval_rst ++---------------------+----------------+ +| Type | Value | ++=====================+================+ +| Socketed flash | yes | ++---------------------+----------------+ +| Model | W25Q64FVA1Q | ++---------------------+----------------+ +| Size | 8 MiB | ++---------------------+----------------+ +| Package | DIP-8 | ++---------------------+----------------+ +| Write protection | no | ++---------------------+----------------+ +| Dual BIOS feature | no | ++---------------------+----------------+ +| Internal flashing | yes | ++---------------------+----------------+ +``` + +The flash IC is located beside the SATA ports (circled): +![](p8c_ws.jpg) + +### How to flash + +Unlike ordinary desktop boards, the BIOS version 3202 of ASUS P8C WS does not +apply any write protection, so the main SPI flash can be accessed using +[flashrom], and the whole flash is writable. + +The following command may be used to flash coreboot. (To do so, linux kernel +should be started with `iomem=relaxed`) + +``` +# flashrom -p internal -w coreboot.rom +``` + +The flash chip is a socketed DIP-8 SPI flash, so it's also easy to remove and +flash externally. + +## Working +- Intel Xeon E3-1225 V2 with 4 M391B1G73BH0-YK0 UDIMMs, ECC confirmed active +- PS/2 keyboard with SeaBIOS 1.14.0 and Debian GNU/Linux with kernel 5.10.40 +- Both Onboard NIC +- S3 Suspend to RAM +- USB2 on rear and front panel connectors +- USB3 +- Integrated SATA +- CPU Temp sensors (tested PSensor on GNU/Linux) +- LPC TPM on TPM-header (tested tpm-tools with TPM 1.2 Infineon SLB9635TT12) +- Native raminit +- Integrated graphics with libgfxinit (both analog and digital output from DVI-I) +- Nvidia Quadro 600 in all PCIe-16x slots +- Compex WLM200NX (Qualcomm Atheros AR9220) in PCI slot +- Onboard IEEE1394 controller under PCI bus +- Debug output from serial port + +## Untested + +- EHCI debugging +- S/PDIF audio +- PS/2 mouse +- LPT port + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | ++------------------+--------------------------------------------------+ +| Southbridge | bd82x6x | ++------------------+--------------------------------------------------+ +| CPU | model_206ax | ++------------------+--------------------------------------------------+ +| Super I/O | Nuvoton NCT6776F | ++------------------+--------------------------------------------------+ +| EC | None | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+--------------------------------------------------+ +``` + +## Extra resources + +- [Flash chip datasheet][W25Q64FVA1Q] + +[ASUS P8C WS]: https://www.asus.com/supportonly/p8c_ws/helpdesk_knowledge/ +[W25Q64FVA1Q]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf +[flashrom]: https://flashrom.org/Flashrom diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 2e2ba20..2e1d294 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -19,6 +19,7 @@ - [A88XM-E](asus/a88xm-e.md) - [F2A85-M](asus/f2a85-m.md) - [P5Q](asus/p5q.md) +- [P8C WS](asus/p8c_ws.md) - [P8H61-M LX](asus/p8h61-m_lx.md) - [P8H61-M Pro](asus/p8h61-m_pro.md) - [P8H77-V](asus/p8h77-v.md) diff --git a/src/mainboard/asus/p8x7x-series/Kconfig b/src/mainboard/asus/p8x7x-series/Kconfig index 4f4f31b..bc246e7 100644 --- a/src/mainboard/asus/p8x7x-series/Kconfig +++ b/src/mainboard/asus/p8x7x-series/Kconfig @@ -21,6 +21,7 @@ config VARIANT_DIR string + default "p8c_ws" if BOARD_ASUS_P8C_WS default "p8h77-v" if BOARD_ASUS_P8H77_V default "p8z77-m_pro" if BOARD_ASUS_P8Z77_M_PRO default "p8z77-v_lx2" if BOARD_ASUS_P8Z77_V_LX2 @@ -28,6 +29,7 @@ config MAINBOARD_PART_NUMBER string + default "P8C WS" if BOARD_ASUS_P8C_WS default "P8H77-V" if BOARD_ASUS_P8H77_V default "P8Z77-M PRO" if BOARD_ASUS_P8Z77_M_PRO default "P8Z77-V LX2" if BOARD_ASUS_P8Z77_V_LX2 diff --git a/src/mainboard/asus/p8x7x-series/Kconfig.name b/src/mainboard/asus/p8x7x-series/Kconfig.name index 3509eea..b4d8948 100644 --- a/src/mainboard/asus/p8x7x-series/Kconfig.name +++ b/src/mainboard/asus/p8x7x-series/Kconfig.name @@ -1,3 +1,11 @@ +config BOARD_ASUS_P8C_WS + bool "P8C_WS" + select BOARD_ASUS_P8X7X_SERIES + select BOARD_ROMSIZE_KB_8192 + select MAINBOARD_HAS_LPC_TPM + select SUPERIO_NUVOTON_NCT6776 + select USE_NATIVE_RAMINIT + config BOARD_ASUS_P8H77_V bool "P8H77-V" select BOARD_ASUS_P8X7X_SERIES diff --git a/src/mainboard/asus/p8x7x-series/dsdt.asl b/src/mainboard/asus/p8x7x-series/dsdt.asl index e8e2b3a..e93fe97 100644 --- a/src/mainboard/asus/p8x7x-series/dsdt.asl +++ b/src/mainboard/asus/p8x7x-series/dsdt.asl @@ -22,5 +22,8 @@ { #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> + #if CONFIG(BOARD_ASUS_P8C_WS) + #include "variants/p8c_ws/pci.asl" + #endif } } diff --git a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/board_info.txt b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/board_info.txt new file mode 100644 index 0000000..44dcf5b --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asus.com/supportonly/p8c_ws/helpdesk_knowledge/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: 2013 diff --git a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/cmos.default b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/cmos.default new file mode 100644 index 0000000..c7aa620 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/cmos.default @@ -0,0 +1,6 @@ +boot_option=Fallback +debug_level=Debug +nmi=Disable +power_on_after_fail=Disable +sata_mode=AHCI +gfx_uma_size=64M diff --git a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/cmos.layout b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/cmos.layout new file mode 100644 index 0000000..0f9de5e --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/cmos.layout @@ -0,0 +1,86 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 2 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 3 debug_level + +# coreboot config options: southbridge +408 1 e 1 nmi + +409 2 e 4 power_on_after_fail +411 2 e 5 sata_mode + +# coreboot config options: northbridge +416 5 e 6 gfx_uma_size + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations +#ID value text + +# Generic on/off enum +1 0 Disable +1 1 Enable + +# boot_option +2 0 Fallback +2 1 Normal + +# debug_level +3 0 Emergency +3 1 Alert +3 2 Critical +3 3 Error +3 4 Warning +3 5 Notice +3 6 Info +3 7 Debug +3 8 Spew + +# power_on_after_fail +4 0 Disable +4 1 Enable +4 2 Keep + +# sata_mode +5 0 AHCI +5 1 Compatible +5 2 Legacy + +# gfx_uma_size (Intel IGP Video RAM size) +6 0 32M +6 1 64M +6 2 96M +6 3 128M +6 4 160M +6 5 192M +6 6 224M +6 7 256M +6 8 288M +6 9 320M +6 10 352M +6 11 384M +6 12 416M +6 13 448M +6 14 480M +6 15 512M +6 16 1024M + +# ----------------------------------------------------------------- +checksums + +checksum 392 423 984 diff --git a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/data.vbt b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/data.vbt new file mode 100644 index 0000000..fce6b67 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/data.vbt Binary files differ diff --git a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c new file mode 100644 index 0000000..9f84b49 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <device/pnp_ops.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) +#define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI) + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin states */ + pnp_write_config(GLOBAL_DEV, 0x1a, 0xc8); + pnp_write_config(GLOBAL_DEV, 0x1b, 0x0e); + pnp_write_config(GLOBAL_DEV, 0x1c, 0x83); + pnp_write_config(GLOBAL_DEV, 0x24, 0x20); + pnp_write_config(GLOBAL_DEV, 0x27, 0x10); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x68); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x00); + + /* Power RAM in S3 */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x10); + + pnp_set_logical_device(SERIAL_DEV); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + /* Enable UART */ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} diff --git a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/gma-mainboard.ads b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/gma-mainboard.ads new file mode 100644 index 0000000..c9e4326 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/gma-mainboard.ads @@ -0,0 +1,16 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/gpio.c b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/gpio.c new file mode 100644 index 0000000..a93ad6a --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/gpio.c @@ -0,0 +1,183 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio12 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio6 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio48 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio72 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/hda_verb.c b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/hda_verb.c new file mode 100644 index 0000000..574da72 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/hda_verb.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0892, /* Codec Vendor / Device ID: Realtek ALC892 */ + 0x104384fb, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x104384fb), + AZALIA_PIN_CFG(0, 0x11, 0x99430140), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x01011012), + AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x17, 0x01012014), + AZALIA_PIN_CFG(0, 0x18, 0x01a19850), + AZALIA_PIN_CFG(0, 0x19, 0x02a19c60), + AZALIA_PIN_CFG(0, 0x1a, 0x0181305f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4005e601), + AZALIA_PIN_CFG(0, 0x1e, 0x014b6130), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb new file mode 100644 index 0000000..4de539b --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb @@ -0,0 +1,87 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/sandybridge + device domain 0 on + device pci 01.1 on end # PCIEX16_2 (electrical x8) + device pci 06.0 on end # PCIEX16_3 (electrical x4) + subsystemid 0x1043 0x84ca inherit + chip southbridge/intel/bd82x6x + register "gen1_dec" = "0x000c0291" + device pci 1c.0 on end # RP #1: PCIEX16_4 (electrical x4) + device pci 1c.1 off end # RP #2: + device pci 1c.2 off end # RP #3: + device pci 1c.3 off end # RP #4: + device pci 1c.4 on end # RP #5: PCIEX1_1 + device pci 1c.5 on end # RP #6: 82574 GbE #1 + device pci 1c.6 on end # RP #7: 82574 GbE #2 + device pci 1c.7 off end # RP #8: + device pci 1e.0 on end # PCI bridge + device pci 1f.0 on # LPC bridge + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # Parallel + io 0x60 = 0x0378 + irq 0x70 = 5 + drq 0x74 = 4 # No DMA + irq 0xf0 = 0x3c # Printer mode + end + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # UART B, IR + device pnp 2e.5 on # PS/2 KBC + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # Keyboard + irq 0x72 = 12 # Mouse + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO8 + device pnp 2e.107 off end # GPIO9 + device pnp 2e.8 off end # WDT + device pnp 2e.108 off end # GPIO0 + device pnp 2e.208 off end # GPIOA + device pnp 2e.308 off end # GPIO base + device pnp 2e.109 off # GPIO1 + irq 0xf0 = 0xfb + irq 0xf1 = 0x0 + irq 0xf5 = 0xff + irq 0xf7 = 0xff + end + device pnp 2e.209 on # GPIO2 + irq 0xe0 = 0xef + end + device pnp 2e.309 on # GPIO3 + irq 0xea = 0xff + end + device pnp 2e.409 on end # GPIO4 + device pnp 2e.509 on end # GPIO5 + device pnp 2e.609 on end # GPIO6 + device pnp 2e.709 off end # GPIO7 + device pnp 2e.a on # ACPI + irq 0xe6 = 0x0c + irq 0xe7 = 0x11 + irq 0xf2 = 0x5d + end + device pnp 2e.b on # HWM, LED + io 0x60 = 0x0290 + io 0x62 = 0x0000 + end + device pnp 2e.d off end # VID + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off # GPIO PP/OD + # Enable i2c slave to 0x1d + irq 0xf0 = 0x9d + end + device pnp 2e.14 off end # SVID + device pnp 2e.16 off end # Deep sleep + device pnp 2e.17 off end # GPIOA + end + chip drivers/pc80/tpm + device pnp c31.0 on end # TPM + end + end + end + end +end diff --git a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/pci.asl b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/pci.asl new file mode 100644 index 0000000..76af84c --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/pci.asl @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +// Intel PCI to PCI bridge 0:1e.0 + +Device (PCIB) +{ + Name (_ADR, 0x001E0000) // _ADR: Address + Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake + + Method (_PRT) // _PRT: PCI Interrupt Routing Table + { + If (PICM) { + Return (Package() { + Package() { 0x0000ffff, 0, 0, 0x10 }, + Package() { 0x0000ffff, 1, 0, 0x11 }, + Package() { 0x0000ffff, 2, 0, 0x12 }, + Package() { 0x0000ffff, 3, 0, 0x13 }, + Package() { 0x0003ffff, 0, 0, 0x13 }, + }) + } + Return (Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + }) + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/55850 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb696193e5a67c42adf45e54d455d2dff7681ca7 Gerrit-Change-Number: 55850 Gerrit-PatchSet: 6 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit July 2021