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Change subject: soc/intel/alderlake: Correct Bus and Device of Touch Host Controller
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Patchset:
PS1:
I have verified that my earlier patch that added those TCH0/1 has mistake and this patch fixes that.
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Change subject: soc/intel/alderlake: Correct Bus and Device of Touch Host Controller
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Update THC BDF as per EDS Section 23
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Change subject: arch/x86: Save resume vector to stack in x86_64 mode
......................................................................
Patch Set 2: Code-Review+1
(2 comments)
File src/arch/x86/wakeup.S:
https://review.coreboot.org/c/coreboot/+/55947/comment/424e3766_96d6a429
PS2, Line 20: It's OK to overwrite the return address at (%rsp) because this
: * function doesn't return.
Is that happening? This looks like a 32bit op so I would expect the upper 4 bytes of 4(%rsp) to be preserved?
https://review.coreboot.org/c/coreboot/+/55947/comment/5a7ea5a7_a4f44043
PS2, Line 23: mov
Explicitly use movl to make sure only 4 bytes get moved?
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Change subject: mb/google/brya: Add HANG_DETECT host event to EC S0ix wake mask
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/55988/comment/026b690f_180ea2dd
PS1, Line 10: BIOS
> BIOS means coreboot?
Yes, but will change.
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Hello build bot (Jenkins), Furquan Shaikh, Paul Menzel, Boris Mittelberg,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/55988
to look at the new patch set (#2).
Change subject: mb/google/brya: Add HANG_DETECT host event to EC S0ix wake mask
......................................................................
mb/google/brya: Add HANG_DETECT host event to EC S0ix wake mask
The brya EC supports S0ix hang detection, but it was not enabled in
coreboot as well, masking that event out of S0ix, therefore add it in to
the EC S0ix wake mask.
TEST=After EC prints "Warning: Detected sleep hang! Waking host up!",
the host actually wakes up
Change-Id: I2c699114abcd9a045a41858c731e4b6fe99d3000
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
---
M src/mainboard/google/brya/variants/baseboard/include/baseboard/ec.h
1 file changed, 3 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/55988/2
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Change subject: soc/intel/alderlake: Set max Pkg C-states to Auto
......................................................................
Patch Set 6: Code-Review+1
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/55706/comment/9739b223_7ed2c122
PS6, Line 9: This patch configures max Pkg C-state to Auto which
: limits the max C-state to deep C-state
fit upto 72col
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/55706/comment/85ae4f50_a0adb34e
PS6, Line 47: /*
: * The Max Pkg Cstate
: * Values 0 - C0/C1, 1 - C2, 2 - C3, 3 - C6, 4 - C7, 5 - C7S, 6 - C8, 7 - C9, 8 - C10,
: * 254 - CPU Default , 255 - Auto.
: */
: enum pkgcstate_limit {
: LIMIT_C0_C1 = 0,
: LIMIT_C2 = 1,
: LIMIT_C3 = 2,
: LIMIT_C6 = 3,
: LIMIT_C7 = 4,
: LIMIT_C7S = 5,
: LIMIT_C8 = 6,
: LIMIT_C9 = 7,
: LIMIT_C10 = 8,
: LIMIT_CPUDEFAULT = 254,
: LIMIT_AUTO = 255,
: };
can we move this to chip.h ?
https://review.coreboot.org/c/coreboot/+/55706/comment/db7bbb4f_27bddcfa
PS6, Line 545: /* Set the Max Pkg C-states to Auto */
do we need this comment? UPD name and assignment is self-explanatory IMHO
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