coreboot-gerrit July 2021

coreboot-gerrit@coreboot.org

1 participants
5824 discussions

Change in coreboot[master]: cpu/intel/common: Create get_cache_info() function
by Subrata Banik (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Rizwan Qureshi, Angel Pons, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55965 ) Change subject: cpu/intel/common: Create get_cache_info() function ...................................................................... Patch Set 1: (2 comments) File src/cpu/intel/common/common_init.c: https://review.coreboot.org/c/coreboot/+/55965/comment/04578145_5ebc4ee3 PS1, Line 331: 0x03 > I assume 0x03 is supposed to be LLC here? Create a macro for that? if we are taking cache_level as argument then do we still need macro ? https://review.coreboot.org/c/coreboot/+/55965/comment/c0b57aaa_da141917 PS1, Line 332: : const size_t assoc = CPUID_CACHE_WAYS_OF_ASSOC(res) + 1; : const size_t partitions = CPUID_CACHE_PHYS_LINE(res) + 1; : const size_t cache_line_size = CPUID_CACHE_COHER_LINE(res) + 1; : const size_t number_of_sets = CPUID_CACHE_NO_OF_SETS(res) + 1; : const size_t cache_size = assoc * partitions * cache_line_size * number_of_sets; : printk(BIOS_INFO, "Cache Information : "); : printk(BIOS_INFO, "assoc=%zd par=%zd line_size=%zd sets=%zd\n", : assoc, partitions, cache_line_size, number_of_sets); : printk(BIOS_INFO, "@@ cache_size 0x%lx bytes\n", cache_size); > also remarkably similar to https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/sr… ... maybe this function should take a parameter for the ecx value passed to CPUID? Yes, this is doable but then only problem is smbios_write_type7_cache_parameters() expects to get those individual fields like level, cache_type, assoc etc. etc. so we have two possible ways: 1. Do we want to execute cpuid instruction several time and return those bit-fields as part of dedicated function like below? static struct cpuid_result get_cpu_cache_parameters(int cache_type) { /* 1. Add a check to detect CPU if it belongs to IA or AMD? */ return cpuid_ext(DETERMINISTIC_CACHE_PARAMETERS_CPUID, cache_type); } size_t get_cpu_cache_type(int cache_type) { struct cpuid_result res = get_cpu_cache_parameters(); return CPUID_CACHE_TYPE(res); } ... 2. Return all cache parameters as part of a single function call. here cache_type is only input argument and rests are output as below? size_t get_cache_info(int cache_type, size_t *assoc, size_t *partitions, ...) { struct cpuid_result res = cpuid_ext(DETERMINISTIC_CACHE_PARAMETERS_CPUID, cache_type); *assoc = CPUID_CACHE_WAYS_OF_ASSOC(res) + 1; *partitions = CPUID_CACHE_PHYS_LINE(res) + 1; ... } Then caller of get_cache_info() function like smbios_write_type7_cache_parameters() can use these output variables (assoc, partitions) to perform the regular operations. > > `get_cache_info(unsigned int cache_level)` > or similar? > then the SMBIOS code could reuse this function. Yes, this is possible, but need your help to define one path. -- To view, visit https://review.coreboot.org/c/coreboot/+/55965 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0dd701fb47460092448b64c7fa2162f762bf3095 Gerrit-Change-Number: 55965 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 01 Jul 2021 14:45:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/alderlake: Correct Bus and Device of Touch Host Controller
by Varshit B Pandya (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Rizwan Qureshi, Subrata Banik, Patrick Rudolph. Varshit B Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55998 ) Change subject: soc/intel/alderlake: Correct Bus and Device of Touch Host Controller ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/alderlake/include/soc/pci_devs.h: https://review.coreboot.org/c/coreboot/+/55998/comment/05e419c6_1375cf8b PS1, Line 82: > tab? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/55998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41858ea156c8258ea0e7be9e2f67fb0e24144c80 Gerrit-Change-Number: 55998 Gerrit-PatchSet: 2 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 01 Jul 2021 14:20:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/hatch/scout: update gpios and device tree
by Tim Wawrzynczak (Code Review) 01 Jul '21

01 Jul '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55922 ) Change subject: mb/google/hatch/scout: update gpios and device tree ...................................................................... mb/google/hatch/scout: update gpios and device tree Scout-specific changes to puff reference following bring-up - copy baseline changes from genesis - update GPIOs - update PCIe ports for TPUs - remove LSPCON - enable eMMC - disable touch I2C - enable uart BUG=b:187078663 TEST=boot scout BRANCH=none Signed-off-by: Jeff Chase <jnchase(a)google.com> Change-Id: Ic3cb9cf515ab7a4a0ebbee249644dd3f133d8735 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55922 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/hatch/variants/scout/gpio.c M src/mainboard/google/hatch/variants/scout/include/variant/gpio.h M src/mainboard/google/hatch/variants/scout/overridetree.cb 3 files changed, 144 insertions(+), 54 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/hatch/variants/scout/gpio.c b/src/mainboard/google/hatch/variants/scout/gpio.c index 5a911fc..c916d55 100644 --- a/src/mainboard/google/hatch/variants/scout/gpio.c +++ b/src/mainboard/google/hatch/variants/scout/gpio.c @@ -9,33 +9,83 @@ PAD_CFG_GPI(GPP_A16, NONE, DEEP), /* A18 : LAN_PE_ISOLATE_ODL */ PAD_CFG_GPO(GPP_A18, 1, DEEP), + /* A19 : Not connected */ + PAD_NC(GPP_A19, NONE), + /* A20 : Not connected */ + PAD_NC(GPP_A20, NONE), /* A23 : M2_WLAN_INT_ODL */ PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, INVERT), /* B5 : LAN_CLKREQ_ODL */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + /* B6 : M2_SSD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + /* B7 : M2_TPU0_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + /* B8 : CLK_PCIE_REQ3 (not connected) */ + PAD_NC(GPP_B8, NONE), + /* B9 : M2_TPU1_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* B10 : M2_WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* C0 : SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* C1 : SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + /* C3 : PCH_MBCLK1_R (i350) */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + /* C4 : PCH_MBDAT1_R (i350) */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* C6: M2_WLAN_WAKE_ODL */ PAD_CFG_GPI_SCI_LOW(GPP_C6, NONE, DEEP, EDGE_SINGLE), /* C7 : LAN_WAKE_ODL */ PAD_CFG_GPI_SCI_LOW(GPP_C7, NONE, DEEP, EDGE_SINGLE), /* C10 : PCH_PCON_RST_ODL */ PAD_CFG_GPO(GPP_C10, 1, DEEP), - /* C11 : PCH_PCON_PDB_ODL */ + /* C11 : PCH_PCON1_PDB_ODL */ PAD_CFG_GPO(GPP_C11, 1, DEEP), + /* C12 : PCH_RX_TSUM_UART_TX */ + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), + /* C13 : PCH_RX_TSUM_UART_RX */ + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* C15 : WLAN_OFF_L */ PAD_CFG_GPO(GPP_C15, 1, DEEP), - /* E2 : EN_PP_MST_OD */ - PAD_CFG_GPO(GPP_E2, 1, DEEP), - /* E9 : USB_A0_OC_ODL */ - PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* + * TODO(b/187094460): Re-enable touch screen I2C after resolving USB + * conflict + */ + + /* C18 : PCH_I2C_USI_SDA */ + PAD_NC(GPP_C18, NONE), + /* C19 : PCH_I2C_USI_SDL */ + PAD_NC(GPP_C19, NONE), + + /* D13 : SMBUS_ISP_SCALAR */ + PAD_CFG_GPO(GPP_D13, 0, DEEP), + /* D14 : EC_PCH_INT_L */ + PAD_CFG_GPI_APIC(GPP_D14, NONE, PLTRST, LEVEL, INVERT), + /* D15 : USI_RST_L */ + PAD_CFG_GPO(GPP_D15, 1, DEEP), + + /* E2 : Not connected */ + PAD_NC(GPP_E2, NONE), + /* E3 : TPU_RST_PIN40 */ + PAD_CFG_GPO(GPP_E3, 1, DEEP), + /* E7 : TPU_RST_PIN42 */ + PAD_CFG_GPO(GPP_E7, 1, DEEP), + /* E9 : PU 10K to PP3300_SOC_A */ + PAD_NC(GPP_E9, NONE), /* E10 : USB_A1_OC_ODL */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + /* E15 : PCH_TYPEC_UPFB */ + PAD_CFG_GPI(GPP_E15, NONE, DEEP), + + /* E18 : DDI1_CLK */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), + /* E19 : DDI1_DATA */ + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* F11 : EMMC_CMD */ PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), @@ -66,6 +116,10 @@ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), /* H5: PCH_I2C_PCON_SCL */ PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H6 : PCH_I2C_TPU_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : PCH_I2C_TPU_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), /* H22 : PWM_PP3300_BIOZZER */ PAD_CFG_GPO(GPP_H22, 0, DEEP), }; diff --git a/src/mainboard/google/hatch/variants/scout/include/variant/gpio.h b/src/mainboard/google/hatch/variants/scout/include/variant/gpio.h index 79a1410..9dd2434 100644 --- a/src/mainboard/google/hatch/variants/scout/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/scout/include/variant/gpio.h @@ -5,4 +5,7 @@ #include <baseboard/gpio.h> +#undef EC_SYNC_IRQ +#define EC_SYNC_IRQ GPP_D14_IRQ + #endif diff --git a/src/mainboard/google/hatch/variants/scout/overridetree.cb b/src/mainboard/google/hatch/variants/scout/overridetree.cb index a30dad0..a6e1150 100644 --- a/src/mainboard/google/hatch/variants/scout/overridetree.cb +++ b/src/mainboard/google/hatch/variants/scout/overridetree.cb @@ -13,7 +13,7 @@ [PchSerialIoIndexSPI1] = PchSerialIoPci, [PchSerialIoIndexSPI2] = PchSerialIoDisabled, [PchSerialIoIndexUART0] = PchSerialIoSkipInit, - [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART1] = PchSerialIoPci, [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" @@ -182,16 +182,49 @@ }, }" - # PCIe port 7 for LAN + # PCIe root port 7 for LAN register "PcieRpEnable[6]" = "1" register "PcieRpLtrEnable[6]" = "1" - # PCIe port 11 (x2) for NVMe hybrid storage devices - register "PcieRpEnable[10]" = "1" - register "PcieRpLtrEnable[10]" = "1" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" register "PcieClkSrcClkReq[0]" = "0" + # PCIe root port 8 for WLAN + register "PcieRpEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "1" + # Uses CLK SRC 3 + register "PcieClkSrcUsage[3]" = "7" + register "PcieClkSrcClkReq[3]" = "3" + + # PCIe root port 9 for SSD (PCIe Lanes 9-12) + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + # RP 9 uses CLK SRC 1 + register "PcieClkSrcUsage[1]" = "8" + register "PcieClkSrcClkReq[1]" = "1" + + # PCIe root port 10-12 disabled + register "PcieRpEnable[9]" = "0" + register "PcieRpEnable[10]" = "0" + register "PcieRpEnable[11]" = "0" + + # PCIe root port 13 TPU0 + register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" + # RP 13 uses CLK SRC 2 + register "PcieClkSrcUsage[2]" = "12" + register "PcieClkSrcClkReq[2]" = "2" + + # PCIe root port 14 TPU1 + register "PcieRpEnable[13]" = "1" + register "PcieRpLtrEnable[13]" = "1" + # RP 14 uses CLK SRC 4 + register "PcieClkSrcUsage[4]" = "13" + register "PcieClkSrcClkReq[4]" = "4" + + register "PcieRpEnable[14]" = "0" + register "PcieRpEnable[15]" = "0" + # GPIO for SD card detect register "sdcard_cd_gpio" = "vSD3_CD_B" @@ -205,38 +238,35 @@ chip drivers/intel/dptf ## Active Policy register "policies.active[0]" = "{.target=DPTF_CPU, - .thresholds={TEMP_PCT(90, 85), - TEMP_PCT(85, 75), - TEMP_PCT(80, 65), - TEMP_PCT(75, 55), - TEMP_PCT(70, 45),}}" + .thresholds={TEMP_PCT(94, 0),}}" register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, - .thresholds={TEMP_PCT(50, 85), - TEMP_PCT(47, 75), - TEMP_PCT(45, 65), - TEMP_PCT(42, 55), - TEMP_PCT(39, 45),}}" + .thresholds={TEMP_PCT(72, 90), + TEMP_PCT(68, 80), + TEMP_PCT(62, 70), + TEMP_PCT(54, 60), + TEMP_PCT(46, 50), + TEMP_PCT(39, 40),}}" ## Passive Policy - register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 93, 5000)" - register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 6000)" + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000)" ## Critical Policy register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" - register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN)" ## Power Limits Control # PL1 is fixed at 15W, avg over 28-32s interval - # 25-64W PL2 in 1000mW increments, avg over 28-32s interval + # 51-51W PL2 in 1000mW increments, avg over 28-32s interval register "controls.power_limits.pl1" = "{ .min_power = 15000, .max_power = 15000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 200,}" + .granularity = 125,}" register "controls.power_limits.pl2" = "{ - .min_power = 25000, - .max_power = 64000, + .min_power = 51000, + .max_power = 51000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 1000,}" @@ -333,15 +363,13 @@ device usb 3.3 on end end chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Rear Left"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 0)" - device usb 3.4 on end + # USB3 Port 5 is not populated + device usb 3.4 off end end chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Rear Middle"" + register "desc" = ""USB3 M.2 HDMI-to-USB"" register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 1)" + register "group" = "ACPI_PLD_GROUP(2, 0)" device usb 3.5 on end end end @@ -351,22 +379,9 @@ # RFU - Reserved for Future Use. end # I2C #0 device pci 15.1 off end # I2C #1 - device pci 15.2 on - chip drivers/i2c/generic - register "hid" = ""1AF80175"" - register "name" = ""PS17"" - register "desc" = ""Parade PS175"" - device i2c 4a on end - end - end # I2C #2, PCON PS175. - device pci 15.3 on - chip drivers/i2c/generic - register "hid" = ""10EC2142"" - register "name" = ""RTD2"" - register "desc" = ""Realtek RTD2142"" - device i2c 4a on end - end - end # I2C #3, Realtek RTD2142. + device pci 15.2 off end # I2C #2, PCON PS175. + device pci 15.3 off end # I2C #3, Realtek RTD2142. + device pci 16.0 on end # Management Engine Interface 1 device pci 19.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" @@ -381,9 +396,9 @@ device i2c 1a on end end end #I2C #4 - device pci 1a.0 on end # eMMC - device pci 1c.6 on - chip drivers/net + device pci 1a.0 on end # eMMC + device pci 1c.6 on # PCI Root Port 7 (LAN) + chip drivers/net # RTL8111H Ethernet NIC register "customized_leds" = "0x05af" register "wake" = "GPE0_DW1_07" # GPP_C7 register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A18)" @@ -393,8 +408,26 @@ register "device_index" = "0" device pci 00.0 on end end - end # RTL8111H Ethernet NIC - device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) + end + device pci 1c.7 on # PCI Root Port 8 (WLAN) + register "PcieRpSlotImplemented[7]" = "1" # M.2 Slot + end + device pci 1d.0 on # PCI Root Port 9 (SSD) + register "PcieRpSlotImplemented[8]" = "1" # M.2 Slot + end + device pci 1d.1 off end # PCI Root Port 10 (Not connected) + device pci 1d.2 off end # PCI Root Port 11 (Not connected) + device pci 1d.3 off end # PCI Root Port 12 (Not connected) + device pci 1d.4 on # PCI Root Port 13 (TPU0) + register "PcieRpSlotImplemented[12]" = "1" # M.2 Slot + end + device pci 1d.5 on # PCI Root Port 14 (TPU1) + register "PcieRpSlotImplemented[13]" = "1" # M.2 Slot + end + device pci 1d.6 on end # PCI Root Port 15 (non-root) + device pci 1d.7 on end # PCI Root Port 16 (non-root) + device pci 1e.0 on end # UART #0 + device pci 1e.1 on end # UART #1 device pci 1e.3 off end # GSPI #1 end -- To view, visit https://review.coreboot.org/c/coreboot/+/55922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3cb9cf515ab7a4a0ebbee249644dd3f133d8735 Gerrit-Change-Number: 55922 Gerrit-PatchSet: 2 Gerrit-Owner: Jeff Chase <jnchase(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Joe Tessler <jrt(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/intel/alderlake: Correct Bus and Device of Touch Host Controller
by Subrata Banik (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Varshit B Pandya, Maulik V Vaghela, Tim Wawrzynczak, Rizwan Qureshi, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55998 ) Change subject: soc/intel/alderlake: Correct Bus and Device of Touch Host Controller ...................................................................... Patch Set 1: Code-Review+1 (1 comment) File src/soc/intel/alderlake/include/soc/pci_devs.h: https://review.coreboot.org/c/coreboot/+/55998/comment/60f55d3d_18cd5d0a PS1, Line 82: tab? -- To view, visit https://review.coreboot.org/c/coreboot/+/55998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41858ea156c8258ea0e7be9e2f67fb0e24144c80 Gerrit-Change-Number: 55998 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 01 Jul 2021 14:05:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/alderlake: Correct Bus and Device of Touch Host Controller
by Subrata Banik (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Varshit B Pandya, Maulik V Vaghela, Tim Wawrzynczak, Rizwan Qureshi, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55998 ) Change subject: soc/intel/alderlake: Correct Bus and Device of Touch Host Controller ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: I have verified that my earlier patch that added those TCH0/1 has mistake and this patch fixes that. -- To view, visit https://review.coreboot.org/c/coreboot/+/55998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41858ea156c8258ea0e7be9e2f67fb0e24144c80 Gerrit-Change-Number: 55998 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 01 Jul 2021 14:05:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/alderlake: Correct Bus and Device of Touch Host Controller
by Subrata Banik (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Varshit B Pandya, Maulik V Vaghela, Tim Wawrzynczak, Rizwan Qureshi, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55998 ) Change subject: soc/intel/alderlake: Correct Bus and Device of Touch Host Controller ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Update THC BDF as per EDS Section 23 -- To view, visit https://review.coreboot.org/c/coreboot/+/55998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41858ea156c8258ea0e7be9e2f67fb0e24144c80 Gerrit-Change-Number: 55998 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 01 Jul 2021 14:04:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya: Swap P-sensor IRQ
by Tim Wawrzynczak (Code Review) 01 Jul '21

01 Jul '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55977 ) Change subject: mb/google/brya: Swap P-sensor IRQ ...................................................................... mb/google/brya: Swap P-sensor IRQ P-sensor is swap by the latest schematic. Thus, swap the IRQ for correct P-sensor. BUG=b:192331122,b:181555900 TEST=check P-sensor driver can be probed without error. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I3ccb31c1925e476e2ebb34b2439a491759472405 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55977 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/brya0/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index 5bb93e5..9ef7478 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -326,7 +326,7 @@ device ref i2c2 on chip drivers/i2c/sx9324 register "desc" = ""SAR1 Proximity Sensor"" - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H19_IRQ)" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" register "speed" = "I2C_SPEED_FAST" register "uid" = "1" register "reg_gnrl_ctrl0" = "0x16" @@ -374,7 +374,7 @@ end chip drivers/i2c/sx9324 register "desc" = ""SAR2 Proximity Sensor"" - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H19_IRQ)" register "speed" = "I2C_SPEED_FAST" register "uid" = "2" register "reg_gnrl_ctrl0" = "0x16" -- To view, visit https://review.coreboot.org/c/coreboot/+/55977 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ccb31c1925e476e2ebb34b2439a491759472405 Gerrit-Change-Number: 55977 Gerrit-PatchSet: 2 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: arch/x86: Save resume vector to stack in x86_64 mode
by Arthur Heymans (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Iru Cai, Iru Cai (vimacs). Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55947 ) Change subject: arch/x86: Save resume vector to stack in x86_64 mode ...................................................................... Patch Set 2: Code-Review+1 (2 comments) File src/arch/x86/wakeup.S: https://review.coreboot.org/c/coreboot/+/55947/comment/424e3766_96d6a429 PS2, Line 20: It's OK to overwrite the return address at (%rsp) because this : * function doesn't return. Is that happening? This looks like a 32bit op so I would expect the upper 4 bytes of 4(%rsp) to be preserved? https://review.coreboot.org/c/coreboot/+/55947/comment/5a7ea5a7_a4f44043 PS2, Line 23: mov Explicitly use movl to make sure only 4 bytes get moved? -- To view, visit https://review.coreboot.org/c/coreboot/+/55947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45f2678071b2511c0af5dce9d9b73ac70dfd7252 Gerrit-Change-Number: 55947 Gerrit-PatchSet: 2 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Attention: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Comment-Date: Thu, 01 Jul 2021 13:47:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya: Add HANG_DETECT host event to EC S0ix wake mask
by Tim Wawrzynczak (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Paul Menzel, Boris Mittelberg. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55988 ) Change subject: mb/google/brya: Add HANG_DETECT host event to EC S0ix wake mask ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/55988/comment/026b690f_180ea2dd PS1, Line 10: BIOS > BIOS means coreboot? Yes, but will change. -- To view, visit https://review.coreboot.org/c/coreboot/+/55988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c699114abcd9a045a41858c731e4b6fe99d3000 Gerrit-Change-Number: 55988 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Thu, 01 Jul 2021 13:45:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya: Add HANG_DETECT host event to EC S0ix wake mask
by Tim Wawrzynczak (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Tim Wawrzynczak, Boris Mittelberg. Hello build bot (Jenkins), Furquan Shaikh, Paul Menzel, Boris Mittelberg, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55988 to look at the new patch set (#2). Change subject: mb/google/brya: Add HANG_DETECT host event to EC S0ix wake mask ...................................................................... mb/google/brya: Add HANG_DETECT host event to EC S0ix wake mask The brya EC supports S0ix hang detection, but it was not enabled in coreboot as well, masking that event out of S0ix, therefore add it in to the EC S0ix wake mask. TEST=After EC prints "Warning: Detected sleep hang! Waking host up!", the host actually wakes up Change-Id: I2c699114abcd9a045a41858c731e4b6fe99d3000 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/baseboard/include/baseboard/ec.h 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/55988/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c699114abcd9a045a41858c731e4b6fe99d3000 Gerrit-Change-Number: 55988 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit July 2021