coreboot-gerrit July 2021

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Change in coreboot[master]: cpu/intel/common: Create get_cache_info() function
by Tim Wawrzynczak (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Furquan Shaikh, Rizwan Qureshi, Subrata Banik, Angel Pons, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55965 ) Change subject: cpu/intel/common: Create get_cache_info() function ...................................................................... Patch Set 1: (2 comments) File src/cpu/intel/common/common_init.c: https://review.coreboot.org/c/coreboot/+/55965/comment/b9d844fd_aaa1929c PS1, Line 329: get_cache_info > @Tim, do you think we can move this code into x86 common ? and make same logic as https://review. […] Yeah that sounds good, take the leaf and the ecx argument https://review.coreboot.org/c/coreboot/+/55965/comment/50c818f5_596ef2c9 PS1, Line 331: 0x03 > if we are taking cache_level as argument then do we still need macro ? For this case, it would still be useful, `#define INTEL_CACHE_PARAMETERS_CPUID_LAST_LEVEL_CACHE 0x03` or similar -- To view, visit https://review.coreboot.org/c/coreboot/+/55965 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0dd701fb47460092448b64c7fa2162f762bf3095 Gerrit-Change-Number: 55965 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 01 Jul 2021 16:42:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: configs: Build test x86_64 on Sandy Bridge
by Patrick Rudolph (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Angel Pons. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55472 ) Change subject: configs: Build test x86_64 on Sandy Bridge ...................................................................... Patch Set 10: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/55472/comment/c538ed04_2e299e31 PS8, Line 7: Sandybridge > Sandy Bridge Done https://review.coreboot.org/c/coreboot/+/55472/comment/193d0ad7_06fcff61 PS8, Line 9: on real hardware > on Sandy Bridge Done -- To view, visit https://review.coreboot.org/c/coreboot/+/55472 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c18af8bfa87636c68741e4759059276c287d052 Gerrit-Change-Number: 55472 Gerrit-PatchSet: 10 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 01 Jul 2021 16:42:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: configs: Build test x86_64 on Sandy Bridge
by Patrick Rudolph (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Patrick Rudolph. Hello build bot (Jenkins), Angel Pons, Arthur Heymans, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55472 to look at the new patch set (#10). Change subject: configs: Build test x86_64 on Sandy Bridge ...................................................................... configs: Build test x86_64 on Sandy Bridge Add defconfig to build test x86_64 code on Sandy Bridge. Change-Id: I2c18af8bfa87636c68741e4759059276c287d052 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- A configs/config.hp_compaq_8200_elite_sff_pc.x86_64 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/55472/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/55472 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c18af8bfa87636c68741e4759059276c287d052 Gerrit-Change-Number: 55472 Gerrit-PatchSet: 10 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/intel/gma: Move extended VBT just below opregion
by Tim Wawrzynczak (Code Review) 01 Jul '21

01 Jul '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55341 ) Change subject: drivers/intel/gma: Move extended VBT just below opregion ...................................................................... drivers/intel/gma: Move extended VBT just below opregion Currently the flow for opregion init is as below: 1. Allocate memory for opregion first (cbmem_add(opregion)) 2. Check if VBT size > 6 KiB (this requires extended VBT support) 3. In case of extended VBT requirement, we allocate another chunk of memory which is equal to size of VBT (cbmem_add(extended_vbt)) 4. Pass physical address pointer to OS via RVDA We can optimize the above flow to allocate single chunk of memory by checking VBT size in earlier step. The new optimized flow for opregion init is as below: 1. Check if VBT size > 6 KiB (this requires extended VBT support) 2. In case of extended VBT requirement, total memory to be allocated is calculated as sizeof(opregion) + sizeof (extended_vbt) In case where VBT size is < 6 KiB, total memory requirement would be equal to sizeof(opregion) 3. Based on above calculation, allocate single chunk of memory based on total size. This will also be helpful for the case of virtualization where guest users don't have access to physical address and when it needs relative address of VBT compared to absolute address. In case of opregion 2.1 spec, we need to pass relative address of VBT from opregion base in RVDA. This optimization will help in meeting this requirement since relative address of extended VBT is easy to get. This change will ensure that it meets opregion specification requirement and will be compatible with future versions as well. BUG=b:190019970 BRANCH=None TEST=check the address of extended VBT region and address is coming correctly. Change-Id: Ic0e255df63145409096b0b9312c6c51c05f49931 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55341 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/drivers/intel/gma/opregion.c 1 file changed, 24 insertions(+), 15 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/drivers/intel/gma/opregion.c b/src/drivers/intel/gma/opregion.c index 49938e0..799c7fd 100644 --- a/src/drivers/intel/gma/opregion.c +++ b/src/drivers/intel/gma/opregion.c @@ -265,13 +265,28 @@ return (vbt->hdr_vbt_size > sizeof(opregion->vbt.gvd1)); } +/* + * Copy extended VBT at the end of opregion and fill rvda and rvds + * values correctly for the opregion. + */ +static void opregion_add_ext_vbt(igd_opregion_t *opregion, uint8_t *ext_vbt, + optionrom_vbt_t *vbt) +{ + /* Copy VBT into extended VBT region (at offset 8 KiB) */ + memcpy(ext_vbt, vbt, vbt->hdr_vbt_size); + + /* Fill RVDA value with address of physical pointer */ + opregion->mailbox3.rvda = (uintptr_t)ext_vbt; + opregion->mailbox3.rvds = vbt->hdr_vbt_size; +} + /* Initialize IGD OpRegion, called from ACPI code and OS drivers */ enum cb_err intel_gma_init_igd_opregion(void) { igd_opregion_t *opregion; struct region_device rdev; optionrom_vbt_t *vbt = NULL; - optionrom_vbt_t *ext_vbt = NULL; + size_t opregion_size = sizeof(igd_opregion_t); if (acpi_is_wakeup_s3()) return intel_gma_restore_opregion(); @@ -291,13 +306,16 @@ return CB_ERR; } - opregion = cbmem_add(CBMEM_ID_IGD_OPREGION, sizeof(*opregion)); + if (is_ext_vbt_required(opregion, vbt)) + opregion_size += vbt->hdr_vbt_size; + + opregion = cbmem_add(CBMEM_ID_IGD_OPREGION, opregion_size); if (!opregion) { printk(BIOS_ERR, "GMA: Failed to add IGD OpRegion to CBMEM.\n"); return CB_ERR; } - memset(opregion, 0, sizeof(igd_opregion_t)); + memset(opregion, 0, opregion_size); memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE, sizeof(opregion->header.signature)); @@ -305,18 +323,9 @@ ARRAY_SIZE(vbt->coreblock_biosbuild)); /* Extended VBT support */ if (is_ext_vbt_required(opregion, vbt)) { - ext_vbt = cbmem_add(CBMEM_ID_EXT_VBT, vbt->hdr_vbt_size); - - if (ext_vbt == NULL) { - printk(BIOS_ERR, - "GMA: Unable to add Ext VBT to cbmem!\n"); - rdev_munmap(&rdev, vbt); - return CB_ERR; - } - - memcpy(ext_vbt, vbt, vbt->hdr_vbt_size); - opregion->mailbox3.rvda = (uintptr_t)ext_vbt; - opregion->mailbox3.rvds = vbt->hdr_vbt_size; + /* Place extended VBT just after opregion */ + uint8_t *ext_vbt = (uint8_t *)opregion + sizeof(*opregion); + opregion_add_ext_vbt(opregion, ext_vbt, vbt); } else { /* Raw VBT size which can fit in gvd1 */ memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size); -- To view, visit https://review.coreboot.org/c/coreboot/+/55341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0e255df63145409096b0b9312c6c51c05f49931 Gerrit-Change-Number: 55341 Gerrit-PatchSet: 18 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: merged

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Change in coreboot[master]: util/cbfstool: Remove legacy cbfs support
by Arthur Heymans (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Arthur Heymans. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56001 to look at the new patch set (#5). Change subject: util/cbfstool: Remove legacy cbfs support ...................................................................... util/cbfstool: Remove legacy cbfs support FMAP has been there for quite some time and the coreboot code itself cannot handle legacy images anymore so it makes sense to drop support in cbfstool itself. Change-Id: I2f34a25dae1ec1924cabe392dcd1480d7b4fbf49 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/cbfstool/cbfs_image.c M util/cbfstool/cbfs_image.h M util/cbfstool/cbfstool.c 3 files changed, 37 insertions(+), 283 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/56001/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/56001 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f34a25dae1ec1924cabe392dcd1480d7b4fbf49 Gerrit-Change-Number: 56001 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cbfstool/cbfs-mkstage.c: Change signature of parse_elf_to_xip_stage()
by 9elements QA (Code Review) 01 Jul '21

01 Jul '21

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55792 ) Change subject: cbfstool/cbfs-mkstage.c: Change signature of parse_elf_to_xip_stage() ...................................................................... Patch Set 3: Automatic boot test returned (PASS/FAIL/TOTAL): 6 / 1 / 7 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/65991 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/65990 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/65989 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/65988 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/65987 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/65985 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/65984 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/55792 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie36f64f55d4fc7034780116c28aaed65aa304d5e Gerrit-Change-Number: 55792 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 01 Jul 2021 16:17:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/intel/common: Create get_cache_info() function
by Subrata Banik (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Rizwan Qureshi, Angel Pons, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55965 ) Change subject: cpu/intel/common: Create get_cache_info() function ...................................................................... Patch Set 1: (2 comments) File src/cpu/intel/common/common_init.c: https://review.coreboot.org/c/coreboot/+/55965/comment/9fdc7005_73104cf6 PS1, Line 329: get_cache_info @Tim, do you think we can move this code into x86 common ? and make same logic as https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/sr… to pass the correct leaf https://review.coreboot.org/c/coreboot/+/55965/comment/45cb81d9_858cff78 PS1, Line 332: : const size_t assoc = CPUID_CACHE_WAYS_OF_ASSOC(res) + 1; : const size_t partitions = CPUID_CACHE_PHYS_LINE(res) + 1; : const size_t cache_line_size = CPUID_CACHE_COHER_LINE(res) + 1; : const size_t number_of_sets = CPUID_CACHE_NO_OF_SETS(res) + 1; : const size_t cache_size = assoc * partitions * cache_line_size * number_of_sets; : printk(BIOS_INFO, "Cache Information : "); : printk(BIOS_INFO, "assoc=%zd par=%zd line_size=%zd sets=%zd\n", : assoc, partitions, cache_line_size, number_of_sets); : printk(BIOS_INFO, "@@ cache_size 0x%lx bytes\n", cache_size); > looking a little closer, I'm not sure if we'd SMBIOS (generic x86 code) to depend on soc/intel/commo […] thats good idea may be -- To view, visit https://review.coreboot.org/c/coreboot/+/55965 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0dd701fb47460092448b64c7fa2162f762bf3095 Gerrit-Change-Number: 55965 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 01 Jul 2021 16:15:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: util/cbfstool: Remove legacy cbfs support
by Arthur Heymans (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Arthur Heymans. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56001 to look at the new patch set (#4). Change subject: util/cbfstool: Remove legacy cbfs support ...................................................................... util/cbfstool: Remove legacy cbfs support FMAP has been there for quite some time and the coreboot code itself cannot handle legacy images anymore so it makes sense to drop support in cbfstool itself. Change-Id: I2f34a25dae1ec1924cabe392dcd1480d7b4fbf49 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/cbfstool/cbfs_image.c M util/cbfstool/cbfs_image.h M util/cbfstool/cbfstool.c 3 files changed, 22 insertions(+), 264 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/56001/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/56001 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f34a25dae1ec1924cabe392dcd1480d7b4fbf49 Gerrit-Change-Number: 56001 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/cbfstool: Remove legacy cbfs support
by Arthur Heymans (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Arthur Heymans. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56001 to look at the new patch set (#3). Change subject: util/cbfstool: Remove legacy cbfs support ...................................................................... util/cbfstool: Remove legacy cbfs support FMAP has been there for quite some time and the coreboot code itself cannot handle legacy images anymore so it makes sense to drop support in cbfstool itself. Change-Id: I2f34a25dae1ec1924cabe392dcd1480d7b4fbf49 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/cbfstool/cbfs_image.c M util/cbfstool/cbfs_image.h M util/cbfstool/cbfstool.c 3 files changed, 22 insertions(+), 263 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/56001/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/56001 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f34a25dae1ec1924cabe392dcd1480d7b4fbf49 Gerrit-Change-Number: 56001 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/intel/common: Create get_cache_info() function
by Tim Wawrzynczak (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Furquan Shaikh, Rizwan Qureshi, Subrata Banik, Angel Pons, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55965 ) Change subject: cpu/intel/common: Create get_cache_info() function ...................................................................... Patch Set 1: (1 comment) File src/cpu/intel/common/common_init.c: https://review.coreboot.org/c/coreboot/+/55965/comment/16158e71_76d841aa PS1, Line 332: : const size_t assoc = CPUID_CACHE_WAYS_OF_ASSOC(res) + 1; : const size_t partitions = CPUID_CACHE_PHYS_LINE(res) + 1; : const size_t cache_line_size = CPUID_CACHE_COHER_LINE(res) + 1; : const size_t number_of_sets = CPUID_CACHE_NO_OF_SETS(res) + 1; : const size_t cache_size = assoc * partitions * cache_line_size * number_of_sets; : printk(BIOS_INFO, "Cache Information : "); : printk(BIOS_INFO, "assoc=%zd par=%zd line_size=%zd sets=%zd\n", : assoc, partitions, cache_line_size, number_of_sets); : printk(BIOS_INFO, "@@ cache_size 0x%lx bytes\n", cache_size); > > also remarkably similar to https://review.coreboot. […] looking a little closer, I'm not sure if we'd SMBIOS (generic x86 code) to depend on soc/intel/common code, so maybe this function should go somewhere in arch/x86, maybe arch/x86/cpu_common.c ? -- To view, visit https://review.coreboot.org/c/coreboot/+/55965 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0dd701fb47460092448b64c7fa2162f762bf3095 Gerrit-Change-Number: 55965 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 01 Jul 2021 16:04:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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coreboot-gerrit July 2021