coreboot-gerrit July 2021

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Change in coreboot[master]: soc/intel/alderlake: Enable energy efficiency turbo mode
by Subrata Banik (Code Review) 01 Jul '21

01 Jul '21

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55705 ) Change subject: soc/intel/alderlake: Enable energy efficiency turbo mode ...................................................................... soc/intel/alderlake: Enable energy efficiency turbo mode This patch enables the energy efficiency turbo mode. Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Change-Id: I2d76c948bdc9c208f5728e305b3034fcede6f4bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/55705 Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/alderlake/fsp_params.c 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Maulik V Vaghela: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 7fe996e..783d2a9 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -517,6 +517,8 @@ s_cfg->Hwp = 1; s_cfg->Cx = 1; s_cfg->PsOnEnable = 1; + /* Enable the energy efficient turbo mode */ + s_cfg->EnergyEfficientTurbo = 1; } static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg, -- To view, visit https://review.coreboot.org/c/coreboot/+/55705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d76c948bdc9c208f5728e305b3034fcede6f4bf Gerrit-Change-Number: 55705 Gerrit-PatchSet: 7 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: vagdevi.p(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya0: Update the FIVR configurations
by Subrata Banik (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: V Sowmya, Kedar J. Karanje, Maulik V Vaghela, vagdevi.p(a)intel.com, Tim Wawrzynczak, Vinay Kumar. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55704 ) Change subject: mb/google/brya0: Update the FIVR configurations ...................................................................... Patch Set 3: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/55704/comment/0e449763_d0515a51 PS3, Line 11: bypass rails impletemented. you can fit upto col 72 -- To view, visit https://review.coreboot.org/c/coreboot/+/55704 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c4fdb38c5c56798935b2c6627a75c3f1ac9fbef Gerrit-Change-Number: 55704 Gerrit-PatchSet: 3 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: vagdevi.p(a)intel.com Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: vagdevi.p(a)intel.com Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Comment-Date: Thu, 01 Jul 2021 13:40:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Update the FIVR configurations
by Subrata Banik (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: V Sowmya, Kedar J. Karanje, Maulik V Vaghela, vagdevi.p(a)intel.com, Tim Wawrzynczak, Vinay Kumar. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55703 ) Change subject: mb/intel/adlrvp: Update the FIVR configurations ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55703 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I83e6910502d5cf9d4c26fa581272f59ac483ae19 Gerrit-Change-Number: 55703 Gerrit-PatchSet: 5 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: vagdevi.p(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: vagdevi.p(a)intel.com Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Comment-Date: Thu, 01 Jul 2021 13:39:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add support to update the FIVR configs
by Subrata Banik (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: V Sowmya, Kedar J. Karanje, Maulik V Vaghela, vagdevi.p(a)intel.com, Tim Wawrzynczak, Vinay Kumar, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55702 ) Change subject: soc/intel/alderlake: Add support to update the FIVR configs ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/alderlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/55702/comment/b094a3fa_690c13b5 PS5, Line 543: if (config->ext_fivr_settings.configure_ext_fivr) { if (!config->ext_fivr_settings.configure_ext_fivr) return; would help to reduce one unnecessary tab for you. IMHO -- To view, visit https://review.coreboot.org/c/coreboot/+/55702 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf6c74bda5a167abf63938ebed6affc6b31c76f5 Gerrit-Change-Number: 55702 Gerrit-PatchSet: 5 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: vagdevi.p(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: vagdevi.p(a)intel.com Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 01 Jul 2021 13:39:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: test
by Mars Chen (Code Review) 01 Jul '21

01 Jul '21

Mars Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56000 ) Change subject: test ...................................................................... test Change-Id: I34ad3fab181c7f4a6b52453250a3165097dc8ccb --- A src/test 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/56000/1 diff --git a/src/test b/src/test new file mode 100644 index 0000000..9daeafb --- /dev/null +++ b/src/test @@ -0,0 +1 @@ +test -- To view, visit https://review.coreboot.org/c/coreboot/+/56000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34ad3fab181c7f4a6b52453250a3165097dc8ccb Gerrit-Change-Number: 56000 Gerrit-PatchSet: 1 Gerrit-Owner: Mars Chen <chenxiangrui(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/usb4/retimer: Update code to assign correct port number
by build bot (Jenkins) (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Furquan Shaikh, Paul Menzel, Tim Wawrzynczak. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55945 ) Change subject: drivers/intel/usb4/retimer: Update code to assign correct port number ...................................................................... Patch Set 3: (1 comment) File src/drivers/intel/usb4/retimer/retimer.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123132): https://review.coreboot.org/c/coreboot/+/55945/comment/077e435e_31d76ad6 PS3, Line 359: "%s: No DFP%1d power GPIO for %s \n", __func__, unnecessary whitespace before a quoted newline -- To view, visit https://review.coreboot.org/c/coreboot/+/55945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib11637ae39046e0afdacd33bc34e8a59e6f2bfb1 Gerrit-Change-Number: 55945 Gerrit-PatchSet: 3 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Abhijeet Rao <abhijeet.rao(a)intel.corp-partner.google.com> Gerrit-CC: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 01 Jul 2021 12:39:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/emulation/qemu-i440fx: Tidy up PAM register writes
by 9elements QA (Code Review) 01 Jul '21

01 Jul '21

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55899 ) Change subject: mb/emulation/qemu-i440fx: Tidy up PAM register writes ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 6 / 1 / 7 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/65907 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/65906 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/65905 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/65904 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/65903 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/65901 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/65900 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/55899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9036425d726ffb69737ea6ed36c7a8f61d9d040a Gerrit-Change-Number: 55899 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Thu, 01 Jul 2021 12:23:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: Refactor `xdci_can_enable()` function
by Patrick Georgi (Code Review) 01 Jul '21

01 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55790 ) Change subject: soc/intel: Refactor `xdci_can_enable()` function ...................................................................... soc/intel: Refactor `xdci_can_enable()` function The same pattern appears on all `xdci_can_enable()` call sites. Move the logic inside the function and take the xDCI devfn as parameter. Change-Id: I94c24c10c7fc7c5b4938cffca17bdfb853c7bd59 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55790 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/apollolake/chip.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/common/block/include/intelblocks/xdci.h M src/soc/intel/common/block/xdci/xdci.c M src/soc/intel/elkhartlake/fsp_params.c M src/soc/intel/icelake/fsp_params.c M src/soc/intel/jasperlake/fsp_params.c M src/soc/intel/skylake/chip.c M src/soc/intel/tigerlake/fsp_params.c 10 files changed, 16 insertions(+), 35 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index c814d8c..7fe996e 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -371,10 +371,7 @@ static void fill_fsps_xdci_params(FSP_S_CONFIG *s_cfg, const struct soc_intel_alderlake_config *config) { - /* Enable xDCI controller if enabled in devicetree and allowed */ - if (!xdci_can_enable()) - devfn_disable(pci_root_bus(), PCH_DEVFN_USBOTG); - s_cfg->XdciEnable = is_devfn_enabled(PCH_DEVFN_USBOTG); + s_cfg->XdciEnable = xdci_can_enable(PCH_DEVFN_USBOTG); } static void fill_fsps_uart_params(FSP_S_CONFIG *s_cfg, diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index b9f007d..4cc29e6 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -680,10 +680,7 @@ else apl_fsp_silicon_init_params_cb(cfg, silconfig); - /* Enable xDCI controller if enabled in devicetree and allowed */ - if (!xdci_can_enable()) - devfn_disable(pci_root_bus(), PCH_DEVFN_XDCI); - silconfig->UsbOtg = is_devfn_enabled(PCH_DEVFN_XDCI); + silconfig->UsbOtg = xdci_can_enable(PCH_DEVFN_XDCI); silconfig->VmxEnable = CONFIG(ENABLE_VMX); diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index c3989e5..9d2d722 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -497,10 +497,7 @@ } } - /* Enable xDCI controller if enabled in devicetree and allowed */ - if (!xdci_can_enable()) - devfn_disable(pci_root_bus(), PCH_DEVFN_USBOTG); - params->XdciEnable = is_devfn_enabled(PCH_DEVFN_USBOTG); + params->XdciEnable = xdci_can_enable(PCH_DEVFN_USBOTG); /* Set Debug serial port */ params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; diff --git a/src/soc/intel/common/block/include/intelblocks/xdci.h b/src/soc/intel/common/block/include/intelblocks/xdci.h index 4610590..32d9212 100644 --- a/src/soc/intel/common/block/include/intelblocks/xdci.h +++ b/src/soc/intel/common/block/include/intelblocks/xdci.h @@ -4,6 +4,6 @@ #define SOC_INTEL_COMMON_BLOCK_XDCI_H void soc_xdci_init(struct device *dev); -int xdci_can_enable(void); +bool xdci_can_enable(unsigned int xdci_devfn); #endif /* SOC_INTEL_COMMON_BLOCK_XDCI_H */ diff --git a/src/soc/intel/common/block/xdci/xdci.c b/src/soc/intel/common/block/xdci/xdci.c index 9f15ac1..e1d8809 100644 --- a/src/soc/intel/common/block/xdci/xdci.c +++ b/src/soc/intel/common/block/xdci/xdci.c @@ -8,9 +8,14 @@ __weak void soc_xdci_init(struct device *dev) { /* no-op */ } -int xdci_can_enable(void) +bool xdci_can_enable(unsigned int xdci_devfn) { - return vboot_can_enable_udc(); + /* Enable xDCI controller if enabled in devicetree and allowed */ + if (!vboot_can_enable_udc()) { + devfn_disable(pci_root_bus(), xdci_devfn); + return false; + } + return is_devfn_enabled(xdci_devfn); } static struct device_operations usb_xdci_ops = { diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c index e738d11..210040e 100644 --- a/src/soc/intel/elkhartlake/fsp_params.c +++ b/src/soc/intel/elkhartlake/fsp_params.c @@ -181,10 +181,7 @@ params->UsbClockGatingEnable = 1; params->UsbPowerGatingEnable = 1; - /* Enable xDCI controller if enabled in devicetree and allowed */ - if (!xdci_can_enable()) - devfn_disable(pci_root_bus(), PCH_DEVFN_USBOTG); - params->XdciEnable = is_devfn_enabled(PCH_DEVFN_USBOTG); + params->XdciEnable = xdci_can_enable(PCH_DEVFN_USBOTG); /* PCIe root ports config */ for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index eb608f3..2d63097 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -137,10 +137,7 @@ } } - /* Enable xDCI controller if enabled in devicetree and allowed */ - if (!xdci_can_enable()) - devfn_disable(pci_root_bus(), PCH_DEVFN_USBOTG); - params->XdciEnable = is_devfn_enabled(PCH_DEVFN_USBOTG); + params->XdciEnable = xdci_can_enable(PCH_DEVFN_USBOTG); /* PCI Express */ for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) { diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index 5f33a3b..45bed5e 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -157,10 +157,7 @@ if (params->ScsEmmcEnabled) params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; - /* Enable xDCI controller if enabled in devicetree and allowed */ - if (!xdci_can_enable()) - devfn_disable(pci_root_bus(), PCH_DEVFN_USBOTG); - params->XdciEnable = is_devfn_enabled(PCH_DEVFN_USBOTG); + params->XdciEnable = xdci_can_enable(PCH_DEVFN_USBOTG); /* Provide correct UART number for FSP debug logs */ params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 865fdf0..2599e12 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -456,10 +456,7 @@ /* Show SPI controller if enabled in devicetree.cb */ params->ShowSpiController = is_devfn_enabled(PCH_DEVFN_SPI); - /* Enable xDCI controller if enabled in devicetree and allowed */ - if (!xdci_can_enable()) - devfn_disable(pci_root_bus(), PCH_DEVFN_USBOTG); - params->XdciEnable = is_devfn_enabled(PCH_DEVFN_USBOTG); + params->XdciEnable = xdci_can_enable(PCH_DEVFN_USBOTG); /* Enable or disable Gaussian Mixture Model in devicetree */ params->GmmEnable = is_devfn_enabled(SA_DEVFN_GMM); diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index e7fe51a..afbd747 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -462,10 +462,7 @@ config->tcss_ports[i].ocpin; } - /* Enable xDCI controller if enabled in devicetree and allowed */ - if (!xdci_can_enable()) - devfn_disable(pci_root_bus(), PCH_DEVFN_USBOTG); - params->XdciEnable = is_devfn_enabled(PCH_DEVFN_USBOTG); + params->XdciEnable = xdci_can_enable(PCH_DEVFN_USBOTG); /* PCH UART selection for FSP Debug */ params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; -- To view, visit https://review.coreboot.org/c/coreboot/+/55790 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94c24c10c7fc7c5b4938cffca17bdfb853c7bd59 Gerrit-Change-Number: 55790 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/intel/dptf: Add OEM variables support
by Patrick Georgi (Code Review) 01 Jul '21

01 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50127 ) Change subject: drivers/intel/dptf: Add OEM variables support ...................................................................... drivers/intel/dptf: Add OEM variables support This adds OEM variables feature under DPTF as per BWG doc #541817. Using this, platform vendors can expose an array of OEM-specific values as OEM variables to be used in determining DPTF policy. These are obtained via the ODVP method, and then simply exposed under sysfs. In addition, these gets updated when a notification is received or when the DPTF policy is changed by userspace. BRANCH=None BUG=b:187253038 TEST=Built and tested on dedede board Change-Id: Iaf3cf7b40e9a441b41d0c659d76895a58669c2fb Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50127 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/drivers/intel/dptf/chip.h M src/drivers/intel/dptf/dptf.c 2 files changed, 56 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/drivers/intel/dptf/chip.h b/src/drivers/intel/dptf/chip.h index 5408d9e..59b1e25 100644 --- a/src/drivers/intel/dptf/chip.h +++ b/src/drivers/intel/dptf/chip.h @@ -12,6 +12,9 @@ {.source = DPTF_##src, .temp = (tmp), .type = DPTF_CRITICAL_##typ} #define TEMP_PCT(t, p) {.temp = (t), .fan_pct = (p)} +/* Total number of OEM variables */ +#define DPTF_OEM_VARIABLE_COUNT 6 + struct drivers_intel_dptf_config { struct { struct dptf_active_policy active[DPTF_MAX_ACTIVE_POLICIES]; @@ -51,6 +54,11 @@ const char *desc; } tsr[DPTF_MAX_TSR]; } options; + + /* OEM variables */ + struct { + uint32_t oem_variables[DPTF_OEM_VARIABLE_COUNT]; + } oem_data; }; #endif /* _DRIVERS_INTEL_DPTF_CHIP_H_ */ diff --git a/src/drivers/intel/dptf/dptf.c b/src/drivers/intel/dptf/dptf.c index 7d19df5..f9b4dee 100644 --- a/src/drivers/intel/dptf/dptf.c +++ b/src/drivers/intel/dptf/dptf.c @@ -117,6 +117,53 @@ acpigen_pop_len(); /* Device */ } +/* \_SB.DPTF */ +static void write_oem_variables(const struct drivers_intel_dptf_config *config) +{ + int i; + + acpigen_write_name("ODVX"); + acpigen_write_package(DPTF_OEM_VARIABLE_COUNT); + for (i = 0; i < DPTF_OEM_VARIABLE_COUNT; i++) + acpigen_write_dword(config->oem_data.oem_variables[i]); + acpigen_write_package_end(); + + /* + * Method (ODUP, 2) + * Arg0 = Index of ODVX to update + * Arg1 = Value to place in ODVX[Arg0] + */ + acpigen_write_method_serialized("ODUP", 2); + /* ODVX[Arg0] = Arg1 */ + acpigen_write_store(); + acpigen_emit_byte(ARG1_OP); + acpigen_emit_byte(INDEX_OP); + acpigen_emit_namestring("ODVX"); + acpigen_emit_byte(ARG0_OP); + acpigen_emit_byte(ZERO_OP); /* Ignore Index() Destination */ + acpigen_write_method_end(); + + /* + * Method (ODGT, 1) + * Arg0 = Index of ODVX to get + */ + acpigen_write_method_serialized("ODGT", 1); + /* Return (ODVX[Arg0]) */ + acpigen_emit_byte(RETURN_OP); + acpigen_emit_byte(DEREF_OP); + acpigen_emit_byte(INDEX_OP); + acpigen_emit_namestring("ODVX"); + acpigen_emit_byte(ARG0_OP); + acpigen_emit_byte(ZERO_OP); /* Ignore Index() Destination */ + acpigen_write_method_end(); + + /* Method (ODVP) { Return (ODVX) } */ + acpigen_write_method_serialized("ODVP", 0); + acpigen_emit_byte(RETURN_OP); + acpigen_emit_namestring("ODVX"); + acpigen_write_method_end(); +} + /* \_SB.DPTF.xxxx */ static void write_generic_devices(const struct drivers_intel_dptf_config *config, const struct dptf_platform_info *platform_info) @@ -169,6 +216,7 @@ write_tcpu(parent, config); write_open_dptf_device(dev, platform_info); write_fan(config, platform_info); + write_oem_variables(config); write_generic_devices(config, platform_info); acpigen_pop_len(); /* DPTF Device (write_open_dptf_device) */ -- To view, visit https://review.coreboot.org/c/coreboot/+/50127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf3cf7b40e9a441b41d0c659d76895a58669c2fb Gerrit-Change-Number: 50127 Gerrit-PatchSet: 19 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Todd Broch <tbroch(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: configs: Build test x86_64 on Sandybridge
by Patrick Rudolph (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Patrick Rudolph. Hello build bot (Jenkins), Angel Pons, Arthur Heymans, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55472 to look at the new patch set (#9). Change subject: configs: Build test x86_64 on Sandybridge ...................................................................... configs: Build test x86_64 on Sandybridge Add defconfig to build test x86_64 code on real hardware. Change-Id: I2c18af8bfa87636c68741e4759059276c287d052 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- A configs/config.hp_compaq_8200_elite_sff_pc.x86_64 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/55472/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/55472 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c18af8bfa87636c68741e4759059276c287d052 Gerrit-Change-Number: 55472 Gerrit-PatchSet: 9 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newpatchset

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