coreboot-gerrit July 2021

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Change in coreboot[master]: mb/prodrive/hermes: Implement smbios_mainboard_version
by Patrick Georgi (Code Review) 01 Jul '21

01 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55712 ) Change subject: mb/prodrive/hermes: Implement smbios_mainboard_version ...................................................................... mb/prodrive/hermes: Implement smbios_mainboard_version Return the HSI version read from BMC in smbios_mainboard_version. Change-Id: If907d598c9e05d35f8898d294678f61d075f935a Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55712 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/prodrive/hermes/smbios.c 1 file changed, 10 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/prodrive/hermes/smbios.c b/src/mainboard/prodrive/hermes/smbios.c index 02567d8..af81e86 100644 --- a/src/mainboard/prodrive/hermes/smbios.c +++ b/src/mainboard/prodrive/hermes/smbios.c @@ -2,6 +2,7 @@ #include <smbios.h> #include <types.h> +#include <string.h> #include "variants/baseboard/include/eeprom.h" @@ -26,3 +27,12 @@ else return CONFIG_MAINBOARD_SERIAL_NUMBER; } + +const char *smbios_mainboard_version(void) +{ + static char version_str[8] = { 0 }; + + snprintf(version_str, sizeof(version_str), "HSI %u", get_bmc_hsi()); + + return version_str; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/55712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If907d598c9e05d35f8898d294678f61d075f935a Gerrit-Change-Number: 55712 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede: Create cappy2 variant
by Patrick Georgi (Code Review) 01 Jul '21

01 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55886 ) Change subject: mb/google/dedede: Create cappy2 variant ...................................................................... mb/google/dedede: Create cappy2 variant Create the cappy2 variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:192035460 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_CAPPY2 Signed-off-by: Sunway <lisunwei(a)huaqin.corp-partner.google.com> Change-Id: I772801152b9ca9c2c6afe76a353cb2b62d6210ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/55886 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/Kconfig.name A src/mainboard/google/dedede/variants/cappy2/include/variant/ec.h A src/mainboard/google/dedede/variants/cappy2/include/variant/gpio.h A src/mainboard/google/dedede/variants/cappy2/memory/Makefile.inc A src/mainboard/google/dedede/variants/cappy2/memory/dram_id.generated.txt A src/mainboard/google/dedede/variants/cappy2/memory/mem_parts_used.txt A src/mainboard/google/dedede/variants/cappy2/overridetree.cb 8 files changed, 82 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 29be866..81f28fc 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -114,6 +114,7 @@ default "Pirika" if BOARD_GOOGLE_PIRIKA default "Haboki" if BOARD_GOOGLE_HABOKI default "Cappy" if BOARD_GOOGLE_CAPPY + default "Cappy2" if BOARD_GOOGLE_CAPPY2 config MAX_CPUS int @@ -152,6 +153,7 @@ default "pirika" if BOARD_GOOGLE_PIRIKA default "haboki" if BOARD_GOOGLE_HABOKI default "cappy" if BOARD_GOOGLE_CAPPY + default "cappy2" if BOARD_GOOGLE_CAPPY2 endif #BOARD_GOOGLE_BASEBOARD_DEDEDE diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 1775485..6c908fb 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -153,3 +153,8 @@ bool "-> Cappy" select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 select BASEBOARD_DEDEDE_LAPTOP + +config BOARD_GOOGLE_CAPPY2 + bool "-> Cappy2" + select BOARD_GOOGLE_BASEBOARD_DEDEDE_TPM2 + select BASEBOARD_DEDEDE_LAPTOP diff --git a/src/mainboard/google/dedede/variants/cappy2/include/variant/ec.h b/src/mainboard/google/dedede/variants/cappy2/include/variant/ec.h new file mode 100644 index 0000000..08870e0 --- /dev/null +++ b/src/mainboard/google/dedede/variants/cappy2/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/dedede/variants/cappy2/include/variant/gpio.h b/src/mainboard/google/dedede/variants/cappy2/include/variant/gpio.h new file mode 100644 index 0000000..9078664 --- /dev/null +++ b/src/mainboard/google/dedede/variants/cappy2/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/dedede/variants/cappy2/memory/Makefile.inc b/src/mainboard/google/dedede/variants/cappy2/memory/Makefile.inc new file mode 100644 index 0000000..b0ca222 --- /dev/null +++ b/src/mainboard/google/dedede/variants/cappy2/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! +## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder.spd.hex diff --git a/src/mainboard/google/dedede/variants/cappy2/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/cappy2/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/dedede/variants/cappy2/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/dedede/variants/cappy2/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/cappy2/memory/mem_parts_used.txt new file mode 100644 index 0000000..e4258b5 --- /dev/null +++ b/src/mainboard/google/dedede/variants/cappy2/memory/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/{ddr4,lp4x}. +# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/dedede/variants/cappy2/overridetree.cb b/src/mainboard/google/dedede/variants/cappy2/overridetree.cb new file mode 100644 index 0000000..404024b --- /dev/null +++ b/src/mainboard/google/dedede/variants/cappy2/overridetree.cb @@ -0,0 +1,42 @@ +chip soc/intel/jasperlake + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Trackpad | + #| I2C1 | Digitizer | + #| I2C2 | Touchscreen | + #| I2C3 | Camera | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + }" + + device domain 0 on + device pci 15.0 on end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/55886 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I772801152b9ca9c2c6afe76a353cb2b62d6210ce Gerrit-Change-Number: 55886 Gerrit-PatchSet: 3 Gerrit-Owner: Sunwei Li <lisunwei(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-CC: Zhi7 Li <lizhi7(a)huaqin.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/variants/primus: Update mainboard properties for BB re...
by Patrick Georgi (Code Review) 01 Jul '21

01 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55888 ) Change subject: mb/google/brya/variants/primus: Update mainboard properties for BB retimer upgrade ...................................................................... mb/google/brya/variants/primus: Update mainboard properties for BB retimer upgrade This changes updates mainboard properties by adding DFP number and power_gpio for each DFP. Reference CB:55348 BUG=b:191897776 Signed-off-by: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Change-Id: I63c912980530e5c9f341bdbab18c07685fd77abf Reviewed-on: https://review.coreboot.org/c/coreboot/+/55888 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/brya/variants/primus/overridetree.cb 1 file changed, 16 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb index 897ff0c..36d015d 100644 --- a/src/mainboard/google/brya/variants/primus/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus/overridetree.cb @@ -156,6 +156,22 @@ .flags = PCIE_RP_LTR | PCIE_RP_AER, }" end #PCIE3 BH799BB + device ref tcss_dma0 on + chip drivers/intel/usb4/retimer + register "dfp" = "{ + [0] = {.power_gpio = ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4), + .group = ACPI_PLD_GROUP(1, 1),}}" + device generic 0 on end + end + end + device ref tcss_dma1 on + chip drivers/intel/usb4/retimer + register "dfp" = "{ + [0] = {.power_gpio = ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4), + .group = ACPI_PLD_GROUP(3, 1)}}" + device generic 0 on end + end + end device ref pcie_rp8 on chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" -- To view, visit https://review.coreboot.org/c/coreboot/+/55888 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63c912980530e5c9f341bdbab18c07685fd77abf Gerrit-Change-Number: 55888 Gerrit-PatchSet: 2 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/var/drawcia: Add LTE modem support for drawper
by Patrick Georgi (Code Review) 01 Jul '21

01 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55181 ) Change subject: mb/google/dedede/var/drawcia: Add LTE modem support for drawper ...................................................................... mb/google/dedede/var/drawcia: Add LTE modem support for drawper Add LTE modem to devicetree. Configure GPIO control for LTE modem by fw_config. Update LTE USB port configuration at run-time after probing FW_CONFIG. By default the concerned USB port takes the Type-A port configuration. BUG=b:186393848 TEST=Build image and check with command modem status Change-Id: I20450ae37e5047dba67211316515994bd2a09600 Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55181 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/variants/drawcia/Makefile.inc M src/mainboard/google/dedede/variants/drawcia/gpio.c M src/mainboard/google/dedede/variants/drawcia/overridetree.cb A src/mainboard/google/dedede/variants/drawcia/ramstage.c M src/mainboard/google/dedede/variants/drawcia/variant.c 5 files changed, 83 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/drawcia/Makefile.inc b/src/mainboard/google/dedede/variants/drawcia/Makefile.inc index 04eb9a4..c517214 100644 --- a/src/mainboard/google/dedede/variants/drawcia/Makefile.inc +++ b/src/mainboard/google/dedede/variants/drawcia/Makefile.inc @@ -1,4 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-or-later ramstage-y += gpio.c +ramstage-y += ramstage.c ramstage-$(CONFIG_FW_CONFIG) += variant.c + +smm-y += variant.c diff --git a/src/mainboard/google/dedede/variants/drawcia/gpio.c b/src/mainboard/google/dedede/variants/drawcia/gpio.c index 96b64cc..955d9a0 100644 --- a/src/mainboard/google/dedede/variants/drawcia/gpio.c +++ b/src/mainboard/google/dedede/variants/drawcia/gpio.c @@ -3,6 +3,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> #include <boardid.h> +#include <bootstate.h> #include <fw_config.h> #include <ec/google/chromeec/ec.h> @@ -16,8 +17,27 @@ /* bid6: Pad configuration for board version 6 or 8 in ramstage*/ static const struct pad_config board6or8_gpio_table[] = { + /* A10 : WWAN_EN */ + PAD_CFG_GPO(GPP_A10, 1, PWROK), + + /* B7 : PCIE_CLKREQ2_N ==> WWAN_SAR_DETECT_ODL*/ + PAD_CFG_GPO(GPP_B7, 1, DEEP), + /* C12 : AP_PEN_DET_ODL has an external pull-up and hence no pad termination.*/ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), + + /* D0 : WWAN_HOST_WAKE ==> WWAN_WDISABLE_L */ + PAD_CFG_GPO(GPP_D0, 1, DEEP), + + /* H0 : WWAN_PERST */ + PAD_CFG_GPO(GPP_H0, 0, PLTRST), +}; + +static const struct pad_config lte_disable_pads[] = { + PAD_NC(GPP_A10, NONE), + PAD_NC(GPP_B7, NONE), + PAD_NC(GPP_D0, NONE), + PAD_NC(GPP_H0, NONE), }; const struct pad_config *variant_override_gpio_table(size_t *num) @@ -32,3 +52,10 @@ return not_board6or8_gpio_table; } + +static void fw_config_handle(void *unused) +{ + if (!fw_config_probe(FW_CONFIG(DB_PORTS, DB_PORTS_1A_HDMI_LTE))) + gpio_configure_pads(lte_disable_pads, ARRAY_SIZE(lte_disable_pads)); +} +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index 852af67..175ed22 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -144,10 +144,30 @@ chip drivers/usb/acpi device usb 0.0 on chip drivers/usb/acpi + register "desc" = ""Multi-use Port"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 2.3 on + probe DB_PORTS DB_PORTS_1A_HDMI + probe DB_PORTS DB_PORTS_1C_1A + probe DB_PORTS DB_PORTS_1A_HDMI_LTE + end + end + chip drivers/usb/acpi register "desc" = ""Camera"" register "type" = "UPC_TYPE_INTERNAL" device usb 2.5 on end end + chip drivers/usb/acpi + register "desc" = ""Multi-use Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 3.3 on + probe DB_PORTS DB_PORTS_1A_HDMI + probe DB_PORTS DB_PORTS_1C_1A + probe DB_PORTS DB_PORTS_1A_HDMI_LTE + end + end end end end # USB xHCI diff --git a/src/mainboard/google/dedede/variants/drawcia/ramstage.c b/src/mainboard/google/dedede/variants/drawcia/ramstage.c new file mode 100644 index 0000000..5acc033 --- /dev/null +++ b/src/mainboard/google/dedede/variants/drawcia/ramstage.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> + +static struct acpi_gpio lte_reset_gpio = ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0); +static struct acpi_gpio lte_enable_gpio = ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10); + +void variant_devtree_update(void) +{ + update_lte_device(&lte_reset_gpio, &lte_enable_gpio); +} diff --git a/src/mainboard/google/dedede/variants/drawcia/variant.c b/src/mainboard/google/dedede/variants/drawcia/variant.c index 3b62855..c557fe0 100644 --- a/src/mainboard/google/dedede/variants/drawcia/variant.c +++ b/src/mainboard/google/dedede/variants/drawcia/variant.c @@ -1,7 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <bootstate.h> +#include <acpi/acpi.h> +#include <baseboard/variants.h> +#include <delay.h> #include <drivers/intel/gma/opregion.h> #include <fw_config.h> +#include <gpio.h> #include <sar.h> const char *get_wifi_sar_cbfs_filename(void) @@ -20,3 +25,20 @@ return "vbt.bin"; } + +static void power_off_lte_module(void) +{ + gpio_output(GPP_H0, 0); + mdelay(20); + gpio_output(GPP_A10, 0); +} + +void variant_smi_sleep(u8 slp_typ) +{ + /* + * Once the FW_CONFIG is provisioned, power off LTE module only under + * the situation where it is stuffed. + */ + if (slp_typ == ACPI_S5) + power_off_lte_module(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/55181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20450ae37e5047dba67211316515994bd2a09600 Gerrit-Change-Number: 55181 Gerrit-PatchSet: 9 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kevin Chiu <kevin.chiu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/var/kracko: Update LTE USB port configuration
by Patrick Georgi (Code Review) 01 Jul '21

01 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54671 ) Change subject: mb/google/dedede/var/kracko: Update LTE USB port configuration ...................................................................... mb/google/dedede/var/kracko: Update LTE USB port configuration Update LTE USB port configuration at run-time after probing FW_CONFIG. By default the concerned USB port takes the Type-A port configuration. BUG=b:178092096 BRANCH=dedede TEST=Build and boot to OS to check LTE by modem status Change-Id: If12cc29ddda6d5c32c0bda840a3680e7bf932f89 Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54671 Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/dedede/variants/baseboard/Makefile.inc M src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h A src/mainboard/google/dedede/variants/baseboard/ramstage.c M src/mainboard/google/dedede/variants/kracko/Makefile.inc M src/mainboard/google/dedede/variants/kracko/overridetree.cb A src/mainboard/google/dedede/variants/kracko/ramstage.c M src/mainboard/google/dedede/variants/metaknight/ramstage.c 7 files changed, 79 insertions(+), 54 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/baseboard/Makefile.inc b/src/mainboard/google/dedede/variants/baseboard/Makefile.inc index 4f87de9..a79e163 100644 --- a/src/mainboard/google/dedede/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/dedede/variants/baseboard/Makefile.inc @@ -3,5 +3,6 @@ romstage-y += memory.c ramstage-y += gpio.c +ramstage-y += ramstage.c smm-y += gpio.c diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h index a3dcd91..78e44b4 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h @@ -5,6 +5,7 @@ #include <soc/gpio.h> #include <stdint.h> +#include <acpi/acpi_device.h> /* The next set of functions return the gpio table and fill in the number of * entries for each table. */ @@ -42,4 +43,6 @@ /* Modify devictree settings during ramstage. */ void variant_devtree_update(void); +/* Modify LTE devictree settings during ramstage. */ +void update_lte_device(struct acpi_gpio *lte_reset_gpio, struct acpi_gpio *lte_enable_gpio); #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/dedede/variants/baseboard/ramstage.c b/src/mainboard/google/dedede/variants/baseboard/ramstage.c new file mode 100644 index 0000000..136fe13 --- /dev/null +++ b/src/mainboard/google/dedede/variants/baseboard/ramstage.c @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi_device.h> +#include <baseboard/variants.h> +#include <console/console.h> +#include <drivers/usb/acpi/chip.h> +#include <fw_config.h> +#include <gpio.h> +#include <soc/pci_devs.h> + +#define LTE_USB_PORT_ID 3 +#define LTE_USB_PORT_TYPE 2 + +void update_lte_device(struct acpi_gpio *lte_reset_gpio, struct acpi_gpio *lte_enable_gpio) +{ + struct device *xhci, *hub = NULL, *port = NULL; + struct drivers_usb_acpi_config *config; + + xhci = pcidev_path_on_root(PCH_DEVFN_XHCI); + if (!xhci) { + printk(BIOS_ERR, "%s: Could not locate XHCI device in DT\n", __func__); + return; + } + + while ((hub = dev_bus_each_child(xhci->link_list, hub)) != NULL) { + while ((port = dev_bus_each_child(hub->link_list, port)) != NULL) { + if (!port->chip_info || port->path.usb.port_id != LTE_USB_PORT_ID) + continue; + + if (fw_config_probe(FW_CONFIG(DB_PORTS, DB_PORTS_LTE_HDMI)) || + fw_config_probe(FW_CONFIG(DB_PORTS, DB_PORTS_1C_LTE)) || + fw_config_probe(FW_CONFIG(DB_PORTS, DB_PORTS_1A_HDMI_LTE))) { + + config = port->chip_info; + config->type = UPC_TYPE_INTERNAL; + if (port->path.usb.port_type == LTE_USB_PORT_TYPE) { + config->has_power_resource = 1; + memcpy(&config->reset_gpio, &lte_reset_gpio, + sizeof(config->reset_gpio)); + config->reset_off_delay_ms = 20; + memcpy(&config->enable_gpio, &lte_enable_gpio, + sizeof(config->enable_gpio)); + config->enable_delay_ms = 20; + } + } + } + } +} diff --git a/src/mainboard/google/dedede/variants/kracko/Makefile.inc b/src/mainboard/google/dedede/variants/kracko/Makefile.inc index fd60a18..7412194 100644 --- a/src/mainboard/google/dedede/variants/kracko/Makefile.inc +++ b/src/mainboard/google/dedede/variants/kracko/Makefile.inc @@ -1,5 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-or-later ramstage-y += gpio.c +ramstage-y += ramstage.c smm-y += variant.c diff --git a/src/mainboard/google/dedede/variants/kracko/overridetree.cb b/src/mainboard/google/dedede/variants/kracko/overridetree.cb index dec4c0a..3561898 100644 --- a/src/mainboard/google/dedede/variants/kracko/overridetree.cb +++ b/src/mainboard/google/dedede/variants/kracko/overridetree.cb @@ -63,14 +63,13 @@ chip drivers/usb/acpi device usb 0.0 on chip drivers/usb/acpi - register "desc" = ""LTE"" - register "type" = "UPC_TYPE_INTERNAL" - register "has_power_resource" = "1" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H17)" - register "reset_off_delay_ms" = "20" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" - register "enable_delay_ms" = "20" - device usb 2.3 on end + register "desc" = ""Multi-use Port"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 2.3 on + probe DB_PORTS DB_PORTS_1C_LTE + probe DB_PORTS DB_PORTS_1C_1A + end end chip drivers/usb/acpi register "desc" = ""UFCamera"" @@ -83,9 +82,13 @@ device usb 2.6 on end end chip drivers/usb/acpi - register "desc" = ""LTE"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 3.3 on end + register "desc" = ""Multi-use Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 3.3 on + probe DB_PORTS DB_PORTS_1C_LTE + probe DB_PORTS DB_PORTS_1C_1A + end end end end diff --git a/src/mainboard/google/dedede/variants/kracko/ramstage.c b/src/mainboard/google/dedede/variants/kracko/ramstage.c new file mode 100644 index 0000000..0faaec1 --- /dev/null +++ b/src/mainboard/google/dedede/variants/kracko/ramstage.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> + +static struct acpi_gpio lte_reset_gpio = ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H17); +static struct acpi_gpio lte_enable_gpio = ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10); + +void variant_devtree_update(void) +{ + update_lte_device(&lte_reset_gpio, &lte_enable_gpio); +} diff --git a/src/mainboard/google/dedede/variants/metaknight/ramstage.c b/src/mainboard/google/dedede/variants/metaknight/ramstage.c index 3c8e196..0faaec1 100644 --- a/src/mainboard/google/dedede/variants/metaknight/ramstage.c +++ b/src/mainboard/google/dedede/variants/metaknight/ramstage.c @@ -1,53 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <acpi/acpi_device.h> #include <baseboard/variants.h> -#include <console/console.h> -#include <drivers/usb/acpi/chip.h> -#include <fw_config.h> -#include <gpio.h> -#include <soc/pci_devs.h> -#define LTE_USB_PORT_ID 3 -#define LTE_USB_PORT_TYPE 2 static struct acpi_gpio lte_reset_gpio = ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H17); static struct acpi_gpio lte_enable_gpio = ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10); -static void update_xhci_devtree(void) -{ - struct device *xhci, *hub = NULL, *port = NULL; - struct drivers_usb_acpi_config *config; - - xhci = pcidev_path_on_root(PCH_DEVFN_XHCI); - if (!xhci) { - printk(BIOS_ERR, "%s: Could not locate XHCI device in DT\n", __func__); - return; - } - - while ((hub = dev_bus_each_child(xhci->link_list, hub)) != NULL) { - while ((port = dev_bus_each_child(hub->link_list, port)) != NULL) { - if (!port->chip_info || port->path.usb.port_id != LTE_USB_PORT_ID) - continue; - - if (!fw_config_probe(FW_CONFIG(DB_PORTS, DB_PORTS_LTE_HDMI))) - continue; - - config = port->chip_info; - config->type = UPC_TYPE_INTERNAL; - if (port->path.usb.port_type == LTE_USB_PORT_TYPE) { - config->has_power_resource = 1; - memcpy(&config->reset_gpio, &lte_reset_gpio, - sizeof(config->reset_gpio)); - config->reset_off_delay_ms = 10; - memcpy(&config->enable_gpio, &lte_enable_gpio, - sizeof(config->enable_gpio)); - config->enable_delay_ms = 20; - } - } - } -} - void variant_devtree_update(void) { - update_xhci_devtree(); + update_lte_device(&lte_reset_gpio, &lte_enable_gpio); } -- To view, visit https://review.coreboot.org/c/coreboot/+/54671 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If12cc29ddda6d5c32c0bda840a3680e7bf932f89 Gerrit-Change-Number: 54671 Gerrit-PatchSet: 17 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Keith Tzeng <keith.tzeng(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kevin Chiu <kevin.chiu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/intel/usb4/retimer: Update code to assign correct port number
by Maulik V Vaghela (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak. Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55945 ) Change subject: drivers/intel/usb4/retimer: Update code to assign correct port number ...................................................................... Patch Set 2: (1 comment) File src/drivers/intel/usb4/retimer/chip.h: https://review.coreboot.org/c/coreboot/+/55945/comment/a49855a0_a454dd7e PS1, Line 20: uint8_t controller; > Ohk..this is good. Thank you Tim..wasn't aware we can do that. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/55945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib11637ae39046e0afdacd33bc34e8a59e6f2bfb1 Gerrit-Change-Number: 55945 Gerrit-PatchSet: 2 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Abhijeet Rao <abhijeet.rao(a)intel.corp-partner.google.com> Gerrit-CC: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 01 Jul 2021 09:40:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Update controller field for tbt_dma entries
by Maulik V Vaghela (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Furquan Shaikh. Hello build bot (Jenkins), Furquan Shaikh, John Zhao, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55946 to look at the new patch set (#2). Change subject: mb/google/brya: Update controller field for tbt_dma entries ...................................................................... mb/google/brya: Update controller field for tbt_dma entries We need to refernce correct USB port number for driver to identify type-C port number correctly. BUG=b:189476816 BRANCH=None TEST=Check the transactions are happening on correct port. Also checked retimer firmware update on both the ports. Change-Id: I20c088ee81610155067abad086eba8d72f73ad60 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/mainboard/google/brya/variants/brya0/overridetree.cb 1 file changed, 4 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/55946/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55946 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20c088ee81610155067abad086eba8d72f73ad60 Gerrit-Change-Number: 55946 Gerrit-PatchSet: 2 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Abhijeet Rao <abhijeet.rao(a)intel.corp-partner.google.com> Gerrit-CC: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/intel/usb4/retimer: Update code to assign correct port number
by Maulik V Vaghela (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak. Hello build bot (Jenkins), Furquan Shaikh, John Zhao, Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55945 to look at the new patch set (#2). Change subject: drivers/intel/usb4/retimer: Update code to assign correct port number ...................................................................... drivers/intel/usb4/retimer: Update code to assign correct port number Since TBT controller can have maximum 2 ports per controller, our code will loop over DFP structure twice and determine port number. Retimer driver used to assign port number as below: 1. Check if power GPIO is assigned for particular DFP entry or not 2. If entry is there, assign loop count as port number Since loop count is 2, retimer will never assign port number = 2 even if it's present. In case of more than 1 controller, port number assigned will still be 0 or 1 even though actual port index might be 2 or 3. This will create an issue where even if you do transaction on device on controller 2 (port index 2 or 3), EC will route it on port 0 or 1 due to incorrect port index. Updated the driver flow as per below to handle this scenario: 1. Check if power GPIO is assigned for particular DFP entry or not 2. get USB port number from config since it's stored in usb port information under devicetree 3. Pass the port number to ACPI SSDT and EC code Above changes will ensure that we're assigning correct port number as per calculation and EC will use correct port index. BUG=b:189476816 BRANCH=None TEST=Checked that retimer firmware update works on both ports and update happens on correct port index. Change-Id: Ib11637ae39046e0afdacd33bc34e8a59e6f2bfb1 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/drivers/intel/usb4/retimer/chip.h M src/drivers/intel/usb4/retimer/retimer.c 2 files changed, 16 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/55945/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib11637ae39046e0afdacd33bc34e8a59e6f2bfb1 Gerrit-Change-Number: 55945 Gerrit-PatchSet: 2 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Abhijeet Rao <abhijeet.rao(a)intel.corp-partner.google.com> Gerrit-CC: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: device/pci_device.c: Reuse `irq` variable
by Patrick Georgi (Code Review) 01 Jul '21

01 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55892 ) Change subject: device/pci_device.c: Reuse `irq` variable ...................................................................... device/pci_device.c: Reuse `irq` variable The `irq` variable has the same value as `pIntAtoD[line - 1]`. Change-Id: Iabf760adbc3014b32cfe6f908dc04c38b71bd980 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55892 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/device/pci_device.c 1 file changed, 2 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Werner Zeh: Looks good to me, approved diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 3634660..63c1dc5 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1633,11 +1633,10 @@ printk(BIOS_DEBUG, "Assigning IRQ %d to %s\n", irq, dev_path(dev)); - pci_write_config8(dev, PCI_INTERRUPT_LINE, pIntAtoD[line - 1]); + pci_write_config8(dev, PCI_INTERRUPT_LINE, irq); /* Change to level triggered. */ - i8259_configure_irq_trigger(pIntAtoD[line - 1], - IRQ_LEVEL_TRIGGERED); + i8259_configure_irq_trigger(irq, IRQ_LEVEL_TRIGGERED); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/55892 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabf760adbc3014b32cfe6f908dc04c38b71bd980 Gerrit-Change-Number: 55892 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Select VBOOT_X86_SHA256_ACCELERATION config
by Patrick Georgi (Code Review) 01 Jul '21

01 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55612 ) Change subject: soc/intel/alderlake: Select VBOOT_X86_SHA256_ACCELERATION config ...................................................................... soc/intel/alderlake: Select VBOOT_X86_SHA256_ACCELERATION config By enabling the flag alderlake platform will use hardware sha instruction instead of software implementation for sha256. This will speed up firmware verification especially on low-performance device. Change-Id: Ie8ab02360fdceafab257e9a301e6a89d3a22c3ae Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55612 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/alderlake/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 375fedc..3c49748 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -255,6 +255,7 @@ select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_VBNV_CMOS select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH + select VBOOT_X86_SHA256_ACCELERATION config CBFS_SIZE hex -- To view, visit https://review.coreboot.org/c/coreboot/+/55612 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8ab02360fdceafab257e9a301e6a89d3a22c3ae Gerrit-Change-Number: 55612 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kangheui Won <khwon(a)chromium.org> Gerrit-CC: Kangheui Won <khwon(a)google.com> Gerrit-MessageType: merged

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coreboot-gerrit July 2021