coreboot-gerrit July 2021

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Change in coreboot[master]: vboot: add VBOOT_X86_SHA256_ACCELERATION config
by Patrick Georgi (Code Review) 01 Jul '21

01 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55611 ) Change subject: vboot: add VBOOT_X86_SHA256_ACCELERATION config ...................................................................... vboot: add VBOOT_X86_SHA256_ACCELERATION config Add Kconfig option for VBOOT_X86_SHA256_ACCELERATION, which will use x86-sha extension for SHA256 instead of software implementation. TEST=Able to call vb2ex_hwcrypto_digest_init() and perform SHA using HW crypto engine. Change-Id: Idc8be8711c69f4ebc489cd37cc3749c0b257c610 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55611 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/security/vboot/Kconfig M src/security/vboot/Makefile.inc 2 files changed, 9 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index 0368758..7cbeea3 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -274,6 +274,14 @@ software sync needs to also support it. This setting tells vboot to perform EFS software sync. +config VBOOT_X86_SHA256_ACCELERATION + bool "Use sha extension for sha256 hash calculation" + default n + depends on ARCH_X86 + help + Use sha256msg1, sha256msg2, sha256rnds2 instruction to accelerate + SHA hash calculation in vboot. + menu "GBB configuration" config GBB_HWID diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index 47830f3..d604d1c 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -28,6 +28,7 @@ CC="$$(CC_$(1))" \ CFLAGS="$$(VBOOT_CFLAGS_$(1))" VBOOT2="y" \ EC_EFS="$(CONFIG_VBOOT_EC_EFS)" \ + X86_SHA_EXT="$(CONFIG_VBOOT_X86_SHA256_ACCELERATION)" \ $(MAKE) -C $(VBOOT_SOURCE) \ BUILD=$$(abspath $$(dir $$(VBOOT_LIB_$(1)))) \ V=$(V) \ -- To view, visit https://review.coreboot.org/c/coreboot/+/55611 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc8be8711c69f4ebc489cd37cc3749c0b257c610 Gerrit-Change-Number: 55611 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: Update vboot submodule to upstream main
by Patrick Georgi (Code Review) 01 Jul '21

01 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55992 ) Change subject: Update vboot submodule to upstream main ...................................................................... Update vboot submodule to upstream main Updating from commit id b38e3a63: cros_ec: Use boot mode to check if EC can be trusted to commit id ccc56f4: vboot: add x86 SHA256 ext support Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Change-Id: I4e170e84a12646386d3fd84ae97add6c19f23809 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55992 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M 3rdparty/vboot 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/3rdparty/vboot b/3rdparty/vboot index b38e3a6..ccc56f4 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit b38e3a63a8b1d42fd707e4c23e71c3f3ed84e6ad +Subproject commit ccc56f46c51fa9d0c2b3c086ace97c14fe887c32 -- To view, visit https://review.coreboot.org/c/coreboot/+/55992 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e170e84a12646386d3fd84ae97add6c19f23809 Gerrit-Change-Number: 55992 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: Update vboot submodule to upstream main
by Patrick Georgi (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Kangheui Won. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55992 ) Change subject: Update vboot submodule to upstream main ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55992 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e170e84a12646386d3fd84ae97add6c19f23809 Gerrit-Change-Number: 55992 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kangheui Won <khwon(a)google.com> Gerrit-Comment-Date: Thu, 01 Jul 2021 09:38:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Update vboot submodule to upstream main
by Subrata Banik (Code Review) 01 Jul '21

01 Jul '21

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55992 ) Change subject: Update vboot submodule to upstream main ...................................................................... Update vboot submodule to upstream main Updating from commit id b38e3a63: cros_ec: Use boot mode to check if EC can be trusted to commit id ccc56f4: vboot: add x86 SHA256 ext support Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Change-Id: I4e170e84a12646386d3fd84ae97add6c19f23809 --- M 3rdparty/vboot 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/55992/1 diff --git a/3rdparty/vboot b/3rdparty/vboot index b38e3a6..ccc56f4 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit b38e3a63a8b1d42fd707e4c23e71c3f3ed84e6ad +Subproject commit ccc56f46c51fa9d0c2b3c086ace97c14fe887c32 -- To view, visit https://review.coreboot.org/c/coreboot/+/55992 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e170e84a12646386d3fd84ae97add6c19f23809 Gerrit-Change-Number: 55992 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/adlrvp: Fix DDR5 Boot issue
by Meera Ravindranath (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Bora Guvendik, Furquan Shaikh, Selma Bensaid, Maulik V Vaghela, Meera Ravindranath, Subrata Banik. Hello Bora Guvendik, build bot (Jenkins), Furquan Shaikh, Selma Bensaid, Maulik V Vaghela, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50996 to look at the new patch set (#13). Change subject: mb/adlrvp: Fix DDR5 Boot issue ...................................................................... mb/adlrvp: Fix DDR5 Boot issue The coreboot SMBus driver requires additional changes to accomodate the DDR5 EEPROM read which has resulted in a broken code flow for boot. This CL serves as a temp WA to let FSP perform the SPD read for DDR5 and pass SPD addresses to FSP UPD array. BUG=b:180458099 TEST=Build and boot DDR5 adlrvp to OS Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Change-Id: I9998bfcd12b81c11fcc9f791da2a27d3c788e48a --- M src/mainboard/intel/adlrvp/romstage_fsp_params.c 1 file changed, 10 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/50996/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/50996 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9998bfcd12b81c11fcc9f791da2a27d3c788e48a Gerrit-Change-Number: 50996 Gerrit-PatchSet: 13 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/adlrvp: Fix DDR5 Boot issue
by build bot (Jenkins) (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Bora Guvendik, Furquan Shaikh, Selma Bensaid, Maulik V Vaghela, Subrata Banik. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50996 ) Change subject: mb/adlrvp: Fix DDR5 Boot issue ...................................................................... Patch Set 12: (2 comments) File src/mainboard/intel/adlrvp/romstage_fsp_params.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123122): https://review.coreboot.org/c/coreboot/+/50996/comment/1c068ab8_8a1ba495 PS12, Line 62: is updated with DDR5 suuport 'suuport' may be misspelled - perhaps 'support'? Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123122): https://review.coreboot.org/c/coreboot/+/50996/comment/2d0f254a_5a969dc6 PS12, Line 62: is updated with DDR5 suuport trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/50996 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9998bfcd12b81c11fcc9f791da2a27d3c788e48a Gerrit-Change-Number: 50996 Gerrit-PatchSet: 12 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Thu, 01 Jul 2021 08:25:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/adlrvp: Fix DDR5 Boot issue
by Meera Ravindranath (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Bora Guvendik, Furquan Shaikh, Selma Bensaid, Maulik V Vaghela, Subrata Banik. Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50996 ) Change subject: mb/adlrvp: Fix DDR5 Boot issue ...................................................................... Patch Set 12: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/50996/comment/7deefc67_f316e48f PS11, Line 9: DDR5 boot flow is currently broken in master coreboot. > I think it would be better to capture that there are changes required in the smbus driver to accommo […] Done File src/mainboard/intel/adlrvp/romstage_fsp_params.c: https://review.coreboot.org/c/coreboot/+/50996/comment/49765273_ea8ebab5 PS11, Line 61: for (int i = 0; i < 16; i++) > Can you please add a comment why this is being done here and a TODO to drop this once the smbus driv […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/50996 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9998bfcd12b81c11fcc9f791da2a27d3c788e48a Gerrit-Change-Number: 50996 Gerrit-PatchSet: 12 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Thu, 01 Jul 2021 07:49:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/adlrvp: Fix DDR5 Boot issue
by Meera Ravindranath (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Bora Guvendik, Selma Bensaid, Maulik V Vaghela, Subrata Banik, Meera Ravindranath. Hello Bora Guvendik, build bot (Jenkins), Furquan Shaikh, Selma Bensaid, Maulik V Vaghela, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50996 to look at the new patch set (#12). Change subject: mb/adlrvp: Fix DDR5 Boot issue ...................................................................... mb/adlrvp: Fix DDR5 Boot issue The coreboot SMBus driver requires additional changes to accomodate the DDR5 EEPROM read which has resulted in a broken code flow for boot. This CL serves as a temp WA to let FSP perform the SPD read for DDR5 and pass SPD addresses to FSP UPD array. BUG=b:180458099 TEST=Build and boot DDR5 adlrvp to OS Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Change-Id: I9998bfcd12b81c11fcc9f791da2a27d3c788e48a --- M src/mainboard/intel/adlrvp/romstage_fsp_params.c 1 file changed, 10 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/50996/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/50996 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9998bfcd12b81c11fcc9f791da2a27d3c788e48a Gerrit-Change-Number: 50996 Gerrit-PatchSet: 12 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: SMBIOS: Drop now-unnecessary unions
by Patrick Georgi (Code Review) 01 Jul '21

01 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55910 ) Change subject: SMBIOS: Drop now-unnecessary unions ...................................................................... SMBIOS: Drop now-unnecessary unions Now that the refactoring is complete, the unions for the table header are no longer needed. Therefore, drop them. Change-Id: I4e170e84a12646386d3fd84ae973dd6c18f25809 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55910 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/drivers/wifi/generic/smbios.c M src/include/smbios.h 2 files changed, 18 insertions(+), 144 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/drivers/wifi/generic/smbios.c b/src/drivers/wifi/generic/smbios.c index 7c697ad..793349d 100644 --- a/src/drivers/wifi/generic/smbios.c +++ b/src/drivers/wifi/generic/smbios.c @@ -10,14 +10,7 @@ static int smbios_write_intel_wifi(struct device *dev, int *handle, unsigned long *current) { struct smbios_type_intel_wifi { - union { - struct { - u8 type; - u8 length; - u16 handle; - }; - struct smbios_header header; - }; + struct smbios_header header; u8 str; u8 eos[2]; } __packed; diff --git a/src/include/smbios.h b/src/include/smbios.h index edc56f7..a98023b 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -287,14 +287,7 @@ } __packed; struct smbios_type0 { - union { - struct { - u8 type; - u8 length; - u16 handle; - }; - struct smbios_header header; - }; + struct smbios_header header; u8 vendor; u8 bios_version; u16 bios_start_segment; @@ -312,14 +305,7 @@ } __packed; struct smbios_type1 { - union { - struct { - u8 type; - u8 length; - u16 handle; - }; - struct smbios_header header; - }; + struct smbios_header header; u8 manufacturer; u8 product_name; u8 version; @@ -354,14 +340,7 @@ } smbios_board_type; struct smbios_type2 { - union { - struct { - u8 type; - u8 length; - u16 handle; - }; - struct smbios_header header; - }; + struct smbios_header header; u8 manufacturer; u8 product_name; u8 version; @@ -414,14 +393,7 @@ } smbios_enclosure_type; struct smbios_type3 { - union { - struct { - u8 type; - u8 length; - u16 handle; - }; - struct smbios_header header; - }; + struct smbios_header header; u8 manufacturer; u8 _type; u8 version; @@ -441,14 +413,7 @@ } __packed; struct smbios_type4 { - union { - struct { - u8 type; - u8 length; - u16 handle; - }; - struct smbios_header header; - }; + struct smbios_header header; u8 socket_designation; u8 processor_type; u8 processor_family; @@ -559,14 +524,7 @@ #define SMBIOS_CACHE_OP_MODE_UNKNOWN 3 struct smbios_type7 { - union { - struct { - u8 type; - u8 length; - u16 handle; - }; - struct smbios_header header; - }; + struct smbios_header header; u8 socket_designation; u16 cache_configuration; u16 max_cache_size; @@ -680,14 +638,7 @@ }; struct smbios_type8 { - union { - struct { - u8 type; - u8 length; - u16 handle; - }; - struct smbios_header header; - }; + struct smbios_header header; u8 internal_reference_designator; u8 internal_connector_type; u8 external_reference_designator; @@ -822,14 +773,7 @@ } __packed; struct smbios_type9 { - union { - struct { - u8 type; - u8 length; - u16 handle; - }; - struct smbios_header header; - }; + struct smbios_header header; u8 slot_designation; u8 slot_type; u8 slot_data_bus_width; @@ -848,27 +792,13 @@ } __packed; struct smbios_type11 { - union { - struct { - u8 type; - u8 length; - u16 handle; - }; - struct smbios_header header; - }; + struct smbios_header header; u8 count; u8 eos[2]; } __packed; struct smbios_type15 { - union { - struct { - u8 type; - u8 length; - u16 handle; - }; - struct smbios_header header; - }; + struct smbios_header header; u16 area_length; u16 header_offset; u16 data_offset; @@ -898,14 +828,7 @@ #define SMBIOS_USE_EXTENDED_MAX_CAPACITY (1 << 31) struct smbios_type16 { - union { - struct { - u8 type; - u8 length; - u16 handle; - }; - struct smbios_header header; - }; + struct smbios_header header; u8 location; u8 use; u8 memory_error_correction; @@ -917,14 +840,7 @@ } __packed; struct smbios_type17 { - union { - struct { - u8 type; - u8 length; - u16 handle; - }; - struct smbios_header header; - }; + struct smbios_header header; u16 phys_memory_array_handle; u16 memory_error_information_handle; u16 total_width; @@ -951,14 +867,7 @@ } __packed; struct smbios_type19 { - union { - struct { - u8 type; - u8 length; - u16 handle; - }; - struct smbios_header header; - }; + struct smbios_header header; u32 starting_address; u32 ending_address; u16 memory_array_handle; @@ -969,28 +878,14 @@ } __packed; struct smbios_type32 { - union { - struct { - u8 type; - u8 length; - u16 handle; - }; - struct smbios_header header; - }; + struct smbios_header header; u8 reserved[6]; u8 boot_status; u8 eos[2]; } __packed; struct smbios_type38 { - union { - struct { - u8 type; - u8 length; - u16 handle; - }; - struct smbios_header header; - }; + struct smbios_header header; u8 interface_type; u8 ipmi_rev; u8 i2c_slave_addr; @@ -1025,14 +920,7 @@ #define SMBIOS_DEVICE_TYPE_COUNT 10 struct smbios_type41 { - union { - struct { - u8 type; - u8 length; - u16 handle; - }; - struct smbios_header header; - }; + struct smbios_header header; u8 reference_designation; u8 device_type: 7; u8 device_status: 1; @@ -1045,14 +933,7 @@ } __packed; struct smbios_type127 { - union { - struct { - u8 type; - u8 length; - u16 handle; - }; - struct smbios_header header; - }; + struct smbios_header header; u8 eos[2]; } __packed; -- To view, visit https://review.coreboot.org/c/coreboot/+/55910 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e170e84a12646386d3fd84ae973dd6c18f25809 Gerrit-Change-Number: 55910 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/emulation/qemu-i440fx/fw_cfg.c: Use `smbios_header`
by Patrick Georgi (Code Review) 01 Jul '21

01 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55913 ) Change subject: mb/emulation/qemu-i440fx/fw_cfg.c: Use `smbios_header` ...................................................................... mb/emulation/qemu-i440fx/fw_cfg.c: Use `smbios_header` Replace uses of `smbios_type0` with `smbios_header` for correctness. Change-Id: I2479984f5322f0fb474ff1707c1dd1f5885f30e9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55913 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/emulation/qemu-i440fx/fw_cfg.c 1 file changed, 9 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c index d6caedf..01be2c3 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c @@ -393,14 +393,14 @@ static unsigned long smbios_next(unsigned long current) { - struct smbios_type0 *t0; + struct smbios_header *header; int l, count = 0; char *s; - t0 = (void*)current; - current += t0->length; + header = (void *)current; + current += header->length; for (;;) { - s = (void*)current; + s = (void *)current; l = strlen(s); if (!l) return current + (count ? 1 : 2); @@ -424,7 +424,7 @@ unsigned long fw_cfg_smbios_tables(int *handle, unsigned long *current) { FWCfgFile f; - struct smbios_type0 *t0; + struct smbios_header *header; unsigned long start, end; int ret, i, count = 1; char *str; @@ -446,8 +446,8 @@ if (i == 16384) return 0; i += sizeof(struct smbios_type0) - 2; - t0 = (struct smbios_type0*)(*current - i); - if (t0->type != SMBIOS_BIOS_INFORMATION || t0->handle != 0) + header = (struct smbios_header *)(*current - i); + if (header->type != SMBIOS_BIOS_INFORMATION || header->handle != 0) return 0; printk(BIOS_DEBUG, "QEMU: coreboot type0 table found at 0x%lx.\n", *current - i); @@ -461,8 +461,8 @@ fw_cfg_get(f.select, (void *)start, f.size); end = start; do { - t0 = (struct smbios_type0*)end; - if (t0->type == SMBIOS_END_OF_TABLE) + header = (struct smbios_header *)end; + if (header->type == SMBIOS_END_OF_TABLE) break; end = smbios_next(end); count++; -- To view, visit https://review.coreboot.org/c/coreboot/+/55913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2479984f5322f0fb474ff1707c1dd1f5885f30e9 Gerrit-Change-Number: 55913 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit July 2021