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Change subject: drivers/intel/usb4/retimer: Update code to assign correct port number
......................................................................
Patch Set 1:
(1 comment)
File src/drivers/intel/usb4/retimer/chip.h:
https://review.coreboot.org/c/coreboot/+/55945/comment/eaad25ac_d7ae56a9
PS1, Line 20: uint8_t controller;
> It looks like this is only used to calculate the USB port number. […]
Ohk..this is good. Thank you Tim..wasn't aware we can do that. :)
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Change subject: soc/intel/jsl: Control Fivr bypass mode by DisableExternalVnnVcc1p05BypassMode config
......................................................................
Patch Set 9:
(6 comments)
This change is ready for review.
Commit Message:
https://review.coreboot.org/c/coreboot/+/55744/comment/d3b204c1_c7b5f29f
PS7, Line 8:
> Please elaborate, what the problem is.
Done
Patchset:
PS9:
Hi Paul,
Sorry for the mistakes, I just push wrong changes to review. Thanks to your kindly reminding.
I just made a new change to correct them, if you have time please correct me if anything still not perfect one.
BTW, I am also changing the config name after discussed internally.
Simon
File src/soc/intel/jasperlake/chip.h:
https://review.coreboot.org/c/coreboot/+/55744/comment/2f56b517_c15d99be
PS7, Line 23: #define MAX_HD_AUDIO_SSP_LINKS 6
> Please revert this (unrelated) hunk.
Done
https://review.coreboot.org/c/coreboot/+/55744/comment/ff62e38e_1ff573ab
PS7, Line 408: do
> does
Done
File src/soc/intel/jasperlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/55744/comment/c6e6e6f7_a0358df2
PS7, Line 69: params->CpuMpPpi = (uintptr_t)mp_fill_ppi_services_data();
> Unrelated.
Done
https://review.coreboot.org/c/coreboot/+/55744/comment/d55899c8_8118f315
PS7, Line 186: config->PchPmSlpAMinAssert, config->PchPmPwrCycDur);
> Unrelated.
Done
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Change subject: selfboot: Add support for selfload in romstage
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/55865/comment/5a2a4047_6f14224d
PS4, Line 11:
> This is the error. I don't think that this needs to be in the commit message: […]
From the paste `undefined reference to `bootmem_region_targets_type'` could be added to the commit message.
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Change subject: soc/intel/common/block/cse: Add ME EOP timestamps
......................................................................
Patch Set 6: Code-Review+2
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Change subject: mb/google/brya: Add HANG_DETECT host event to EC S0ix wake mask
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/55988/comment/f6bb14de_7815fbda
PS1, Line 10: BIOS
BIOS means coreboot?
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Change subject: soc/intel/common/block/cse: Add ME EOP timestamps
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Patch Set 6: Code-Review+1
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Change subject: mb/google/hatch/scout: update gpios and device tree
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Could you please assist by submitting this change for us?
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Change subject: mb/google/dedede/var/cret: Disable SDCard controller
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Patchset:
PS1:
> Thank you for review. […]
Thanks for confirming that the GPIOs are configured as NC.
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Change subject: mb/google/dedede/var/cret: Disable SDCard controller
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Should we also configure the SD Card GPIOs as PAD_NC for Cret?
Thank you for review.
CB:51629 set GPP_H1, GPP_G0 ~ GPP_G7 to PAD_NC already,
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