coreboot-gerrit July 2021

coreboot-gerrit@coreboot.org

1 participants
5823 discussions

Change in coreboot[master]: soc/intel/skylake: Switch to runtime generation of Intel Power Engine
by Tim Wawrzynczak (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Patrick Rudolph. Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56014 ) Change subject: soc/intel/skylake: Switch to runtime generation of Intel Power Engine ...................................................................... soc/intel/skylake: Switch to runtime generation of Intel Power Engine The pep.asl file is being obsoleted by runtime generation, therefore switch skylake boards to this method. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I7c7cb424278946a9767ea329d18fb03d4e57dce8 --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/acpi/pch.asl 2 files changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/56014/1 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index d16a7c9..416de67 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -55,6 +55,7 @@ select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT + select SOC_INTEL_COMMON_BLOCK_ACPI_PEP select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl index 136e5c4..e088ca1 100644 --- a/src/soc/intel/skylake/acpi/pch.asl +++ b/src/soc/intel/skylake/acpi/pch.asl @@ -65,6 +65,3 @@ #if CONFIG(SOC_INTEL_COMMON_BLOCK_SGX) #include <soc/intel/common/acpi/sgx.asl> #endif - -/* Intel Power Engine Plug-in */ -#include <soc/intel/common/block/acpi/acpi/pep.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/56014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c7cb424278946a9767ea329d18fb03d4e57dce8 Gerrit-Change-Number: 56014 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/intel/common: Add Intel Power Engine support to discoverable PMC
by Tim Wawrzynczak (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Patrick Rudolph. Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56013 ) Change subject: soc/intel/common: Add Intel Power Engine support to discoverable PMC ...................................................................... soc/intel/common: Add Intel Power Engine support to discoverable PMC In order to get rid of pep.asl, skylake also needs to support runtime generation of the Intel Power Engine, therefore add this support to devices that have a discoverable PMC as well. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I4bf0c4a338301b335fa78617e0f2ed5a9f4360ed --- M src/soc/intel/common/block/pmc/pmc.c 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/56013/1 diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index 0ff71b9..e3cab11 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -5,6 +5,7 @@ #include <console/console.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <intelblocks/acpi.h> #include <intelblocks/pmc.h> #include <soc/pci_devs.h> @@ -73,6 +74,12 @@ pch_pmc_add_io_resources(dev, config); } +static void pmc_fill_ssdt(const struct device *dev) +{ + if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_PEP)) + generate_acpi_power_engine(dev); +} + static struct device_operations device_ops = { .read_resources = pch_pmc_read_resources, .set_resources = pci_dev_set_resources, @@ -80,6 +87,9 @@ .init = pmc_soc_init, .ops_pci = &pci_dev_ops_pci, .scan_bus = scan_static_bus, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_fill_ssdt = pmc_fill_ssdt, +#endif }; static const unsigned short pci_device_ids[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/56013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4bf0c4a338301b335fa78617e0f2ed5a9f4360ed Gerrit-Change-Number: 56013 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/intel/elkhartlake: Switch to runtime generation of Power Engine
by Tim Wawrzynczak (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Patrick Rudolph. Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56012 ) Change subject: soc/intel/elkhartlake: Switch to runtime generation of Power Engine ...................................................................... soc/intel/elkhartlake: Switch to runtime generation of Power Engine The pep.asl file is being obsoleted by runtime generation, therefore switch elkhartlake boards to this method. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I47f03b440729d4b37ae0abc84bd1d18c4e01657d --- M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/acpi/southbridge.asl M src/soc/intel/elkhartlake/pmc.c 3 files changed, 5 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/56012/1 diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index f440d33..6f494ad 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -42,6 +42,7 @@ select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT + select SOC_INTEL_COMMON_BLOCK_ACPI_PEP select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU diff --git a/src/soc/intel/elkhartlake/acpi/southbridge.asl b/src/soc/intel/elkhartlake/acpi/southbridge.asl index 059f220..2da44bc 100644 --- a/src/soc/intel/elkhartlake/acpi/southbridge.asl +++ b/src/soc/intel/elkhartlake/acpi/southbridge.asl @@ -38,9 +38,6 @@ /* PCI _OSC */ #include <soc/intel/common/acpi/pci_osc.asl> -/* Intel Power Engine Plug-in */ -#include <soc/intel/common/block/acpi/acpi/pep.asl> - /* EMMC/SD card */ #include "scs.asl" diff --git a/src/soc/intel/elkhartlake/pmc.c b/src/soc/intel/elkhartlake/pmc.c index 45a368c..49b7802 100644 --- a/src/soc/intel/elkhartlake/pmc.c +++ b/src/soc/intel/elkhartlake/pmc.c @@ -4,6 +4,7 @@ #include <console/console.h> #include <device/device.h> #include <device/mmio.h> +#include <intelblocks/acpi.h> #include <intelblocks/pmc.h> #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> @@ -98,4 +99,7 @@ .set_resources = noop_set_resources, .init = soc_acpi_mode_init, .enable = pmc_init, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_fill_ssdt = generate_acpi_power_engine, +#endif }; -- To view, visit https://review.coreboot.org/c/coreboot/+/56012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47f03b440729d4b37ae0abc84bd1d18c4e01657d Gerrit-Change-Number: 56012 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/intel/jasperlake: Switch to runtime generation of Intel Power Engine
by Tim Wawrzynczak (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Patrick Rudolph. Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56011 ) Change subject: soc/intel/jasperlake: Switch to runtime generation of Intel Power Engine ...................................................................... soc/intel/jasperlake: Switch to runtime generation of Intel Power Engine The pep.asl file is being obsoleted by runtime generation, therefore switch jasperlake boards to this method. soc/intel/jasperlake: Switch to acpigen PEPD Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Ib7f17f9b3b1396708ba68fa7a6d199d6e8b0ba11 --- M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/acpi/southbridge.asl M src/soc/intel/jasperlake/pmc.c 3 files changed, 5 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/56011/1 diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index a05cd72..0490d43 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -42,6 +42,7 @@ select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT + select SOC_INTEL_COMMON_BLOCK_ACPI_PEP select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CNVI diff --git a/src/soc/intel/jasperlake/acpi/southbridge.asl b/src/soc/intel/jasperlake/acpi/southbridge.asl index e623cc3..93e538e 100644 --- a/src/soc/intel/jasperlake/acpi/southbridge.asl +++ b/src/soc/intel/jasperlake/acpi/southbridge.asl @@ -44,9 +44,6 @@ /* PCI _OSC */ #include <soc/intel/common/acpi/pci_osc.asl> -/* Intel Power Engine Plug-in */ -#include <soc/intel/common/block/acpi/acpi/pep.asl> - /* EMMC/SD card */ #include "scs.asl" diff --git a/src/soc/intel/jasperlake/pmc.c b/src/soc/intel/jasperlake/pmc.c index dce791c..a081d64 100644 --- a/src/soc/intel/jasperlake/pmc.c +++ b/src/soc/intel/jasperlake/pmc.c @@ -4,6 +4,7 @@ #include <console/console.h> #include <device/mmio.h> #include <device/device.h> +#include <intelblocks/acpi.h> #include <intelblocks/pmc.h> #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> @@ -106,4 +107,7 @@ .set_resources = noop_set_resources, .init = soc_acpi_mode_init, .enable = pmc_init, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_fill_ssdt = generate_acpi_power_engine, +#endif }; -- To view, visit https://review.coreboot.org/c/coreboot/+/56011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7f17f9b3b1396708ba68fa7a6d199d6e8b0ba11 Gerrit-Change-Number: 56011 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/intel/cannonlake: Switch to runtime generation of Intel Power Engine
by Tim Wawrzynczak (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Patrick Rudolph. Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56010 ) Change subject: soc/intel/cannonlake: Switch to runtime generation of Intel Power Engine ...................................................................... soc/intel/cannonlake: Switch to runtime generation of Intel Power Engine The pep.asl file is being obsoleted by runtime generation, therefore switch cannonlake boards to this method. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Ic5343b0fd37eafac29a23846c8cfc3ca93d1821d --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/acpi/southbridge.asl M src/soc/intel/cannonlake/pmc.c 3 files changed, 5 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/56010/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 5fc80af..68c5933 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -81,6 +81,7 @@ select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT + select SOC_INTEL_COMMON_BLOCK_ACPI_PEP select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CNVI diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index fa75673..052847d 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -39,6 +39,3 @@ /* GbE 0:1f.6 */ #include <soc/intel/common/block/acpi/acpi/pch_glan.asl> - -/* Intel Power Engine Plug-in */ -#include <soc/intel/common/block/acpi/acpi/pep.asl> diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c index 59f4be5..a8e63e4 100644 --- a/src/soc/intel/cannonlake/pmc.c +++ b/src/soc/intel/cannonlake/pmc.c @@ -4,6 +4,7 @@ #include <console/console.h> #include <device/mmio.h> #include <device/device.h> +#include <intelblocks/acpi.h> #include <intelblocks/pmc.h> #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> @@ -124,5 +125,8 @@ .set_resources = noop_set_resources, .init = soc_acpi_mode_init, .enable = pmc_init, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_fill_ssdt = generate_acpi_power_engine, +#endif .scan_bus = scan_static_bus, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/56010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5343b0fd37eafac29a23846c8cfc3ca93d1821d Gerrit-Change-Number: 56010 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/intel/cannonlake: Switch PMC to use device callbacks
by Tim Wawrzynczak (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Patrick Rudolph. Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56009 ) Change subject: soc/intel/cannonlake: Switch PMC to use device callbacks ...................................................................... soc/intel/cannonlake: Switch PMC to use device callbacks Now that the PMC device is marked as hidden in devicetrees, the device callbacks can be used instead of BOOT_STATE_INIT_ENTRY callbacks. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: If292728ad975ba803fed6abea879f6f634470a11 --- M src/soc/intel/cannonlake/chip.c M src/soc/intel/cannonlake/include/soc/pmc.h M src/soc/intel/cannonlake/lpc.c M src/soc/intel/cannonlake/pmc.c M src/soc/intel/cannonlake/systemagent.c 5 files changed, 34 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/56009/1 diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index aa6fb1b..6c32b30 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -195,6 +195,9 @@ dev->ops = &cpu_bus_ops; else if (dev->path.type == DEVICE_PATH_GPIO) block_gpio_enable(dev); + else if (dev->path.type == DEVICE_PATH_PCI && + dev->path.pci.devfn == PCH_DEVFN_PMC) + dev->ops = &pmc_ops; } struct chip_operations soc_intel_cannonlake_ops = { diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h index 7b00398..c8120a9 100644 --- a/src/soc/intel/cannonlake/include/soc/pmc.h +++ b/src/soc/intel/cannonlake/include/soc/pmc.h @@ -3,6 +3,10 @@ #ifndef _SOC_CANNONLAKE_PMC_H_ #define _SOC_CANNONLAKE_PMC_H_ +#include <device/device.h> + +extern struct device_operations pmc_ops; + /* PCI Configuration Space (D31:F2): PMC */ #define PWRMBASE 0x10 #define ABASE 0x20 diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c index 0e63e0d..315b704 100644 --- a/src/soc/intel/cannonlake/lpc.c +++ b/src/soc/intel/cannonlake/lpc.c @@ -49,21 +49,4 @@ i8259_configure_irq_trigger(9, 1); } -/* Fill up LPC IO resource structure inside SoC directory */ -void pch_lpc_soc_fill_io_resources(struct device *dev) -{ - /* - * PMC pci device gets hidden from PCI bus due to Silicon - * policy hence bind ACPI BASE aka ABASE (offset 0x20) with - * LPC IO resources to ensure that ABASE falls under PCI reserved - * IO memory range. - * - * Note: Don't add any more resource with same offset 0x20 - * under this device space. - */ - pch_lpc_add_new_resource(dev, PCI_BASE_ADDRESS_4, - ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, IORESOURCE_IO | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED); -} - #endif diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c index d6c30a8..59f4be5 100644 --- a/src/soc/intel/cannonlake/pmc.c +++ b/src/soc/intel/cannonlake/pmc.c @@ -68,7 +68,22 @@ write32(pmcbase + DSX_CFG, reg); } -static void pmc_init(void *unused) +static void soc_pmc_read_resources(struct device *dev) +{ + struct resource *res; + + /* Add the fixed MMIO resource */ + mmio_resource(dev, 0, PCH_PWRM_BASE_ADDRESS / KiB, PCH_PWRM_BASE_SIZE / KiB); + + /* Add the fixed I/O resource */ + res = new_resource(dev, 1); + res->base = (resource_t)ACPI_BASE_ADDRESS; + res->size = (resource_t)ACPI_BASE_SIZE; + res->limit = res->base + res->size - 1; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static void pmc_init(struct device *dev) { const config_t *config = config_of_soc(); @@ -82,16 +97,7 @@ config_deep_sx(config->deep_sx_config); } -/* -* Initialize PMC controller. -* -* PMC controller gets hidden from PCI bus during FSP-Silicon init call. -* Hence PCI enumeration can't be used to initialize bus device and -* allocate resources. -*/ -BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, pmc_init, NULL); - -static void soc_acpi_mode_init(void *unused) +static void soc_acpi_mode_init(struct device *dev) { /* * PMC initialization happens earlier for this SoC because FSP-Silicon @@ -106,11 +112,17 @@ * taking different actions based on disabling of ACPI (e.g. flushing of * all EC hostevent bits). * - * P.S.: This cannot be done as part of pmc_soc_init as PMC device is - * hidden and hence the PMC driver never gets enumerated and so init is - * not called for it. + * Because the device is set as `hidden` in the devicetree, enumeration + * is skipped, but the device callbacks are still called as if it were + * found. */ pmc_set_acpi_mode(); } -BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, soc_acpi_mode_init, NULL); +struct device_operations pmc_ops = { + .read_resources = soc_pmc_read_resources, + .set_resources = noop_set_resources, + .init = soc_acpi_mode_init, + .enable = pmc_init, + .scan_bus = scan_static_bus, +}; diff --git a/src/soc/intel/cannonlake/systemagent.c b/src/soc/intel/cannonlake/systemagent.c index a79e618..0b5e8e3 100644 --- a/src/soc/intel/cannonlake/systemagent.c +++ b/src/soc/intel/cannonlake/systemagent.c @@ -27,17 +27,6 @@ { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" }, { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" }, { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" }, - /* - * PMC pci device gets hidden from PCI bus due to Silicon - * policy hence binding PMCBAR aka PWRMBASE (offset 0x10) with - * SA resources to ensure that PMCBAR falls under PCI reserved - * memory range. - * - * Note: Don't add any more resource with same offset 0x10 - * under this device space. - */ - { PCI_BASE_ADDRESS_0, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE, - "PMCBAR" }, }; sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources, -- To view, visit https://review.coreboot.org/c/coreboot/+/56009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If292728ad975ba803fed6abea879f6f634470a11 Gerrit-Change-Number: 56009 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: cannonlake mainboards: Set PMC as hidden in devicetree
by Tim Wawrzynczak (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Jeremy Soller. Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56008 ) Change subject: cannonlake mainboards: Set PMC as hidden in devicetree ...................................................................... cannonlake mainboards: Set PMC as hidden in devicetree FSP-S hides the PMC from the PCI bus when it runs, but there are still initialization steps coreboot programs for the PMC. Therefore, change all of the cannonlake mainboards to set the PMC as hidden in the devicetree, which means the device will be skipped during enumeration, but device callbacks are still issued as if the device were enabled. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Ib4a20ce9075ce7653388a5d3e281fe774bf89355 --- M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb M src/mainboard/purism/librem_cnl/variants/librem_14/devicetree.cb M src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb M src/mainboard/system76/gaze15/devicetree.cb M src/mainboard/system76/lemp9/devicetree.cb M src/mainboard/system76/oryp5/devicetree.cb M src/mainboard/system76/oryp6/devicetree.cb M src/mainboard/system76/whl-u/devicetree.cb 12 files changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/56008/1 diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 90bd260..63a46c0 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -459,7 +459,7 @@ end end # LPC/eSPI device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller + device pci 1f.2 hidden end # Power Management Controller device pci 1f.3 on end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 7d9d1e6..f533d56 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -352,7 +352,7 @@ end end # eSPI Interface device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller + device pci 1f.2 hidden end # Power Management Controller device pci 1f.3 on end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 47709d9..95b6119 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -396,7 +396,7 @@ end end # LPC/eSPI device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller + device pci 1f.2 hidden end # Power Management Controller device pci 1f.3 on end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index f035b79..98d14d9 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -425,7 +425,7 @@ end end # LPC/eSPI device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller + device pci 1f.2 hidden end # Power Management Controller device pci 1f.3 on end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb index 12b1c47..e0ea3f2 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb @@ -71,7 +71,7 @@ end end # LPC Interface device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller + device pci 1f.2 hidden end # Power Management Controller device pci 1f.3 on end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_14/devicetree.cb index 6d0eb20..0ca8493 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_14/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_14/devicetree.cb @@ -274,7 +274,7 @@ end end device pci 1f.1 off end # P2SB - device pci 1f.2 off end # Power Management Controller + device pci 1f.2 hidden end # Power Management Controller device pci 1f.3 on # Intel HDA register "PchHdaAudioLinkHda" = "1" end diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb index 836f4ac..a681299 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb @@ -231,7 +231,7 @@ device pci 1e.3 off end # GSPI #1 device pci 1f.0 on end # LPC Bridge device pci 1f.1 off end # P2SB - device pci 1f.2 off end # Power Management Controller + device pci 1f.2 hidden end # Power Management Controller device pci 1f.3 on # Intel HDA register "PchHdaAudioLinkHda" = "1" end diff --git a/src/mainboard/system76/gaze15/devicetree.cb b/src/mainboard/system76/gaze15/devicetree.cb index 5165f61..fef0e03 100644 --- a/src/mainboard/system76/gaze15/devicetree.cb +++ b/src/mainboard/system76/gaze15/devicetree.cb @@ -202,7 +202,7 @@ end end device pci 1f.1 off end # P2SB - device pci 1f.2 off end # Power Management Controller + device pci 1f.2 hidden end # Power Management Controller device pci 1f.3 on # Intel HDA register "PchHdaAudioLinkHda" = "1" register "PchHdaAudioLinkDmic0" = "1" diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb index 80f0ef4..97df26b 100644 --- a/src/mainboard/system76/lemp9/devicetree.cb +++ b/src/mainboard/system76/lemp9/devicetree.cb @@ -189,7 +189,7 @@ end end device pci 1f.1 off end # P2SB - device pci 1f.2 off end # Power Management Controller + device pci 1f.2 hidden end # Power Management Controller device pci 1f.3 on # Intel HDA register "PchHdaAudioLinkHda" = "1" end diff --git a/src/mainboard/system76/oryp5/devicetree.cb b/src/mainboard/system76/oryp5/devicetree.cb index e8463ca..d26a46d 100644 --- a/src/mainboard/system76/oryp5/devicetree.cb +++ b/src/mainboard/system76/oryp5/devicetree.cb @@ -190,7 +190,7 @@ end end device pci 1f.1 off end # P2SB - device pci 1f.2 off end # Power Management Controller + device pci 1f.2 hidden end # Power Management Controller device pci 1f.3 on # Intel HDA subsystemid 0x1558 0x96e1 register "PchHdaAudioLinkHda" = "1" diff --git a/src/mainboard/system76/oryp6/devicetree.cb b/src/mainboard/system76/oryp6/devicetree.cb index a23362e..16d83e6 100644 --- a/src/mainboard/system76/oryp6/devicetree.cb +++ b/src/mainboard/system76/oryp6/devicetree.cb @@ -205,7 +205,7 @@ end end device pci 1f.1 off end # P2SB - device pci 1f.2 off end # Power Management Controller + device pci 1f.2 hidden end # Power Management Controller device pci 1f.3 on # Intel HDA register "PchHdaAudioLinkHda" = "1" end diff --git a/src/mainboard/system76/whl-u/devicetree.cb b/src/mainboard/system76/whl-u/devicetree.cb index ade42a4..8844bd8 100644 --- a/src/mainboard/system76/whl-u/devicetree.cb +++ b/src/mainboard/system76/whl-u/devicetree.cb @@ -167,7 +167,7 @@ end end device pci 1f.1 off end # P2SB - device pci 1f.2 off end # Power Management Controller + device pci 1f.2 hidden end # Power Management Controller device pci 1f.3 on # Intel HDA register "PchHdaAudioLinkHda" = "1" register "PchHdaAudioLinkDmic0" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/56008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4a20ce9075ce7653388a5d3e281fe774bf89355 Gerrit-Change-Number: 56008 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/intel/tigerlake: Switch to runtime generation of Intel Power Engine
by Tim Wawrzynczak (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Patrick Rudolph. Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56007 ) Change subject: soc/intel/tigerlake: Switch to runtime generation of Intel Power Engine ...................................................................... soc/intel/tigerlake: Switch to runtime generation of Intel Power Engine The pep.asl file is being obsoleted by runtime generation, therefore switch tigerlake boards to this method. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I8e97c589273e934e89d69d8829680b9cac1ff9f5 --- M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/acpi/southbridge.asl M src/soc/intel/tigerlake/pmc.c 3 files changed, 5 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/56007/1 diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index e41d7a7..520b7f2 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -47,6 +47,8 @@ select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT + select SOC_INTEL_COMMON_BLOCK_ACPI_PEP + select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CNVI diff --git a/src/soc/intel/tigerlake/acpi/southbridge.asl b/src/soc/intel/tigerlake/acpi/southbridge.asl index 59bcf74..8300c23 100644 --- a/src/soc/intel/tigerlake/acpi/southbridge.asl +++ b/src/soc/intel/tigerlake/acpi/southbridge.asl @@ -38,8 +38,5 @@ /* PCI _OSC */ #include <soc/intel/common/acpi/pci_osc.asl> -/* Intel Power Engine Plug-in */ -#include <soc/intel/common/block/acpi/acpi/pep.asl> - /* GbE 0:1f.6 */ #include <soc/intel/common/block/acpi/acpi/pch_glan.asl> diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c index dd2b61b..10ba110 100644 --- a/src/soc/intel/tigerlake/pmc.c +++ b/src/soc/intel/tigerlake/pmc.c @@ -11,6 +11,7 @@ #include <device/mmio.h> #include <device/device.h> #include <drivers/intel/pmc_mux/chip.h> +#include <intelblocks/acpi.h> #include <intelblocks/pmc.h> #include <intelblocks/pmclib.h> #include <intelblocks/pmc_ipc.h> @@ -121,6 +122,8 @@ acpigen_pop_len(); /* PMC Device */ acpigen_pop_len(); /* Scope */ + generate_acpi_power_engine(); + printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), dev->chip_ops->name, dev_path(dev)); } -- To view, visit https://review.coreboot.org/c/coreboot/+/56007 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e97c589273e934e89d69d8829680b9cac1ff9f5 Gerrit-Change-Number: 56007 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/intel/alderlake: Switch to runtime generation of Intel Power Engine
by Tim Wawrzynczak (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Patrick Rudolph. Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56006 ) Change subject: soc/intel/alderlake: Switch to runtime generation of Intel Power Engine ...................................................................... soc/intel/alderlake: Switch to runtime generation of Intel Power Engine The pep.asl file is being obsoleted by runtime generation, therefore switch alderlake boards to this method. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I617bc3d1c3cf4ac6b6cbbd790dcf62e731024834 --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/acpi/southbridge.asl M src/soc/intel/alderlake/pmc.c 3 files changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/56006/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 3c49748..089daf9 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -50,6 +50,8 @@ select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO + select SOC_INTEL_COMMON_BLOCK_ACPI_PEP + select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU diff --git a/src/soc/intel/alderlake/acpi/southbridge.asl b/src/soc/intel/alderlake/acpi/southbridge.asl index 59bcf74..8300c23 100644 --- a/src/soc/intel/alderlake/acpi/southbridge.asl +++ b/src/soc/intel/alderlake/acpi/southbridge.asl @@ -38,8 +38,5 @@ /* PCI _OSC */ #include <soc/intel/common/acpi/pci_osc.asl> -/* Intel Power Engine Plug-in */ -#include <soc/intel/common/block/acpi/acpi/pep.asl> - /* GbE 0:1f.6 */ #include <soc/intel/common/block/acpi/acpi/pch_glan.asl> diff --git a/src/soc/intel/alderlake/pmc.c b/src/soc/intel/alderlake/pmc.c index dd88b1d..df75396 100644 --- a/src/soc/intel/alderlake/pmc.c +++ b/src/soc/intel/alderlake/pmc.c @@ -11,6 +11,7 @@ #include <device/mmio.h> #include <device/device.h> #include <drivers/intel/pmc_mux/chip.h> +#include <intelblocks/acpi.h> #include <intelblocks/pmc.h> #include <intelblocks/pmc_ipc.h> #include <intelblocks/pmclib.h> @@ -122,6 +123,9 @@ acpigen_pop_len(); /* PMC Device */ acpigen_pop_len(); /* Scope */ + /* Add Intel Power Engine device */ + generate_acpi_power_engine(dev); + printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), dev->chip_ops->name, dev_path(dev)); } -- To view, visit https://review.coreboot.org/c/coreboot/+/56006 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I617bc3d1c3cf4ac6b6cbbd790dcf62e731024834 Gerrit-Change-Number: 56006 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/intel/common/block/acpi: Add LPM requirements support to PEPD _DSM
by Tim Wawrzynczak (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Patrick Rudolph. Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56005 ) Change subject: soc/intel/common/block/acpi: Add LPM requirements support to PEPD _DSM ...................................................................... soc/intel/common/block/acpi: Add LPM requirements support to PEPD _DSM This patch adds support for the S0ix UUID in the Intel Power Engine _DSM method. This allows the ACPI tables to expose device/IP power states requirements for different system low power states BUG=b:185437326 TEST=cat /sys/kernel/debug/pmc_core/substate_requirements Element | S0i2.0 | S0i3.0 | Status | USB2PLL_OFF_STS | Required | Required | Yes | PCIe/USB3.1_Gen2PLL_OFF_STS | Required | Required | | PCIe_Gen3PLL_OFF_STS | Required | Required | Yes | OPIOPLL_OFF_STS | Required | Required | | OCPLL_OFF_STS | Required | Required | Yes | MainPLL_OFF_STS | | Required | | MIPIPLL_OFF_STS | Required | Required | Yes | Fast_XTAL_Osc_OFF_STS | | Required | | AC_Ring_Osc_OFF_STS | Required | Required | Yes | SATAPLL_OFF_STS | Required | Required | Yes | XTAL_USB2PLL_OFF_STS | | Required | Yes | CSME_PG_STS | Required | Required | Yes | SATA_PG_STS | Required | Required | Yes | xHCI_PG_STS | Required | Required | | UFSX2_PG_STS | Required | Required | Yes | OTG_PG_STS | Required | Required | Yes | SPA_PG_STS | Required | Required | Yes | SPB_PG_STS | Required | Required | Yes | SPC_PG_STS | Required | Required | Yes | THC0_PG_STS | Required | Required | Yes | THC1_PG_STS | Required | Required | Yes | GBETSN_PG_STS | Required | Required | Yes | GBE_PG_STS | Required | Required | Yes | LPSS_PG_STS | Required | Required | | ADSP_D3_STS | | Required | Yes | xHCI0_D3_STS | Required | Required | | xDCI1_D3_STS | Required | Required | Yes | IS_D3_STS | Required | Required | | GBE_TSN_D3_STS | Required | Required | Yes | CPU_C10_REQ_STS_0 | Required | Required | Yes | CNVI_REQ_STS_6 | | Required | | ISH_REQ_STS_7 | | Required | Yes | MPHY_Core_DL_REQ_STS_16 | Required | Required | | Break-even_En_REQ_STS_17 | Required | Required | Yes | Auto-demo_En_REQ_STS_18 | Required | Required | Yes | Int_Timer_SS_Wake0_Pol_STS | Required | Required | | Int_Timer_SS_Wake1_Pol_STS | Required | Required | | Int_Timer_SS_Wake2_Pol_STS | Required | Required | | Int_Timer_SS_Wake3_Pol_STS | Required | Required | | Int_Timer_SS_Wake4_Pol_STS | Required | Required | | Int_Timer_SS_Wake5_Pol_STS | Required | Required | | Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I542290bd5490aa6580a5ae2b266da3d78bc17e6b --- M src/soc/intel/common/block/acpi/Kconfig M src/soc/intel/common/block/acpi/pep.c M src/soc/intel/common/block/include/intelblocks/pmc_ipc.h 3 files changed, 75 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/56005/1 diff --git a/src/soc/intel/common/block/acpi/Kconfig b/src/soc/intel/common/block/acpi/Kconfig index 12c0d45..8d6ede2 100644 --- a/src/soc/intel/common/block/acpi/Kconfig +++ b/src/soc/intel/common/block/acpi/Kconfig @@ -21,6 +21,15 @@ Generate an Intel Power Engine device object in the SSDT. This is usually used for providing ACPI hooks for S0ix exit/entry. +config SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ + bool + depends on SOC_INTEL_COMMON_BLOCK_ACPI_PEP + help + Generate a 2nd set of _DSM functions for the Power Engine device that + will return a buffer that contains the contents of the PMC's LPM + requirements registers. A kernel can use this to display the + requirements for different LPM substates. + config SOC_INTEL_COMMON_BLOCK_CRASHLOG bool depends on SOC_INTEL_CRASHLOG diff --git a/src/soc/intel/common/block/acpi/pep.c b/src/soc/intel/common/block/acpi/pep.c index 9723d28..1dcbb0a 100644 --- a/src/soc/intel/common/block/acpi/pep.c +++ b/src/soc/intel/common/block/acpi/pep.c @@ -3,17 +3,24 @@ #include <acpi/acpigen.h> #include <console/console.h> #include <intelblocks/acpi.h> +#include <intelblocks/pmc_ipc.h> #include <soc/pci_devs.h> #include <stdlib.h> #include <types.h> #define LPI_S0_HELPER_UUID "c4eb40a0-6cd2-11e2-bcfd-0800200c9a66" +#define PEP_S0IX_UUID "57a6512e-3979-4e9d-9708-ff13b2508972" #define SYSTEM_POWER_MANAGEMENT_HID "INT33A1" #define SYSTEM_POWER_MANAGEMENT_CID "PNP0D80" #define EC_S0IX_HOOK "\\_SB.PCI0.LPCB.EC0.S0IX" #define MAINBOARD_HOOK "\\_SB.MS0X" #define ENABLE_PM_BITS_HOOK "\\_SB.PCI0.EGPM" #define RESTORE_PM_BITS_HOOK "\\_SB.PCI0.RGPM" +#define LPM_STATES 8 +#define LPM_REQ_PER_STATE 6 +#define LPM_REGISTERS_COUNT (LPM_STATES * LPM_REQ_PER_STATE) +#define PMC_LPM_REQ_BASE 0x1000 +#define LPM_REQ_REG_STRIDE 48 /* * Supported functions bitmask @@ -105,10 +112,65 @@ lpi_s0ix_exit, /* s0ix exit */ }; +/* + * Supported functions bitmask + * bit 0: other functions than 0 are supported + * bits 1-6: function x supported + */ +static void pep_s0ix_enum_functions(void *unused) +{ + if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ)) + acpigen_write_return_singleton_buffer(0x03); + else + acpigen_write_return_singleton_buffer(0x00); +} + +static void pep_s0ix_collect_lpm_requirements(void *unused) +{ + if (!CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ)) + return; + + uint32_t *reg = calloc(LPM_REGISTERS_COUNT, sizeof(uint32_t)); + enum cb_err result = CB_SUCCESS; + uint32_t *ptr = reg; + + /* Read the various LPM state requirement registers from the PMC */ + for (size_t i = 0; i < LPM_STATES && result == CB_SUCCESS; i++) { + for (size_t j = 0; j < LPM_REQ_PER_STATE; j++) { + const uint32_t offset = PMC_LPM_REQ_BASE + i * LPM_REQ_REG_STRIDE + + j * sizeof(uint32_t); + const uint32_t cmd_reg = pmc_make_ipc_cmd(PMC_IPC_CMD_GENERAL_COMM, + PMC_IPC_SUBCMD_GEN_COMM_READ, + 0); + struct pmc_ipc_buffer req = {.buf[0] = offset}; + struct pmc_ipc_buffer res = {}; + + result = pmc_send_ipc_cmd(cmd_reg, &req, &res); + if (result != CB_SUCCESS) + break; + + *ptr++ = res.buf[0]; + } + } + + if (result == CB_SUCCESS) + acpigen_write_return_byte_buffer((uint8_t *)reg, LPM_REGISTERS_COUNT * sizeof(uint32_t)); + else + printk(BIOS_ERR, "ERROR: Failed to retrieve PMC LPM requirements registers\n"); + + free(reg); +} + +static void (*pep_s0ix[])(void *) = { + pep_s0ix_enum_functions, /* enumerate functions */ + pep_s0ix_collect_lpm_requirements, /* Return LPM requirements */ +}; + void generate_acpi_power_engine(const struct device *dev) { struct dsm_uuid ids[] = { DSM_UUID(LPI_S0_HELPER_UUID, lpi_s0_helpers, ARRAY_SIZE(lpi_s0_helpers), NULL), + DSM_UUID(PEP_S0IX_UUID, pep_s0ix, ARRAY_SIZE(pep_s0ix), NULL), }; const char *scope = acpi_device_scope(dev); diff --git a/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h b/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h index b67abc0..de21027 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h +++ b/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h @@ -21,6 +21,10 @@ #define PMC_IPC_CMD_NO_MSI 0 +/* IPC command for general communication */ +#define PMC_IPC_CMD_GENERAL_COMM 0xA0 +#define PMC_IPC_SUBCMD_GEN_COMM_READ 0x02 + /* IPC command to enable/disable PCIe SRCCLK */ #define PMC_IPC_CMD_ID_SET_PCIE_CLOCK 0xAC -- To view, visit https://review.coreboot.org/c/coreboot/+/56005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I542290bd5490aa6580a5ae2b266da3d78bc17e6b Gerrit-Change-Number: 56005 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit July 2021