coreboot-gerrit July 2021

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Change in coreboot[master]: arch/x86: Save resume vector to stack in x86_64 mode
by Patrick Rudolph (Code Review) 02 Jul '21

02 Jul '21

Attention is currently required from: Arthur Heymans, Iru Cai, Iru Cai (vimacs). Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55947 ) Change subject: arch/x86: Save resume vector to stack in x86_64 mode ...................................................................... Patch Set 2: (1 comment) File src/arch/x86/wakeup.S: https://review.coreboot.org/c/coreboot/+/55947/comment/96150844_550b423a PS2, Line 23: mov > Explicitly use movl to make sure only 4 bytes get moved? In Long Mode the default data size is still 32bits and edi is a 32bit operant, so it likely does the right thing already. -- To view, visit https://review.coreboot.org/c/coreboot/+/55947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45f2678071b2511c0af5dce9d9b73ac70dfd7252 Gerrit-Change-Number: 55947 Gerrit-PatchSet: 2 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Attention: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Comment-Date: Fri, 02 Jul 2021 05:04:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/sasukette: Configure I2C times for touchpad
by Tao Xia (Code Review) 02 Jul '21

02 Jul '21

Tao Xia has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56016 ) Change subject: mb/google/dedede/var/sasukette: Configure I2C times for touchpad ...................................................................... mb/google/dedede/var/sasukette: Configure I2C times for touchpad Configure I2C high / low time in the device tree to ensure I2C CLK runs accurately between 380 kHz and 400 kHz. Measured I2C frequency just as below after tuning: touchpad:390.4 kHz BUG=b:192601250 BRANCH=dedede TEST=Build and check after tuning I2C clock is between 380 kHz and 400 kHz Signed-off-by: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Change-Id: Ibe1603a48a3e841b6a50aa0c703697ec615b2854 --- M src/mainboard/google/dedede/variants/sasukette/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/56016/1 diff --git a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb index a39b9d1..776ba8a 100644 --- a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb +++ b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb @@ -23,8 +23,8 @@ .speed = I2C_SPEED_FAST, .speed_config[0] = { .speed = I2C_SPEED_FAST, - .scl_lcnt = 185, - .scl_hcnt = 95, + .scl_lcnt = 180, + .scl_hcnt = 90, .sda_hold = 40, } }, -- To view, visit https://review.coreboot.org/c/coreboot/+/56016 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe1603a48a3e841b6a50aa0c703697ec615b2854 Gerrit-Change-Number: 56016 Gerrit-PatchSet: 1 Gerrit-Owner: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: acpi: Add function to simplify If (CondRefOf (..)) sequences
by Lance Zhao (Code Review) 02 Jul '21

02 Jul '21

Attention is currently required from: Cliff Huang, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Michael Niewöhner, Karthik Ramasubramanian. Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56003 ) Change subject: acpi: Add function to simplify If (CondRefOf (..)) sequences ...................................................................... Patch Set 1: (1 comment) File src/acpi/acpigen.c: https://review.coreboot.org/c/coreboot/+/56003/comment/65842d7c_a9eb1ad9 PS1, Line 2255: acpigen_emit_byte(ZERO_OP); /* ignore COND_REFOF_OP destination */ What's the output of asl and is that needed? -- To view, visit https://review.coreboot.org/c/coreboot/+/56003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e192a569f550ecb77ad264275d52f219eacaca1 Gerrit-Change-Number: 56003 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 02 Jul 2021 03:38:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: selfboot: Add support for selfload in romstage
by Julius Werner (Code Review) 02 Jul '21

02 Jul '21

Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55865 ) Change subject: selfboot: Add support for selfload in romstage ...................................................................... selfboot: Add support for selfload in romstage Since bootmem is not available in romstage, calls to bootmem APIs need to be compile-time eliminated in order to avoid linker error: undefined reference to `bootmem_region_targets_type BUG=None BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_HEROBRINE -x -a -B cherry-picked on top of CB:49392 and verified successful compilation. Change-Id: I8dfa2f2079a9a2859114c53c22bf7ef466ac2ad9 Signed-off-by: Shelley Chen <shchen(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55865 Reviewed-by: Julius Werner <jwerner(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/lib/selfboot.c 1 file changed, 8 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index 641631a..f1c0b97 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -34,6 +34,14 @@ static int segment_targets_type(void *dest, unsigned long memsz, enum bootmem_type dest_type) { + /* No bootmem to check in earlier stages, caller should not use + selfload_check(). */ + if (!ENV_RAMSTAGE) { + printk(BIOS_ERR, + "Callers not supposed to call selfload_check() in romstage"); + return 0; + } + uintptr_t d = (uintptr_t) dest; if (bootmem_region_targets_type(d, memsz, dest_type)) return 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/55865 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8dfa2f2079a9a2859114c53c22bf7ef466ac2ad9 Gerrit-Change-Number: 55865 Gerrit-PatchSet: 7 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: lib/cbfs,commonlib/mem_pool: Make cbfs_free take const pointer
by Furquan Shaikh (Code Review) 02 Jul '21

02 Jul '21

Attention is currently required from: Raul Rangel. Furquan Shaikh has removed a vote from this change. ( https://review.coreboot.org/c/coreboot/+/56002 ) Change subject: lib/cbfs,commonlib/mem_pool: Make cbfs_free take const pointer ...................................................................... Removed Code-Review+2 by Furquan Shaikh <furquan(a)google.com> -- To view, visit https://review.coreboot.org/c/coreboot/+/56002 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie570825f9255d6499e977f6eace58589115e2552 Gerrit-Change-Number: 56002 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: deleteVote

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Change in coreboot[master]: lib/cbfs,commonlib/mem_pool: Make cbfs_free take const pointer
by Julius Werner (Code Review) 02 Jul '21

02 Jul '21

Attention is currently required from: Raul Rangel. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56002 ) Change subject: lib/cbfs,commonlib/mem_pool: Make cbfs_free take const pointer ...................................................................... Patch Set 1: Code-Review-1 (1 comment) Patchset: PS1: While pretty harmless, I'm not sure this is the right thing to do from a design purity point of view. free() in the C standard library doesn't take a const pointer either, after all. Conceptually const means "you may not modify the data pointed to by this pointer", or in other words "I can pass this const pointer around to whatever function I want and I don't need to care what exactly they do with it, I can trust that afterwards I can still use the data in there and it didn't change". free() is explicitly _not_ doing that -- what free() does is make it illegal to ever access the pointed-to data again afterwards. So while it may technically not write to the pointer in our allocator implementation, I would say that conceptually free() is much more similar to a write operation than a read operation, and allowing it on const pointers would undermine that "guarantee" that const is supposed to provide. Is there any really good technical reason why you need to have this (as opposed to just rewriting calling functions to make the variables passed to this non-const)? -- To view, visit https://review.coreboot.org/c/coreboot/+/56002 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie570825f9255d6499e977f6eace58589115e2552 Gerrit-Change-Number: 56002 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Fri, 02 Jul 2021 00:30:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] intelp2m/parser: Add support for double config string
by Jonathan Zhang (Code Review) 02 Jul '21

02 Jul '21

Attention is currently required from: Maxim Polyakov, Johnny Lin, Tim Chu. Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55984 ) Change subject: [WIP] intelp2m/parser: Add support for double config string ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/55984 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic064b9c570b59e97e00f8e1c446d72da5d6f50c2 Gerrit-Change-Number: 55984 Gerrit-PatchSet: 2 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 01 Jul 2021 22:19:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Switch PMC to use device callbacks
by build bot (Jenkins) (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56009 ) Change subject: soc/intel/cannonlake: Switch PMC to use device callbacks ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/cannonlake/chip.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123175): https://review.coreboot.org/c/coreboot/+/56009/comment/861c32b1_61e23ecf PS2, Line 198: else if (dev->path.type == DEVICE_PATH_PCI && suspect code indent for conditional statements (8, 10) -- To view, visit https://review.coreboot.org/c/coreboot/+/56009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If292728ad975ba803fed6abea879f6f634470a11 Gerrit-Change-Number: 56009 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 01 Jul 2021 19:52:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/../car: Calculate SF Mask#1 based on MSR 0xc87
by Tim Wawrzynczak (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Furquan Shaikh, Subrata Banik, Nick Vaccaro, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51374 ) Change subject: soc/intel/common/../car: Calculate SF Mask#1 based on MSR 0xc87 ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/common/block/cpu/car/cache_as_ram.S: https://review.coreboot.org/c/coreboot/+/51374/comment/f290d5db_0b1d324b PS5, Line 524: (1 << data_ways) > i guess better we accommodate this 1 << data_ways in below code as well? If that is how the register should be programmed, then yeah I guess so 😊 Looking again, shouldn't the logic actually be: `(1 << (SFWayCnt - data_ways)) - 1` which would also simplify the flow; it should only add 1 (maybe 2) instructions, a load and a subtraction -- To view, visit https://review.coreboot.org/c/coreboot/+/51374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd0b7e1a90cad4a4837adf6067fe8301dcd0a941 Gerrit-Change-Number: 51374 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Thu, 01 Jul 2021 19:40:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Switch to runtime generation of Intel Power Engine
by Tim Wawrzynczak (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Hello build bot (Jenkins), Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56007 to look at the new patch set (#2). Change subject: soc/intel/tigerlake: Switch to runtime generation of Intel Power Engine ...................................................................... soc/intel/tigerlake: Switch to runtime generation of Intel Power Engine The pep.asl file is being obsoleted by runtime generation, therefore switch tigerlake boards to this method. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I8e97c589273e934e89d69d8829680b9cac1ff9f5 --- M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/acpi/southbridge.asl M src/soc/intel/tigerlake/pmc.c 3 files changed, 5 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/56007/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56007 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e97c589273e934e89d69d8829680b9cac1ff9f5 Gerrit-Change-Number: 56007 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit July 2021