coreboot-gerrit July 2021

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Change in coreboot[master]: drivers/usb/acpi: Create function to get PLD information
by Maulik V Vaghela (Code Review) 02 Jul '21

02 Jul '21

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56024 ) Change subject: drivers/usb/acpi: Create function to get PLD information ...................................................................... drivers/usb/acpi: Create function to get PLD information Create a separate function to get PLD information from USB device. This is helpful in retimer driver where we can attach same USB port information to retimer instance and we can avoid duplication of information. BUG=None BRANCH=None TEST=Check if code compiles and function returns correct value Change-Id: Iaaf140ce1965dce3a812aa2701ce0e29b34ab3e7 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/drivers/usb/acpi/chip.h M src/drivers/usb/acpi/usb_acpi.c 2 files changed, 27 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/56024/1 diff --git a/src/drivers/usb/acpi/chip.h b/src/drivers/usb/acpi/chip.h index 73c69cc..9e9772b 100644 --- a/src/drivers/usb/acpi/chip.h +++ b/src/drivers/usb/acpi/chip.h @@ -68,4 +68,7 @@ struct acpi_gpio privacy_gpio; }; +/* Method to get PLD structure from USB device */ +const struct acpi_pld *usb_acpi_get_pld(const struct device *usb_device); + #endif /* __USB_ACPI_CHIP_H__ */ diff --git a/src/drivers/usb/acpi/usb_acpi.c b/src/drivers/usb/acpi/usb_acpi.c index 9d68d0a..da91328 100644 --- a/src/drivers/usb/acpi/usb_acpi.c +++ b/src/drivers/usb/acpi/usb_acpi.c @@ -37,6 +37,7 @@ { struct drivers_usb_acpi_config *config = dev->chip_info; const char *path = acpi_device_path(dev); + const struct acpi_pld *pld = usb_acpi_get_pld(dev); if (!path || !config) return; @@ -50,15 +51,10 @@ acpigen_write_name_string("_DDN", config->desc); acpigen_write_upc(config->type); - if (config->use_custom_pld) { - /* Use board defined PLD */ - acpigen_write_pld(&config->custom_pld); - } else { - /* Fill PLD strucutre based on port type */ - struct acpi_pld pld; - acpi_pld_fill_usb(&pld, config->type, &config->group); - acpigen_write_pld(&pld); - } + if (pld) + acpigen_write_pld(pld); + else + printk(BIOS_ERR, "Error retrieving PLD for %s \n", path); /* Resources */ if (usb_acpi_add_gpios_to_crs(config) == true) { @@ -126,3 +122,22 @@ CHIP_NAME("USB ACPI Device") .enable_dev = usb_acpi_enable }; + +const struct acpi_pld *usb_acpi_get_pld(const struct device *usb_device) +{ + struct drivers_usb_acpi_config *config = usb_device->chip_info; + static struct acpi_pld pld; + + if (!usb_device || !usb_device->chip_info || usb_device->chip_ops != &drivers_usb_acpi_ops) + return NULL; + + if (config->use_custom_pld) { + /* Use board defined PLD */ + memcpy(&pld, &config->custom_pld, sizeof(pld)); + } else { + /* Fill PLD strucutre based on port type */ + acpi_pld_fill_usb(&pld, config->type, &config->group); + } + + return &pld; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/56024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaaf140ce1965dce3a812aa2701ce0e29b34ab3e7 Gerrit-Change-Number: 56024 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/usb4/retimer: Update code to assign correct port number
by Maulik V Vaghela (Code Review) 02 Jul '21

02 Jul '21

Attention is currently required from: Maulik V Vaghela, Paul Menzel. Hello build bot (Jenkins), Furquan Shaikh, John Zhao, Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55945 to look at the new patch set (#4). Change subject: drivers/intel/usb4/retimer: Update code to assign correct port number ...................................................................... drivers/intel/usb4/retimer: Update code to assign correct port number Since TBT controller can have maximum 2 ports per controller, our code will loop over DFP structure twice and determine port number. Retimer driver used to assign port number as below: 1. Check if power GPIO is assigned for particular DFP entry or not 2. If entry is there, assign loop count as port number Since loop count is 2, retimer will never assign port number = 2 even if it's present. In case of more than 1 controller, port number assigned will still be 0 or 1 even though actual port index might be 2 or 3. This will create an issue where even if you do transaction on device on controller 2 (port index 2 or 3), EC will route it on port 0 or 1 due to incorrect port index. Update the driver flow as per below to handle this scenario: 1. Check if power GPIO is assigned for particular DFP entry or not 2. Get USB port number from config since it's stored in usb port information under devicetree 3. Pass the port number to ACPI SSDT and EC code Above changes will ensure that we're assigning correct port number as per calculation and EC will use correct port index. BUG=b:189476816 BRANCH=None TEST=Checked that retimer firmware update works on both ports and update happens on correct port index. Change-Id: Ib11637ae39046e0afdacd33bc34e8a59e6f2bfb1 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/drivers/intel/usb4/retimer/chip.h M src/drivers/intel/usb4/retimer/retimer.c 2 files changed, 27 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/55945/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/55945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib11637ae39046e0afdacd33bc34e8a59e6f2bfb1 Gerrit-Change-Number: 55945 Gerrit-PatchSet: 4 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Abhijeet Rao <abhijeet.rao(a)intel.corp-partner.google.com> Gerrit-CC: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: nb/intel/x4x: Prepare for x86_64 support
by build bot (Jenkins) (Code Review) 02 Jul '21

02 Jul '21

Attention is currently required from: Damien Zammit, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56019 ) Change subject: nb/intel/x4x: Prepare for x86_64 support ...................................................................... Patch Set 1: (1 comment) File src/northbridge/intel/x4x/raminit_ddr23.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123186): https://review.coreboot.org/c/coreboot/+/56019/comment/7e0b3a95_74bbe7f0 PS1, Line 2093: read32((u32 *)(uintptr_t)(test_address(ch, r) | 0x800000 | (bank << 12))); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/56019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id44eeb7660d0b521a326a5b981c04c16cf0a6f84 Gerrit-Change-Number: 56019 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Damien Zammit Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 02 Jul 2021 08:26:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/x4x: Expose x86_64 support
by Angel Pons (Code Review) 02 Jul '21

02 Jul '21

Attention is currently required from: Damien Zammit, Arthur Heymans, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56022 ) Change subject: nb/intel/x4x: Expose x86_64 support ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: Needs to be rebased atop https://review.coreboot.org/q/topic:%22x86_64-kconfig%22 -- To view, visit https://review.coreboot.org/c/coreboot/+/56022 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d5d5dfbd76a84aa400e44b4bc2ac4f3b5b6f739 Gerrit-Change-Number: 56022 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Damien Zammit Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 02 Jul 2021 08:24:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/x4x: Prepare for x86_64 support
by Arthur Heymans (Code Review) 02 Jul '21

02 Jul '21

Attention is currently required from: Damien Zammit, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56019 ) Change subject: nb/intel/x4x: Prepare for x86_64 support ...................................................................... Patch Set 1: (1 comment) File src/northbridge/intel/x4x/dq_dqs.c: https://review.coreboot.org/c/coreboot/+/56019/comment/6d03b34c_357d1840 PS1, Line 173: write32 > You could use write32p (note the trailing `p`) but it probably won't be reproducible. Can be done in a follow-up. Sounds good. Let me do that instead. I can test now so that's not an issue. -- To view, visit https://review.coreboot.org/c/coreboot/+/56019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id44eeb7660d0b521a326a5b981c04c16cf0a6f84 Gerrit-Change-Number: 56019 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Damien Zammit Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 02 Jul 2021 08:21:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/qemu-x86: Increase heap size
by Angel Pons (Code Review) 02 Jul '21

02 Jul '21

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55761 ) Change subject: cpu/qemu-x86: Increase heap size ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > I guess the devicetree just grows too big with that many CPUs. It fails when generating PIRQ entries (late ramstage, IIRC during SSDT generation) -- To view, visit https://review.coreboot.org/c/coreboot/+/55761 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4f770a7a54d975d213b2456cc7d1ed9151cb6f9 Gerrit-Change-Number: 55761 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Jul 2021 08:20:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/qemu-x86: Increase heap size
by Angel Pons (Code Review) 02 Jul '21

02 Jul '21

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55761 ) Change subject: cpu/qemu-x86: Increase heap size ...................................................................... cpu/qemu-x86: Increase heap size On x86_64, the default heap size is too small when using 32 CPUs. Change-Id: Ib4f770a7a54d975d213b2456cc7d1ed9151cb6f9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55761 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/cpu/qemu-x86/Kconfig 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index 2f961dca..73aadfb 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -50,4 +50,7 @@ default 32 if SMM_TSEG default 4 +config HEAP_SIZE + default 0x8000 + endif -- To view, visit https://review.coreboot.org/c/coreboot/+/55761 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4f770a7a54d975d213b2456cc7d1ed9151cb6f9 Gerrit-Change-Number: 55761 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: cpu/intel/car/p4: Add support x86_64
by Angel Pons (Code Review) 02 Jul '21

02 Jul '21

Attention is currently required from: Arthur Heymans, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56021 ) Change subject: cpu/intel/car/p4: Add support x86_64 ...................................................................... Patch Set 1: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/56021/comment/7483540c_3c88cc6b PS1, Line 7: Add support x86_64 Either `Add support for x86_64` or `Add x86_64 support` Patchset: PS1: Will need to rebase atop what's merged of https://review.coreboot.org/q/topic:%22x86_64-kconfig%22 -- To view, visit https://review.coreboot.org/c/coreboot/+/56021 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77516e3cd5f0d3b7442be660c005a65b00454343 Gerrit-Change-Number: 56021 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 02 Jul 2021 08:19:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src: Consolidate x86_64 support Kconfig
by Angel Pons (Code Review) 02 Jul '21

02 Jul '21

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55760 ) Change subject: src: Consolidate x86_64 support Kconfig ...................................................................... src: Consolidate x86_64 support Kconfig Introduce `USE_EXP_X86_64_SUPPORT` in `src/arch/x86/Kconfig` and guard it with `HAVE_EXP_X86_64_SUPPORT`. Replace the per-CPU implementations of the same functionality with the newly-added Kconfig options. Update documentation and the config file for QEMU accordingly. Change-Id: I550216fd2a8323342d6b605306b0b95ffd5dcd1c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55760 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M Documentation/mainboard/emulation/qemu-i440fx.md M Documentation/mainboard/emulation/qemu-q35.md M configs/config.emulation_qemu_x86_i440fx_x86_64 M src/arch/x86/Kconfig M src/cpu/intel/model_206ax/Kconfig M src/cpu/qemu-x86/Kconfig 6 files changed, 23 insertions(+), 17 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/Documentation/mainboard/emulation/qemu-i440fx.md b/Documentation/mainboard/emulation/qemu-i440fx.md index 059ad12..a311fddb0 100644 --- a/Documentation/mainboard/emulation/qemu-i440fx.md +++ b/Documentation/mainboard/emulation/qemu-i440fx.md @@ -15,7 +15,7 @@ The qemu-i440fx mainboard has been ported to x86_64 and will serve as reference platform to enable additional platforms. -To enable the support set the Kconfig option ``CONFIG_CPU_QEMU_X86_64=y``. +To enable the support set the Kconfig option ``CONFIG_USE_EXP_X86_64_SUPPORT=y``. ## Installing qemu diff --git a/Documentation/mainboard/emulation/qemu-q35.md b/Documentation/mainboard/emulation/qemu-q35.md index 00163e8..cebbc63 100644 --- a/Documentation/mainboard/emulation/qemu-q35.md +++ b/Documentation/mainboard/emulation/qemu-q35.md @@ -15,7 +15,7 @@ The qemu-q35 mainboard has been ported to x86_64 and will serve as reference platform to enable additional platforms. -To enable the support set the Kconfig option ``CONFIG_CPU_QEMU_X86_64=y``. +To enable the support set the Kconfig option ``CONFIG_USE_EXP_X86_64_SUPPORT=y``. ## Installing qemu diff --git a/configs/config.emulation_qemu_x86_i440fx_x86_64 b/configs/config.emulation_qemu_x86_i440fx_x86_64 index 0ddb3f1..d31bbf2 100644 --- a/configs/config.emulation_qemu_x86_i440fx_x86_64 +++ b/configs/config.emulation_qemu_x86_i440fx_x86_64 @@ -1 +1 @@ -CONFIG_CPU_QEMU_X86_64=y +CONFIG_USE_EXP_X86_64_SUPPORT=y diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 2a42a1c..ef07a2a 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -63,6 +63,24 @@ bool default y +config HAVE_EXP_X86_64_SUPPORT + bool + help + Enable experimental support to build and run coreboot in 64-bit mode. + When selecting this option for a new platform, it is highly advisable + to provide a config file for Jenkins to build-test the 64-bit option. + +config USE_EXP_X86_64_SUPPORT + bool "[EXPERIMENTAL] Run coreboot in long (64-bit) mode" + depends on HAVE_EXP_X86_64_SUPPORT + select ARCH_ALL_STAGES_X86_64 + help + When set, most of coreboot runs in long (64-bit) mode instead of the + usual protected flat (32-bit) mode. 64-bit CPUs and OSes can be used + irrespective of whether coreboot runs in 32-bit or 64-bit mode. This + is an experimental option: do not enable unless one wants to test it + and has the means to recover a system when coreboot fails to boot. + config ARCH_X86_64_PGTBL_LOC hex "x86_64 page table location in CBFS" depends on ARCH_BOOTBLOCK_X86_64 diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 67fd701..c168c9b 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -3,16 +3,11 @@ if CPU_INTEL_MODEL_206AX -config ARCH_EXP_X86_64 - bool "Experimental 64bit support" - depends on USE_NATIVE_RAMINIT - default n - config CPU_SPECIFIC_OPTIONS def_bool y - select ARCH_ALL_STAGES_X86_64 if ARCH_EXP_X86_64 select ARCH_X86 select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES + select HAVE_EXP_X86_64_SUPPORT if USE_NATIVE_RAMINIT select MMX select SSE2 select UDELAY_TSC diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index 6d897fe..2f961dca 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -3,6 +3,7 @@ config CPU_QEMU_X86 bool select ARCH_X86 + select HAVE_EXP_X86_64_SUPPORT select UDELAY_TSC select TSC_MONOTONIC_TIMER select UNKNOWN_TSC_RATE @@ -49,12 +50,4 @@ default 32 if SMM_TSEG default 4 -config CPU_QEMU_X86_64 - bool "Experimental 64bit support" - select ARCH_ALL_STAGES_X86_64 - -config CPU_QEMU_X86_32 - bool - default n if CPU_QEMU_X86_64 - default y endif -- To view, visit https://review.coreboot.org/c/coreboot/+/55760 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I550216fd2a8323342d6b605306b0b95ffd5dcd1c Gerrit-Change-Number: 55760 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: src: Introduce `ARCH_ALL_STAGES_X86`
by Angel Pons (Code Review) 02 Jul '21

02 Jul '21

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55759 ) Change subject: src: Introduce `ARCH_ALL_STAGES_X86` ...................................................................... src: Introduce `ARCH_ALL_STAGES_X86` Introduce the `ARCH_ALL_STAGES_X86` Kconfig symbol to automatically select the per-stage arch options. Subsequent commits will leverage this to allow choosing between 32-bit and 64-bit coreboot where all stages are x86. AMD Picasso and AMD Cezanne are the only exceptions to this rule: they disable `ARCH_ALL_STAGES_X86` and explicitly set the per-stage arch options accordingly. Change-Id: Ia2ddbae8c0dfb5301352d725032f6ebd370428c9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55759 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/arch/x86/Kconfig M src/cpu/amd/agesa/Kconfig M src/cpu/amd/pi/Kconfig M src/cpu/intel/haswell/Kconfig M src/cpu/intel/model_1067x/Kconfig M src/cpu/intel/model_106cx/Kconfig M src/cpu/intel/model_2065x/Kconfig M src/cpu/intel/model_206ax/Kconfig M src/cpu/intel/model_65x/Kconfig M src/cpu/intel/model_67x/Kconfig M src/cpu/intel/model_68x/Kconfig M src/cpu/intel/model_6bx/Kconfig M src/cpu/intel/model_6ex/Kconfig M src/cpu/intel/model_6fx/Kconfig M src/cpu/intel/model_6xx/Kconfig M src/cpu/intel/model_f2x/Kconfig M src/cpu/intel/model_f3x/Kconfig M src/cpu/intel/model_f4x/Kconfig M src/cpu/qemu-x86/Kconfig M src/soc/amd/cezanne/Kconfig M src/soc/amd/picasso/Kconfig M src/soc/amd/stoneyridge/Kconfig M src/soc/example/min86/Kconfig M src/soc/intel/alderlake/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/quark/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/tigerlake/Kconfig M src/soc/intel/xeon_sp/Kconfig 36 files changed, 11 insertions(+), 33 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 1003376..2a42a1c 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -28,6 +28,7 @@ config ARCH_ALL_STAGES_X86_32 bool + default ARCH_ALL_STAGES_X86 && !ARCH_ALL_STAGES_X86_64 select ARCH_BOOTBLOCK_X86_32 select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 @@ -58,6 +59,10 @@ select ARCH_ROMSTAGE_X86_64 select ARCH_RAMSTAGE_X86_64 +config ARCH_ALL_STAGES_X86 + bool + default y + config ARCH_X86_64_PGTBL_LOC hex "x86_64 page table location in CBFS" depends on ARCH_BOOTBLOCK_X86_64 diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index f71b8ed..15622c9 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -6,7 +6,6 @@ default y if CPU_AMD_AGESA_FAMILY15_TN default y if CPU_AMD_AGESA_FAMILY16_KB default n - select ARCH_ALL_STAGES_X86_32 select ARCH_X86 select DRIVERS_AMD_PI select TSC_SYNC_LFENCE diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index 4cc6902..aff8d7dc 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -4,7 +4,6 @@ bool default y if CPU_AMD_PI_00730F01 default n - select ARCH_ALL_STAGES_X86_32 select ARCH_X86 select DRIVERS_AMD_PI select TSC_SYNC_LFENCE diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 1c91941..9830305 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -6,7 +6,6 @@ config CPU_SPECIFIC_OPTIONS def_bool y - select ARCH_ALL_STAGES_X86_32 select ARCH_X86 select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select MMX diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig index 6ddb99e..a710e67 100644 --- a/src/cpu/intel/model_1067x/Kconfig +++ b/src/cpu/intel/model_1067x/Kconfig @@ -1,6 +1,5 @@ config CPU_INTEL_MODEL_1067X bool - select ARCH_ALL_STAGES_X86_32 select ARCH_X86 select SSE2 select UDELAY_TSC diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index 9f59b47..ac45cfa 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -1,6 +1,5 @@ config CPU_INTEL_MODEL_106CX bool - select ARCH_ALL_STAGES_X86_32 select ARCH_X86 select SSE2 select UDELAY_TSC diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index f539247..731ea37 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -5,7 +5,6 @@ config CPU_SPECIFIC_OPTIONS def_bool y - select ARCH_ALL_STAGES_X86_32 select ARCH_X86 select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select SSE2 diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 9a0d792..67fd701 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -10,7 +10,6 @@ config CPU_SPECIFIC_OPTIONS def_bool y - select ARCH_ALL_STAGES_X86_32 if !ARCH_EXP_X86_64 select ARCH_ALL_STAGES_X86_64 if ARCH_EXP_X86_64 select ARCH_X86 select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES diff --git a/src/cpu/intel/model_65x/Kconfig b/src/cpu/intel/model_65x/Kconfig index f9d1236..6d41d94 100644 --- a/src/cpu/intel/model_65x/Kconfig +++ b/src/cpu/intel/model_65x/Kconfig @@ -1,5 +1,4 @@ config CPU_INTEL_MODEL_65X bool - select ARCH_ALL_STAGES_X86_32 select ARCH_X86 select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_67x/Kconfig b/src/cpu/intel/model_67x/Kconfig index 2fce135..26a303b 100644 --- a/src/cpu/intel/model_67x/Kconfig +++ b/src/cpu/intel/model_67x/Kconfig @@ -1,5 +1,4 @@ config CPU_INTEL_MODEL_67X bool - select ARCH_ALL_STAGES_X86_32 select ARCH_X86 select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_68x/Kconfig b/src/cpu/intel/model_68x/Kconfig index 67d4b77..79629077 100644 --- a/src/cpu/intel/model_68x/Kconfig +++ b/src/cpu/intel/model_68x/Kconfig @@ -2,6 +2,5 @@ config CPU_INTEL_MODEL_68X bool - select ARCH_ALL_STAGES_X86_32 select ARCH_X86 select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_6bx/Kconfig b/src/cpu/intel/model_6bx/Kconfig index 418f9bd..14274a3 100644 --- a/src/cpu/intel/model_6bx/Kconfig +++ b/src/cpu/intel/model_6bx/Kconfig @@ -1,5 +1,4 @@ config CPU_INTEL_MODEL_6BX bool - select ARCH_ALL_STAGES_X86_32 select ARCH_X86 select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_6ex/Kconfig b/src/cpu/intel/model_6ex/Kconfig index 240cee6..c7d54c5 100644 --- a/src/cpu/intel/model_6ex/Kconfig +++ b/src/cpu/intel/model_6ex/Kconfig @@ -1,6 +1,5 @@ config CPU_INTEL_MODEL_6EX bool - select ARCH_ALL_STAGES_X86_32 select ARCH_X86 select SSE2 select UDELAY_TSC diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig index 048178a..4999726 100644 --- a/src/cpu/intel/model_6fx/Kconfig +++ b/src/cpu/intel/model_6fx/Kconfig @@ -1,6 +1,5 @@ config CPU_INTEL_MODEL_6FX bool - select ARCH_ALL_STAGES_X86_32 select ARCH_X86 select SSE2 select UDELAY_TSC diff --git a/src/cpu/intel/model_6xx/Kconfig b/src/cpu/intel/model_6xx/Kconfig index eb2268a..e05cf89 100644 --- a/src/cpu/intel/model_6xx/Kconfig +++ b/src/cpu/intel/model_6xx/Kconfig @@ -1,5 +1,4 @@ config CPU_INTEL_MODEL_6XX bool - select ARCH_ALL_STAGES_X86_32 select ARCH_X86 select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_f2x/Kconfig b/src/cpu/intel/model_f2x/Kconfig index e1708ba..672cf75 100644 --- a/src/cpu/intel/model_f2x/Kconfig +++ b/src/cpu/intel/model_f2x/Kconfig @@ -1,6 +1,5 @@ config CPU_INTEL_MODEL_F2X bool - select ARCH_ALL_STAGES_X86_32 select ARCH_X86 select SUPPORT_CPU_UCODE_IN_CBFS select SMM_ASEG diff --git a/src/cpu/intel/model_f3x/Kconfig b/src/cpu/intel/model_f3x/Kconfig index 151a8e7..b0a9f7c 100644 --- a/src/cpu/intel/model_f3x/Kconfig +++ b/src/cpu/intel/model_f3x/Kconfig @@ -1,6 +1,5 @@ config CPU_INTEL_MODEL_F3X bool - select ARCH_ALL_STAGES_X86_32 select ARCH_X86 select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON diff --git a/src/cpu/intel/model_f4x/Kconfig b/src/cpu/intel/model_f4x/Kconfig index 2d31655..550a978 100644 --- a/src/cpu/intel/model_f4x/Kconfig +++ b/src/cpu/intel/model_f4x/Kconfig @@ -1,5 +1,4 @@ config CPU_INTEL_MODEL_F4X bool - select ARCH_ALL_STAGES_X86_32 select ARCH_X86 select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index 440d8cb..6d897fe 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -57,5 +57,4 @@ bool default n if CPU_QEMU_X86_64 default y - select ARCH_ALL_STAGES_X86_32 endif diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 78db12f..7dd3447 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -70,6 +70,9 @@ select X86_AMD_FIXED_MTRRS select X86_AMD_INIT_SIPI +config ARCH_ALL_STAGES_X86 + default n + config SOC_AMD_COMMON_BLOCK_UCODE_SIZE default 5568 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 44728a8..42c3bfc 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -69,6 +69,9 @@ select UDK_2017_BINDING select HAVE_CF9_RESET +config ARCH_ALL_STAGES_X86 + default n + config SOC_AMD_COMMON_BLOCK_UCODE_SIZE default 3200 diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 0e80f14..821d1ee 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -10,7 +10,6 @@ config CPU_SPECIFIC_OPTIONS def_bool y select ACPI_SOC_NVS - select ARCH_ALL_STAGES_X86_32 select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select COLLECT_TIMESTAMPS_NO_TSC diff --git a/src/soc/example/min86/Kconfig b/src/soc/example/min86/Kconfig index 66c0e8b..660bf36 100644 --- a/src/soc/example/min86/Kconfig +++ b/src/soc/example/min86/Kconfig @@ -14,7 +14,6 @@ config SOC_SPECIFIC_OPTIONS def_bool y - select ARCH_ALL_STAGES_X86_32 select ARCH_X86 select NO_MONOTONIC_TIMER select NO_MMCONF_SUPPORT diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 3c49748..4cb512a 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -13,7 +13,6 @@ config CPU_SPECIFIC_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select ARCH_ALL_STAGES_X86_32 select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 5b743c6..d81015e 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -24,7 +24,6 @@ def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_NO_PCAT_8259 - select ARCH_ALL_STAGES_X86_32 select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES # CPU specific options diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 6c5610d..305e5b7 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -8,7 +8,6 @@ config CPU_SPECIFIC_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select ARCH_ALL_STAGES_X86_32 select ARCH_X86 select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select BOOT_DEVICE_SUPPORTS_WRITES diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 7301d63..8ccf043 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -8,7 +8,6 @@ config CPU_SPECIFIC_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select ARCH_ALL_STAGES_X86_32 select ARCH_X86 select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select BOOT_DEVICE_SUPPORTS_WRITES diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 5fc80af..8f2f9d2 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -47,7 +47,6 @@ def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_NHLT - select ARCH_ALL_STAGES_X86_32 select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 4169ec4..bfd8c3f 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -13,7 +13,6 @@ config CPU_SPECIFIC_OPTIONS def_bool y - select ARCH_ALL_STAGES_X86_32 select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES select DEBUG_GPIO diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index f440d33..a6498b0 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -8,7 +8,6 @@ config CPU_SPECIFIC_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select ARCH_ALL_STAGES_X86_32 select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index e5ab889..1396460 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -8,7 +8,6 @@ config CPU_SPECIFIC_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select ARCH_ALL_STAGES_X86_32 select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index a05cd72..4d01d31 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -8,7 +8,6 @@ config CPU_SPECIFIC_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select ARCH_ALL_STAGES_X86_32 select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index ffb08c6..497322f 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -9,7 +9,6 @@ config CPU_SPECIFIC_OPTIONS def_bool y - select ARCH_ALL_STAGES_X86_32 select ARCH_X86 select NO_MMCONF_SUPPORT select REG_SCRIPT diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index d16a7c9..9136a5f 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -23,7 +23,6 @@ def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_NHLT - select ARCH_ALL_STAGES_X86_32 select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index e41d7a7..9dc38a5 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -8,7 +8,6 @@ config CPU_SPECIFIC_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select ARCH_ALL_STAGES_X86_32 select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 1a63e59..60786aa 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -26,7 +26,6 @@ config CPU_SPECIFIC_OPTIONS def_bool y - select ARCH_ALL_STAGES_X86_32 select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES select CPU_INTEL_COMMON -- To view, visit https://review.coreboot.org/c/coreboot/+/55759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2ddbae8c0dfb5301352d725032f6ebd370428c9 Gerrit-Change-Number: 55759 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit July 2021