coreboot-gerrit July 2021

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Change in coreboot[master]: nb/intel/x4x: Use write32p
by Arthur Heymans (Code Review) 02 Jul '21

02 Jul '21

Attention is currently required from: Damien Zammit, Angel Pons, Patrick Rudolph. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56029 ) Change subject: nb/intel/x4x: Use write32p ...................................................................... nb/intel/x4x: Use write32p This removes the need for type conversions all over the place. Change-Id: I633a453aff17f1cbbe06b60e3efb67661733d06c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/dq_dqs.c M src/northbridge/intel/x4x/raminit_ddr23.c M src/northbridge/intel/x4x/rcven.c 3 files changed, 13 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/56029/1 diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c index cda503e..e4cc888 100644 --- a/src/northbridge/intel/x4x/dq_dqs.c +++ b/src/northbridge/intel/x4x/dq_dqs.c @@ -170,13 +170,13 @@ if ((count1 % 16) == 0) mchbar_write32(0xf90, 1); const u32 pattern = write_training_schedule[count1]; - write32((u32 *)(uintptr_t)address + 8 * count1, pattern); - write32((u32 *)(uintptr_t)address + 8 * count1 + 4, pattern); + write32p(address + 8 * count1, pattern); + write32p(address + 8 * count1 + 4, pattern); } const u32 good = write_training_schedule[count]; - write32(&data[0], read32((u32 *)(uintptr_t)address + 8 * count)); - write32(&data[4], read32((u32 *)(uintptr_t)address + 8 * count + 4)); + write32(&data[0], read32p(address + 8 * count)); + write32(&data[4], read32p(address + 8 * count + 4)); FOR_EACH_BYTELANE(lane) { u8 expected = (good >> ((lane % 4) * 8)) & 0xff; if (data[lane] != expected) @@ -353,8 +353,8 @@ address = test_address(channel, rank); for (i = 0; i < RT_PATTERN_SIZE; i++) { const u32 good = read_training_schedule[i]; - write32(&data[0], read32((u32 *)(uintptr_t)address + i * 8)); - write32(&data[4], read32((u32 *)(uintptr_t)address + i * 8 + 4)); + write32(&data[0], read32p(address + i * 8)); + write32(&data[4], read32p(address + i * 8 + 4)); FOR_EACH_BYTELANE(lane) { if (data[lane] != (good & 0xff)) @@ -442,8 +442,8 @@ address = test_address(channel, rank); for (i = 0; i < RT_PATTERN_SIZE; i++) { content = read_training_schedule[i]; - write32((u32 *)(uintptr_t)address + 8 * i, content); - write32((u32 *)(uintptr_t)address + 8 * i + 4, content); + write32p(address + 8 * i, content); + write32p(address + 8 * i + 4, content); } } @@ -617,8 +617,8 @@ memset(high_found, 0, TOTAL_BYTELANES * sizeof(high_found[0])); for (samples = 0; samples < N_SAMPLES; samples++) { - write32((u32 *)(uintptr_t)address, 0x12341234); - write32((u32 *)(uintptr_t)address + 4, 0x12341234); + write32p(address, 0x12341234); + write32p(address + 4, 0x12341234); udelay(5); FOR_EACH_BYTELANE(lane) { u8 dq_high = (mchbar_read8(0x561 + 0x400 * channel diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index 126a44b..d19a83a 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -1283,7 +1283,7 @@ } data32 <<= 3; - read32((void *)(uintptr_t)(data32 | addr)); + read32p(data32 | addr); udelay(10); mchbar_clrsetbits8(0x271, 0x3e, NORMALOP_CMD); mchbar_clrsetbits8(0x671, 0x3e, NORMALOP_CMD); @@ -2090,7 +2090,7 @@ if (s->boot_path == BOOT_PATH_NORMAL) { FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { for (bank = 0; bank < 4; bank++) - read32((u32 *)(uintptr_t)(test_address(ch, r) | 0x800000 | (bank << 12))); + read32p(test_address(ch, r) | 0x800000 | (bank << 12)); } } printk(BIOS_DEBUG, "Done dummy reads\n"); diff --git a/src/northbridge/intel/x4x/rcven.c b/src/northbridge/intel/x4x/rcven.c index 5bb395a..1f8be79 100644 --- a/src/northbridge/intel/x4x/rcven.c +++ b/src/northbridge/intel/x4x/rcven.c @@ -38,7 +38,7 @@ } mfence(); /* Read strobe */ - read32((void *)(uintptr_t)addr); + read32p(addr); mfence(); return mchbar_read8(sample_offset) >> 6 & 1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/56029 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I633a453aff17f1cbbe06b60e3efb67661733d06c Gerrit-Change-Number: 56029 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Damien Zammit Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/x4x: Expose x86_64 support
by Arthur Heymans (Code Review) 02 Jul '21

02 Jul '21

Attention is currently required from: Damien Zammit, Patrick Rudolph. Hello build bot (Jenkins), Damien Zammit, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56022 to look at the new patch set (#2). Change subject: nb/intel/x4x: Expose x86_64 support ...................................................................... nb/intel/x4x: Expose x86_64 support TESTED on foxconn g41m. Change-Id: I2d5d5dfbd76a84aa400e44b4bc2ac4f3b5b6f739 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/56022/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56022 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d5d5dfbd76a84aa400e44b4bc2ac4f3b5b6f739 Gerrit-Change-Number: 56022 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Damien Zammit Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/intel/car/p4: Add support x86_64
by Arthur Heymans (Code Review) 02 Jul '21

02 Jul '21

Attention is currently required from: Arthur Heymans, Patrick Rudolph. Hello build bot (Jenkins), Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56021 to look at the new patch set (#2). Change subject: cpu/intel/car/p4: Add support x86_64 ...................................................................... cpu/intel/car/p4: Add support x86_64 Change-Id: I77516e3cd5f0d3b7442be660c005a65b00454343 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/car/p4-netburst/cache_as_ram.S 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/56021/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56021 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77516e3cd5f0d3b7442be660c005a65b00454343 Gerrit-Change-Number: 56021 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Add support to update the FIVR configs
by V Sowmya (Code Review) 02 Jul '21

02 Jul '21

Attention is currently required from: Kedar J. Karanje, Maulik V Vaghela, vagdevi.p(a)intel.com, Tim Wawrzynczak, Subrata Banik, Vinay Kumar, Patrick Rudolph. V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55702 ) Change subject: soc/intel/alderlake: Add support to update the FIVR configs ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/alderlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/55702/comment/4af101e1_b62b906a PS5, Line 543: if (config->ext_fivr_settings.configure_ext_fivr) { > if (!config->ext_fivr_settings.configure_ext_fivr) […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/55702 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf6c74bda5a167abf63938ebed6affc6b31c76f5 Gerrit-Change-Number: 55702 Gerrit-PatchSet: 6 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: vagdevi.p(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: vagdevi.p(a)intel.com Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 02 Jul 2021 10:12:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya0: Update the FIVR configurations
by V Sowmya (Code Review) 02 Jul '21

02 Jul '21

Attention is currently required from: Kedar J. Karanje, Maulik V Vaghela, vagdevi.p(a)intel.com, Tim Wawrzynczak, Subrata Banik, Vinay Kumar. V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55704 ) Change subject: mb/google/brya0: Update the FIVR configurations ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/55704/comment/2620efdd_8ed42d61 PS3, Line 11: bypass rails impletemented. > you can fit upto col 72 Done File src/mainboard/google/brya/variants/brya0/overridetree.cb: https://review.coreboot.org/c/coreboot/+/55704/comment/ee29ae3d_3e9175b7 PS3, Line 40: impletemented > implemented Done -- To view, visit https://review.coreboot.org/c/coreboot/+/55704 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c4fdb38c5c56798935b2c6627a75c3f1ac9fbef Gerrit-Change-Number: 55704 Gerrit-PatchSet: 4 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: vagdevi.p(a)intel.com Gerrit-Attention: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: vagdevi.p(a)intel.com Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Comment-Date: Fri, 02 Jul 2021 10:12:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya0: Update the FIVR configurations
by V Sowmya (Code Review) 02 Jul '21

02 Jul '21

Attention is currently required from: Kedar J. Karanje, Maulik V Vaghela, vagdevi.p(a)intel.com, Vinay Kumar. Hello build bot (Jenkins), Kedar J. Karanje, Maulik V Vaghela, vagdevi.p(a)intel.com, Tim Wawrzynczak, Subrata Banik, Vinay Kumar, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55704 to look at the new patch set (#4). Change subject: mb/google/brya0: Update the FIVR configurations ...................................................................... mb/google/brya0: Update the FIVR configurations This patch sets the disable the external voltage rails since brya board doesn't have V1p05 and Vnn bypass rails implemented. Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Change-Id: I1c4fdb38c5c56798935b2c6627a75c3f1ac9fbef --- M src/mainboard/google/brya/variants/brya0/overridetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/55704/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/55704 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c4fdb38c5c56798935b2c6627a75c3f1ac9fbef Gerrit-Change-Number: 55704 Gerrit-PatchSet: 4 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: vagdevi.p(a)intel.com Gerrit-Attention: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: vagdevi.p(a)intel.com Gerrit-Attention: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Add support to update the FIVR configs
by V Sowmya (Code Review) 02 Jul '21

02 Jul '21

Attention is currently required from: V Sowmya, Kedar J. Karanje, Maulik V Vaghela, vagdevi.p(a)intel.com, Tim Wawrzynczak, Vinay Kumar, Patrick Rudolph. Hello build bot (Jenkins), Kedar J. Karanje, Maulik V Vaghela, vagdevi.p(a)intel.com, Tim Wawrzynczak, Subrata Banik, Vinay Kumar, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55702 to look at the new patch set (#6). Change subject: soc/intel/alderlake: Add support to update the FIVR configs ...................................................................... soc/intel/alderlake: Add support to update the FIVR configs This patch adds the supports to update the optimal FIVR configurations for external voltage rails via devicetree. Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Change-Id: Icf6c74bda5a167abf63938ebed6affc6b31c76f5 --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c 2 files changed, 89 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/55702/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/55702 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf6c74bda5a167abf63938ebed6affc6b31c76f5 Gerrit-Change-Number: 55702 Gerrit-PatchSet: 6 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: vagdevi.p(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: vagdevi.p(a)intel.com Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block/acpi: Move pep.asl to acpigen
by Angel Pons (Code Review) 02 Jul '21

02 Jul '21

Attention is currently required from: Cliff Huang, Furquan Shaikh, Tim Wawrzynczak, Michael Niewöhner, Angel Pons, Patrick Rudolph, Karthik Ramasubramanian. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56004 ) Change subject: soc/intel/common/block/acpi: Move pep.asl to acpigen ...................................................................... Patch Set 1: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/56004/comment/82a24b75_6ad1cc20 PS1, Line 13: TEST=select this on brya, dump SSDT: If true, I'd explicitly mention that the resulting SSDT is equivalent to the DSDT File src/soc/intel/common/block/acpi/pep.c: https://review.coreboot.org/c/coreboot/+/56004/comment/c9e69baf_5c3c43f5 PS1, Line 25: 0x63 How about: 1 << 6 | 1 << 5 | 1 << 1 | 1 << 0 https://review.coreboot.org/c/coreboot/+/56004/comment/1bed5dba_a79de377 PS1, Line 33: static void lpi_get_constraints(void *unused) > please, no spaces at the start of a line Please fix. https://review.coreboot.org/c/coreboot/+/56004/comment/f3b13529_df6e17d0 PS1, Line 40: "\\NULL" I vaguely recall seeing some ASL that used the host bridge device here. Although I don't think it would make much of a difference (constraints are disabled), IMHO it feels slightly "less wrong" to me, whatever it means. https://review.coreboot.org/c/coreboot/+/56004/comment/8723fcdc_308eb9cb PS1, Line 37: acpigen_emit_byte(RETURN_OP); : acpigen_write_package(1); : acpigen_write_package(3); : acpigen_emit_namestring("\\NULL"); /* non-existent */ : acpigen_write_integer(0); /* disabled, no constraints */ : acpigen_write_package(2); : acpigen_write_integer(0); /* revision */ : acpigen_write_package(2); : acpigen_write_integer(0xff); /* apply to all LPIT states */ : acpigen_write_integer(0); /* minimum D-state */ : acpigen_write_package_end(); /* inner 3 */ : acpigen_write_package_end(); /* inner 2 */ : acpigen_write_package_end(); /* inner 1 */ : acpigen_write_package_end(); /* outer */ How about using scopes to show what closes what? acpigen_emit_byte(RETURN_OP); acpigen_write_package(1); { acpigen_write_package(3); { acpigen_emit_namestring("\\NULL"); /* non-existent */ acpigen_write_integer(0); /* disabled, no constraints */ acpigen_write_package(2); { acpigen_write_integer(0); /* revision */ acpigen_write_package(2); { acpigen_write_integer(0xff); /* apply to all LPIT states */ acpigen_write_integer(0); /* minimum D-state */ } acpigen_write_package_end(); } acpigen_write_package_end(); } acpigen_write_package_end(); } acpigen_write_package_end(); -- To view, visit https://review.coreboot.org/c/coreboot/+/56004 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie83722e0ed5792e338fc5c39a57eef43b7464e3b Gerrit-Change-Number: 56004 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 02 Jul 2021 09:40:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add GFx Device ID 0x46a6
by Meera Ravindranath (Code Review) 02 Jul '21

02 Jul '21

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph. Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56026 ) Change subject: soc/intel/alderlake: Add GFx Device ID 0x46a6 ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/56026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ca875c7faf2997d207aff9e292f94a3b6311e94 Gerrit-Change-Number: 56026 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 02 Jul 2021 09:34:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add GFx Device ID 0x46a6
by Maulik V Vaghela (Code Review) 02 Jul '21

02 Jul '21

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56026 ) Change subject: soc/intel/alderlake: Add GFx Device ID 0x46a6 ...................................................................... soc/intel/alderlake: Add GFx Device ID 0x46a6 This CL adds support for new ADL graphics Device ID 0x46a6. TEST=Build and boot Adlrvp board Change-Id: I8ca875c7faf2997d207aff9e292f94a3b6311e94 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/include/device/pci_ids.h M src/soc/intel/alderlake/bootblock/report_platform.c M src/soc/intel/common/block/graphics/graphics.c 3 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/56026/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 541d38e..f3f16fb 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3818,6 +3818,7 @@ #define PCI_DEVICE_ID_INTEL_ADL_P_GT2_3 0x46a3 #define PCI_DEVICE_ID_INTEL_ADL_P_GT2_4 0x46a8 #define PCI_DEVICE_ID_INTEL_ADL_P_GT2_5 0x46b3 +#define PCI_DEVICE_ID_INTEL_ADL_P_GT2_6 0x46a6 #define PCI_DEVICE_ID_INTEL_ADL_S_GT1 0x4680 #define PCI_DEVICE_ID_INTEL_ADL_M_GT1 0x46c0 diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c index 5ddc322..d811123 100644 --- a/src/soc/intel/alderlake/bootblock/report_platform.c +++ b/src/soc/intel/alderlake/bootblock/report_platform.c @@ -105,6 +105,7 @@ { PCI_DEVICE_ID_INTEL_ADL_P_GT2_3, "Alderlake P GT2" }, { PCI_DEVICE_ID_INTEL_ADL_P_GT2_4, "Alderlake P GT2" }, { PCI_DEVICE_ID_INTEL_ADL_P_GT2_5, "Alderlake P GT2" }, + { PCI_DEVICE_ID_INTEL_ADL_P_GT2_6, "Alderlake P GT2" }, { PCI_DEVICE_ID_INTEL_ADL_M_GT1, "Alderlake M GT1" }, }; diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 61d39bd..b99d2a8 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -301,6 +301,7 @@ PCI_DEVICE_ID_INTEL_ADL_P_GT2_3, PCI_DEVICE_ID_INTEL_ADL_P_GT2_4, PCI_DEVICE_ID_INTEL_ADL_P_GT2_5, + PCI_DEVICE_ID_INTEL_ADL_P_GT2_6, PCI_DEVICE_ID_INTEL_ADL_S_GT1, PCI_DEVICE_ID_INTEL_ADL_M_GT1, 0, -- To view, visit https://review.coreboot.org/c/coreboot/+/56026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ca875c7faf2997d207aff9e292f94a3b6311e94 Gerrit-Change-Number: 56026 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit July 2021