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Change in coreboot[master]: soc/intel/common/block/acpi: Add LPM requirements support to PEPD _DSM
by Tim Wawrzynczak (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Patrick Rudolph. Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56005 ) Change subject: soc/intel/common/block/acpi: Add LPM requirements support to PEPD _DSM ...................................................................... soc/intel/common/block/acpi: Add LPM requirements support to PEPD _DSM This patch adds support for the S0ix UUID in the Intel Power Engine _DSM method. This allows the ACPI tables to expose device/IP power states requirements for different system low power states BUG=b:185437326 TEST=cat /sys/kernel/debug/pmc_core/substate_requirements Element | S0i2.0 | S0i3.0 | Status | USB2PLL_OFF_STS | Required | Required | Yes | PCIe/USB3.1_Gen2PLL_OFF_STS | Required | Required | | PCIe_Gen3PLL_OFF_STS | Required | Required | Yes | OPIOPLL_OFF_STS | Required | Required | | OCPLL_OFF_STS | Required | Required | Yes | MainPLL_OFF_STS | | Required | | MIPIPLL_OFF_STS | Required | Required | Yes | Fast_XTAL_Osc_OFF_STS | | Required | | AC_Ring_Osc_OFF_STS | Required | Required | Yes | SATAPLL_OFF_STS | Required | Required | Yes | XTAL_USB2PLL_OFF_STS | | Required | Yes | CSME_PG_STS | Required | Required | Yes | SATA_PG_STS | Required | Required | Yes | xHCI_PG_STS | Required | Required | | UFSX2_PG_STS | Required | Required | Yes | OTG_PG_STS | Required | Required | Yes | SPA_PG_STS | Required | Required | Yes | SPB_PG_STS | Required | Required | Yes | SPC_PG_STS | Required | Required | Yes | THC0_PG_STS | Required | Required | Yes | THC1_PG_STS | Required | Required | Yes | GBETSN_PG_STS | Required | Required | Yes | GBE_PG_STS | Required | Required | Yes | LPSS_PG_STS | Required | Required | | ADSP_D3_STS | | Required | Yes | xHCI0_D3_STS | Required | Required | | xDCI1_D3_STS | Required | Required | Yes | IS_D3_STS | Required | Required | | GBE_TSN_D3_STS | Required | Required | Yes | CPU_C10_REQ_STS_0 | Required | Required | Yes | CNVI_REQ_STS_6 | | Required | | ISH_REQ_STS_7 | | Required | Yes | MPHY_Core_DL_REQ_STS_16 | Required | Required | | Break-even_En_REQ_STS_17 | Required | Required | Yes | Auto-demo_En_REQ_STS_18 | Required | Required | Yes | Int_Timer_SS_Wake0_Pol_STS | Required | Required | | Int_Timer_SS_Wake1_Pol_STS | Required | Required | | Int_Timer_SS_Wake2_Pol_STS | Required | Required | | Int_Timer_SS_Wake3_Pol_STS | Required | Required | | Int_Timer_SS_Wake4_Pol_STS | Required | Required | | Int_Timer_SS_Wake5_Pol_STS | Required | Required | | Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I542290bd5490aa6580a5ae2b266da3d78bc17e6b --- M src/soc/intel/common/block/acpi/Kconfig M src/soc/intel/common/block/acpi/pep.c M src/soc/intel/common/block/include/intelblocks/pmc_ipc.h 3 files changed, 75 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/56005/1 diff --git a/src/soc/intel/common/block/acpi/Kconfig b/src/soc/intel/common/block/acpi/Kconfig index 12c0d45..8d6ede2 100644 --- a/src/soc/intel/common/block/acpi/Kconfig +++ b/src/soc/intel/common/block/acpi/Kconfig @@ -21,6 +21,15 @@ Generate an Intel Power Engine device object in the SSDT. This is usually used for providing ACPI hooks for S0ix exit/entry. +config SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ + bool + depends on SOC_INTEL_COMMON_BLOCK_ACPI_PEP + help + Generate a 2nd set of _DSM functions for the Power Engine device that + will return a buffer that contains the contents of the PMC's LPM + requirements registers. A kernel can use this to display the + requirements for different LPM substates. + config SOC_INTEL_COMMON_BLOCK_CRASHLOG bool depends on SOC_INTEL_CRASHLOG diff --git a/src/soc/intel/common/block/acpi/pep.c b/src/soc/intel/common/block/acpi/pep.c index 9723d28..1dcbb0a 100644 --- a/src/soc/intel/common/block/acpi/pep.c +++ b/src/soc/intel/common/block/acpi/pep.c @@ -3,17 +3,24 @@ #include <acpi/acpigen.h> #include <console/console.h> #include <intelblocks/acpi.h> +#include <intelblocks/pmc_ipc.h> #include <soc/pci_devs.h> #include <stdlib.h> #include <types.h> #define LPI_S0_HELPER_UUID "c4eb40a0-6cd2-11e2-bcfd-0800200c9a66" +#define PEP_S0IX_UUID "57a6512e-3979-4e9d-9708-ff13b2508972" #define SYSTEM_POWER_MANAGEMENT_HID "INT33A1" #define SYSTEM_POWER_MANAGEMENT_CID "PNP0D80" #define EC_S0IX_HOOK "\\_SB.PCI0.LPCB.EC0.S0IX" #define MAINBOARD_HOOK "\\_SB.MS0X" #define ENABLE_PM_BITS_HOOK "\\_SB.PCI0.EGPM" #define RESTORE_PM_BITS_HOOK "\\_SB.PCI0.RGPM" +#define LPM_STATES 8 +#define LPM_REQ_PER_STATE 6 +#define LPM_REGISTERS_COUNT (LPM_STATES * LPM_REQ_PER_STATE) +#define PMC_LPM_REQ_BASE 0x1000 +#define LPM_REQ_REG_STRIDE 48 /* * Supported functions bitmask @@ -105,10 +112,65 @@ lpi_s0ix_exit, /* s0ix exit */ }; +/* + * Supported functions bitmask + * bit 0: other functions than 0 are supported + * bits 1-6: function x supported + */ +static void pep_s0ix_enum_functions(void *unused) +{ + if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ)) + acpigen_write_return_singleton_buffer(0x03); + else + acpigen_write_return_singleton_buffer(0x00); +} + +static void pep_s0ix_collect_lpm_requirements(void *unused) +{ + if (!CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ)) + return; + + uint32_t *reg = calloc(LPM_REGISTERS_COUNT, sizeof(uint32_t)); + enum cb_err result = CB_SUCCESS; + uint32_t *ptr = reg; + + /* Read the various LPM state requirement registers from the PMC */ + for (size_t i = 0; i < LPM_STATES && result == CB_SUCCESS; i++) { + for (size_t j = 0; j < LPM_REQ_PER_STATE; j++) { + const uint32_t offset = PMC_LPM_REQ_BASE + i * LPM_REQ_REG_STRIDE + + j * sizeof(uint32_t); + const uint32_t cmd_reg = pmc_make_ipc_cmd(PMC_IPC_CMD_GENERAL_COMM, + PMC_IPC_SUBCMD_GEN_COMM_READ, + 0); + struct pmc_ipc_buffer req = {.buf[0] = offset}; + struct pmc_ipc_buffer res = {}; + + result = pmc_send_ipc_cmd(cmd_reg, &req, &res); + if (result != CB_SUCCESS) + break; + + *ptr++ = res.buf[0]; + } + } + + if (result == CB_SUCCESS) + acpigen_write_return_byte_buffer((uint8_t *)reg, LPM_REGISTERS_COUNT * sizeof(uint32_t)); + else + printk(BIOS_ERR, "ERROR: Failed to retrieve PMC LPM requirements registers\n"); + + free(reg); +} + +static void (*pep_s0ix[])(void *) = { + pep_s0ix_enum_functions, /* enumerate functions */ + pep_s0ix_collect_lpm_requirements, /* Return LPM requirements */ +}; + void generate_acpi_power_engine(const struct device *dev) { struct dsm_uuid ids[] = { DSM_UUID(LPI_S0_HELPER_UUID, lpi_s0_helpers, ARRAY_SIZE(lpi_s0_helpers), NULL), + DSM_UUID(PEP_S0IX_UUID, pep_s0ix, ARRAY_SIZE(pep_s0ix), NULL), }; const char *scope = acpi_device_scope(dev); diff --git a/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h b/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h index b67abc0..de21027 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h +++ b/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h @@ -21,6 +21,10 @@ #define PMC_IPC_CMD_NO_MSI 0 +/* IPC command for general communication */ +#define PMC_IPC_CMD_GENERAL_COMM 0xA0 +#define PMC_IPC_SUBCMD_GEN_COMM_READ 0x02 + /* IPC command to enable/disable PCIe SRCCLK */ #define PMC_IPC_CMD_ID_SET_PCIE_CLOCK 0xAC -- To view, visit https://review.coreboot.org/c/coreboot/+/56005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I542290bd5490aa6580a5ae2b266da3d78bc17e6b Gerrit-Change-Number: 56005 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/acpi: Move pep.asl to acpigen
by Tim Wawrzynczak (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Patrick Rudolph. Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56004 ) Change subject: soc/intel/common/block/acpi: Move pep.asl to acpigen ...................................................................... soc/intel/common/block/acpi: Move pep.asl to acpigen There is a use-case for generating the AML bytecode at runtime for the Intel Power Engine device, which comes in a followup patch. BUG=b:185437326 TEST=select this on brya, dump SSDT: Scope (\_SB.PCI0) { Device (PEPD) { Name (_HID, "INT33A1") Name (_CID, EisaId ("INT33A1") Method (_DSM, 4, Serialized) { ToBuffer (Arg0, Local0) If ((Local0 == ToUUID ("c4eb40a0-6cd2-11e2-bcfd-0800200c9a66"))) { ToInteger (Arg2, Local1) If ((Local1 == Zero)) { Return (Buffer (One) { 0x63 }) } If ((Local1 == One)) { Return (Package (0x01) { Package (0x03) { \NULL, Zero, Package (0x02) { Zero, Package (0x02) { 0xFF, Zero } } } }) } If ((Local1 == 0x02)){} If ((Local1 == 0x03)){} If ((Local1 == 0x04)){} If ((Local1 == 0x05)) { If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX)) { \_SB.PCI0.LPCB.EC0.S0IX (One) } If (CondRefOf (\_SB.MS0X)) { \_SB.MS0X (One) } If (CondRefOf (\_SB.PCI0.EGPM)) { \_SB.PCI0.EGPM () } } If ((Local1 == 0x06)) { If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX)) { \_SB.PCI0.LPCB.EC0.S0IX (Zero) } If (CondRefOf (\_SB.MS0X)) { \_SB.MS0X (Zero) } If (CondRefOf (\_SB.PCI0.RGPM)) { \_SB.PCI0.RGPM () } } Return (Buffer (One) { 0x00 }) } Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Ie83722e0ed5792e338fc5c39a57eef43b7464e3b --- M src/soc/intel/common/block/acpi/Kconfig M src/soc/intel/common/block/acpi/Makefile.inc A src/soc/intel/common/block/acpi/pep.c M src/soc/intel/common/block/include/intelblocks/acpi.h 4 files changed, 140 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/56004/1 diff --git a/src/soc/intel/common/block/acpi/Kconfig b/src/soc/intel/common/block/acpi/Kconfig index 6aa3abc..12c0d45 100644 --- a/src/soc/intel/common/block/acpi/Kconfig +++ b/src/soc/intel/common/block/acpi/Kconfig @@ -15,6 +15,12 @@ help Generate LPIT table with LPI state entries +config SOC_INTEL_COMMON_BLOCK_ACPI_PEP + bool + help + Generate an Intel Power Engine device object in the SSDT. This is + usually used for providing ACPI hooks for S0ix exit/entry. + config SOC_INTEL_COMMON_BLOCK_CRASHLOG bool depends on SOC_INTEL_CRASHLOG @@ -28,5 +34,4 @@ help Generate CPPC entries for Intel SpeedShift - endif diff --git a/src/soc/intel/common/block/acpi/Makefile.inc b/src/soc/intel/common/block/acpi/Makefile.inc index c78dbc0..c8eaad5 100644 --- a/src/soc/intel/common/block/acpi/Makefile.inc +++ b/src/soc/intel/common/block/acpi/Makefile.inc @@ -3,3 +3,4 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_LPIT) += lpit.c ramstage-$(CONFIG_ACPI_BERT) += acpi_bert.c ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_PEP) += pep.c diff --git a/src/soc/intel/common/block/acpi/pep.c b/src/soc/intel/common/block/acpi/pep.c new file mode 100644 index 0000000..9723d28 --- /dev/null +++ b/src/soc/intel/common/block/acpi/pep.c @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpigen.h> +#include <console/console.h> +#include <intelblocks/acpi.h> +#include <soc/pci_devs.h> +#include <stdlib.h> +#include <types.h> + +#define LPI_S0_HELPER_UUID "c4eb40a0-6cd2-11e2-bcfd-0800200c9a66" +#define SYSTEM_POWER_MANAGEMENT_HID "INT33A1" +#define SYSTEM_POWER_MANAGEMENT_CID "PNP0D80" +#define EC_S0IX_HOOK "\\_SB.PCI0.LPCB.EC0.S0IX" +#define MAINBOARD_HOOK "\\_SB.MS0X" +#define ENABLE_PM_BITS_HOOK "\\_SB.PCI0.EGPM" +#define RESTORE_PM_BITS_HOOK "\\_SB.PCI0.RGPM" + +/* + * Supported functions bitmask + * bit 0: other functions than 0 are supported + * bits 1-6: function x supported + */ +static void lpi_enum_functions(void *unused) +{ + acpigen_write_return_singleton_buffer(0x63); +} + +/* + * For now there is only one disabled non-existent device, because Windows + * expects at least one device and crashes without it with a bluescreen + * (`INTERNAL_POWER_ERROR`). Returning an empty package does not work. + */ + static void lpi_get_constraints(void *unused) +{ + /* Return (Package() { Package() { "\NULL", 0, + Package() { 0, Package() { 0xff, 0 }}}}) */ + acpigen_emit_byte(RETURN_OP); + acpigen_write_package(1); + acpigen_write_package(3); + acpigen_emit_namestring("\\NULL"); /* non-existent */ + acpigen_write_integer(0); /* disabled, no constraints */ + acpigen_write_package(2); + acpigen_write_integer(0); /* revision */ + acpigen_write_package(2); + acpigen_write_integer(0xff); /* apply to all LPIT states */ + acpigen_write_integer(0); /* minimum D-state */ + acpigen_write_package_end(); /* inner 3 */ + acpigen_write_package_end(); /* inner 2 */ + acpigen_write_package_end(); /* inner 1 */ + acpigen_write_package_end(); /* outer */ +} + +static void lpi_empty(void *unused) +{ +} + +static void lpi_s0ix_entry(void *unused) +{ + /* Inform the EC */ + acpigen_write_if_cond_refof(EC_S0IX_HOOK); + acpigen_emit_namestring(EC_S0IX_HOOK); + acpigen_write_integer(1); + acpigen_write_if_end(); + + /* Provide a board level S0ix hook */ + acpigen_write_if_cond_refof(MAINBOARD_HOOK); + acpigen_emit_namestring(MAINBOARD_HOOK); + acpigen_write_integer(1); + acpigen_write_if_end(); + + /* Save the current PM bits then enable GPIO PM with + MISCCFG_GPIO_PM_CONFIG_BITS */ + acpigen_write_if_cond_refof(ENABLE_PM_BITS_HOOK); + acpigen_emit_namestring(ENABLE_PM_BITS_HOOK); + acpigen_write_if_end(); +} + +static void lpi_s0ix_exit(void *unused) +{ + /* Inform the EC */ + acpigen_write_if_cond_refof(EC_S0IX_HOOK); + acpigen_emit_namestring(EC_S0IX_HOOK); + acpigen_write_integer(0); + acpigen_write_if_end(); + + /* Provide a board level S0ix hook */ + acpigen_write_if_cond_refof(MAINBOARD_HOOK); + acpigen_emit_namestring(MAINBOARD_HOOK); + acpigen_write_integer(0); + acpigen_write_if_end(); + + /* Restore GPIO all Community PM */ + acpigen_write_if_cond_refof(RESTORE_PM_BITS_HOOK); + acpigen_emit_namestring(RESTORE_PM_BITS_HOOK); + acpigen_write_if_end(); +} + +static void (*lpi_s0_helpers[])(void *) = { + lpi_enum_functions, /* enumerate functions */ + lpi_get_constraints, /* get device constraints */ + lpi_empty, /* get crash dump device */ + lpi_empty, /* display off notify */ + lpi_empty, /* display on notify */ + lpi_s0ix_entry, /* s0ix entry */ + lpi_s0ix_exit, /* s0ix exit */ +}; + +void generate_acpi_power_engine(const struct device *dev) +{ + struct dsm_uuid ids[] = { + DSM_UUID(LPI_S0_HELPER_UUID, lpi_s0_helpers, ARRAY_SIZE(lpi_s0_helpers), NULL), + }; + + const char *scope = acpi_device_scope(dev); + + acpigen_write_scope(scope); + acpigen_write_device("PEPD"); + + acpigen_write_name_string("_HID", SYSTEM_POWER_MANAGEMENT_HID); + acpigen_write_name("_CID"); + acpigen_emit_eisaid(SYSTEM_POWER_MANAGEMENT_HID); + + acpigen_write_dsm_uuid_arr(ids, ARRAY_SIZE(ids)); + + acpigen_write_device_end(); + acpigen_write_scope_end(); + + printk(BIOS_INFO, "%s: Intel Power Engine Plug-in\n", + acpi_device_path_join(dev->bus->dev, "PEPD")); +} diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h index 90d5e5e..6bba812 100644 --- a/src/soc/intel/common/block/include/intelblocks/acpi.h +++ b/src/soc/intel/common/block/include/intelblocks/acpi.h @@ -90,4 +90,7 @@ */ const struct madt_ioapic_info *soc_get_ioapic_info(size_t *entries); +/* Generate an Intel Power Engine ACPI device */ +void generate_acpi_power_engine(const struct device *dev); + #endif /* _SOC_INTEL_COMMON_BLOCK_ACPI_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/56004 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie83722e0ed5792e338fc5c39a57eef43b7464e3b Gerrit-Change-Number: 56004 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: acpi: Add function to simplify If (CondRefOf (..)) sequences
by Tim Wawrzynczak (Code Review) 01 Jul '21

01 Jul '21

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56003 ) Change subject: acpi: Add function to simplify If (CondRefOf (..)) sequences ...................................................................... acpi: Add function to simplify If (CondRefOf (..)) sequences The new function is called acpigen_write_if_cond_refof(), and it must be paired with a following acpigen_write_if_end() call. Change-Id: I6e192a569f550ecb77ad264275d52f219eacaca1 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/acpi/acpigen.c M src/include/acpi/acpigen.h 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/56003/1 diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index 9818dc2..515c3bb 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -2245,3 +2245,12 @@ acpigen_emit_byte(LOCAL7_OP); acpigen_pop_len(); /* While */ } + +/* Requires matching acpigen_write_if_end() */ +void acpigen_write_if_cond_refof(const char *namestring) +{ + acpigen_write_if(); + acpigen_emit_ext_op(COND_REFOF_OP); + acpigen_emit_namestring(namestring); + acpigen_emit_byte(ZERO_OP); /* ignore COND_REFOF_OP destination */ +} diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h index 2d0bb77..cf1b1e9 100644 --- a/src/include/acpi/acpigen.h +++ b/src/include/acpi/acpigen.h @@ -586,4 +586,7 @@ /* Emits Notify(namestr, value) */ void acpigen_notify(const char *namestr, int value); +/* Emits If (CondRefOf(NAME)) */ +void acpigen_write_if_cond_refof(const char *namestring); + #endif /* __ACPI_ACPIGEN_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/56003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e192a569f550ecb77ad264275d52f219eacaca1 Gerrit-Change-Number: 56003 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: selfboot: Add support for selfload in romstage
by Shelley Chen (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Ravi kumar, Paul Menzel, mturney mturney. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55865 ) Change subject: selfboot: Add support for selfload in romstage ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/55865/comment/041c901d_58a2a406 PS4, Line 11: > From the paste `undefined reference to `bootmem_region_targets_type'` could be added to the commit m […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/55865 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8dfa2f2079a9a2859114c53c22bf7ef466ac2ad9 Gerrit-Change-Number: 55865 Gerrit-PatchSet: 6 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Thu, 01 Jul 2021 17:30:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: selfboot: Add support for selfload in romstage
by Shelley Chen (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Shelley Chen, Ravi kumar, mturney mturney. Hello Ravi kumar, build bot (Jenkins), mturney mturney, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55865 to look at the new patch set (#6). Change subject: selfboot: Add support for selfload in romstage ...................................................................... selfboot: Add support for selfload in romstage Since bootmem is not available in romstage, calls to bootmem APIs need to be compile-time eliminated in order to avoid linker error: undefined reference to `bootmem_region_targets_type BUG=None BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_HEROBRINE -x -a -B cherry-picked on top of CB:49392 and verified successful compilation. Change-Id: I8dfa2f2079a9a2859114c53c22bf7ef466ac2ad9 Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/lib/selfboot.c 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/55865/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/55865 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8dfa2f2079a9a2859114c53c22bf7ef466ac2ad9 Gerrit-Change-Number: 55865 Gerrit-PatchSet: 6 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: HACK coreboot: Fix build errors in romstage HACK
by mturney mturney (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Shelley Chen, Ravi kumar, Dhavalp -, Ravi Kumar Bokka, Julius Werner. mturney mturney has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55595 ) Change subject: HACK coreboot: Fix build errors in romstage HACK ...................................................................... Patch Set 3: (1 comment) Patchset: PS1: > CB:55865 should fix the selfload issue in romstage "[Dhaval] SHRM image is multi segment elf with segments going to discontinuous memory and there is reserved space in between segments so it is technically not possible to merge in to single segment elf. SHRM is required for DDR initialization and must be loaded before QcLIB DDR configuration can be handled. Hence, Multi-segment elf loading support in ROMStage is required and unavoidable. Going back to history, to handle ROMStage limitation of not supporting multi-segment elf load during first project, we had to merge all QcLib segments which was workaround. We also had to split SoC logic in rom-stage and ram-stage for images like AOP which is also multi-segment elf and impossible to merge segments due to physically discontinuous memory hence AOP was loaded in ramstage. Now SHRM image is in the same boat as AOP and have to be loaded in ROMStage. With multi-segment elf support in ROMstage for SHRM, it makes complete sense to do what originally was planned by moving AOP and other possible SoC images loading to ROM stage." -- To view, visit https://review.coreboot.org/c/coreboot/+/55595 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9742c0d4d7616a78215247a98ce2e39825abae9 Gerrit-Change-Number: 55595 Gerrit-PatchSet: 3 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Dhavalp - <dhavalp(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Shelley Chen <shchen(a)google.com> Gerrit-CC: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Dhavalp - <dhavalp(a)codeaurora.org> Gerrit-Attention: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 01 Jul 2021 17:26:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Comment-In-Reply-To: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86: Add X86_CUSTOM_BOOTMEDIA
by Martin Roth (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Raul Rangel, Furquan Shaikh, Marshall Dawson, Angel Pons, Andrey Petrov, Patrick Rudolph. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55853 ) Change subject: arch/x86: Add X86_CUSTOM_BOOTMEDIA ...................................................................... Patch Set 1: Code-Review+2 (1 comment) File src/arch/x86/Kconfig: https://review.coreboot.org/c/coreboot/+/55853/comment/70a28c15_3a9a26a8 PS1, Line 126: this option Nit: This is probably fine, but you might want to make this specific: Turning on X86_CUSTOM_BOOTMEDIA disables X86_TOP4G_BOOTMEDIA_MAP which allows SoC code to provide acustom mmap_boot.c -- To view, visit https://review.coreboot.org/c/coreboot/+/55853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65bbc118bde88687a7d7749c87acf1cbdc56a269 Gerrit-Change-Number: 55853 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 01 Jul 2021 17:17:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/cpu: Cache the uCode to avoid multiple SPI reads
by Raul Rangel (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Jason Glenesk, Furquan Shaikh, Martin Roth, Marshall Dawson, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55987 ) Change subject: soc/amd/common/block/cpu: Cache the uCode to avoid multiple SPI reads ...................................................................... Patch Set 3: (1 comment) File src/soc/amd/common/block/cpu/update_microcode.c: https://review.coreboot.org/c/coreboot/+/55987/comment/6fd4e6e4_abd7fd4f PS2, Line 83: MPB_MAX_SIZE > Reading rest of the code again, could it be the case that there are multiple microcode files added t […] Ah you are right. I forgot about the list. Done. -- To view, visit https://review.coreboot.org/c/coreboot/+/55987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98b9d4ce8290a1f08063176809e903e671663208 Gerrit-Change-Number: 55987 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 01 Jul 2021 17:00:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: lib/cbfs,commonlib/mem_pool: Make cbfs_free take const pointer
by Raul Rangel (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Julius Werner. Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56002 ) Change subject: lib/cbfs,commonlib/mem_pool: Make cbfs_free take const pointer ...................................................................... lib/cbfs,commonlib/mem_pool: Make cbfs_free take const pointer BUG=b:177909625 TEST=Compile Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ie570825f9255d6499e977f6eace58589115e2552 --- M src/commonlib/include/commonlib/mem_pool.h M src/commonlib/mem_pool.c M src/include/cbfs.h M src/lib/cbfs.c 4 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/56002/1 diff --git a/src/commonlib/include/commonlib/mem_pool.h b/src/commonlib/include/commonlib/mem_pool.h index 6c85397..4ed1aa1 100644 --- a/src/commonlib/include/commonlib/mem_pool.h +++ b/src/commonlib/include/commonlib/mem_pool.h @@ -57,6 +57,6 @@ void *mem_pool_alloc(struct mem_pool *mp, size_t sz); /* Free allocation from memory pool. */ -void mem_pool_free(struct mem_pool *mp, void *alloc); +void mem_pool_free(struct mem_pool *mp, const void *alloc); #endif /* _MEM_POOL_H_ */ diff --git a/src/commonlib/mem_pool.c b/src/commonlib/mem_pool.c index c300c65..0feef03 100644 --- a/src/commonlib/mem_pool.c +++ b/src/commonlib/mem_pool.c @@ -23,7 +23,7 @@ return p; } -void mem_pool_free(struct mem_pool *mp, void *p) +void mem_pool_free(struct mem_pool *mp, const void *p) { /* Determine if p was the most recent allocation. */ if (p == NULL || mp->last_alloc != p) diff --git a/src/include/cbfs.h b/src/include/cbfs.h index 9ed5233..6e08438 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -99,7 +99,7 @@ /* Removes a previously allocated CBFS mapping. Should try to unmap mappings in strict LIFO order where possible, since mapping backends often don't support more complicated cases. */ -void cbfs_unmap(void *mapping); +void cbfs_unmap(const void *mapping); /* Load stage into memory filling in prog. Return 0 on success. < 0 on error. */ int cbfs_prog_stage_load(struct prog *prog); diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 32ebfaf..3247278 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -102,7 +102,7 @@ return 0; } -void cbfs_unmap(void *mapping) +void cbfs_unmap(const void *mapping) { /* * This is save to call with mappings that weren't allocated in the cache (e.g. x86 -- To view, visit https://review.coreboot.org/c/coreboot/+/56002 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie570825f9255d6499e977f6eace58589115e2552 Gerrit-Change-Number: 56002 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/block/cpu: Cache the uCode to avoid multiple SPI reads
by Raul Rangel (Code Review) 01 Jul '21

01 Jul '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson, Karthik Ramasubramanian, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Martin Roth, Marshall Dawson, Paul Menzel, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55987 to look at the new patch set (#3). Change subject: soc/amd/common/block/cpu: Cache the uCode to avoid multiple SPI reads ...................................................................... soc/amd/common/block/cpu: Cache the uCode to avoid multiple SPI reads We are currently reading the uCode for each CPU. This is unnecessary since the uCode never changes. BUG=b:177909625 TEST=Boot guybrush and see "microcode: being updated to patch id" for each CPU. I no longer see CBFS access for each CPU. This drops device initialization time by 32 ms. Also boot Ezkinil and verify microcode was also updated. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I98b9d4ce8290a1f08063176809e903e671663208 --- M src/soc/amd/common/block/cpu/update_microcode.c 1 file changed, 36 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/55987/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/55987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98b9d4ce8290a1f08063176809e903e671663208 Gerrit-Change-Number: 55987 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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coreboot-gerrit July 2021