coreboot-gerrit July 2021

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Change in coreboot[master]: mb/google/brya: Create redrix variant
by Felix Held (Code Review) 08 Jul '21

08 Jul '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55883 ) Change subject: mb/google/brya: Create redrix variant ...................................................................... mb/google/brya: Create redrix variant Create the redrix variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:192052098 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_REDRIX Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Change-Id: I4cfa0bd84e1ba9f8140f95d18a6da960da8124ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/55883 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name A src/mainboard/google/brya/variants/redrix/include/variant/ec.h A src/mainboard/google/brya/variants/redrix/include/variant/gpio.h A src/mainboard/google/brya/variants/redrix/memory/Makefile.inc A src/mainboard/google/brya/variants/redrix/memory/dram_id.generated.txt A src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt A src/mainboard/google/brya/variants/redrix/overridetree.cb 8 files changed, 45 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 7f38851..814b782 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -77,12 +77,14 @@ default "Brya" if BOARD_GOOGLE_BRYA0 default "Primus" if BOARD_GOOGLE_PRIMUS default "Gimble" if BOARD_GOOGLE_GIMBLE + default "Redrix" if BOARD_GOOGLE_REDRIX config VARIANT_DIR string default "brya0" if BOARD_GOOGLE_BRYA0 default "primus" if BOARD_GOOGLE_PRIMUS default "gimble" if BOARD_GOOGLE_GIMBLE + default "redrix" if BOARD_GOOGLE_REDRIX config DIMM_SPD_SIZE int diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index f63e46f..15e3bd0 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -20,3 +20,7 @@ select BASEBOARD_BRYA_LAPTOP select CHROMEOS_DSM_CALIB if CHROMEOS select DRIVERS_I2C_MAX98390 + +config BOARD_GOOGLE_REDRIX + bool "-> Redrix" + select BOARD_GOOGLE_BASEBOARD_BRYA diff --git a/src/mainboard/google/brya/variants/redrix/include/variant/ec.h b/src/mainboard/google/brya/variants/redrix/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/brya/variants/redrix/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/brya/variants/redrix/include/variant/gpio.h b/src/mainboard/google/brya/variants/redrix/include/variant/gpio.h new file mode 100644 index 0000000..c4fe342 --- /dev/null +++ b/src/mainboard/google/brya/variants/redrix/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/brya/variants/redrix/memory/Makefile.inc b/src/mainboard/google/brya/variants/redrix/memory/Makefile.inc new file mode 100644 index 0000000..b0ca222 --- /dev/null +++ b/src/mainboard/google/brya/variants/redrix/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! +## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder.spd.hex diff --git a/src/mainboard/google/brya/variants/redrix/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/redrix/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/brya/variants/redrix/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt new file mode 100644 index 0000000..9cff262 --- /dev/null +++ b/src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/lp4x. +# See util/spd_tools/lp4x/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb new file mode 100644 index 0000000..4f2c04a --- /dev/null +++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/alderlake + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/55883 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4cfa0bd84e1ba9f8140f95d18a6da960da8124ad Gerrit-Change-Number: 55883 Gerrit-PatchSet: 3 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/../car: Calculate SF Mask#1 based on MSR 0xc87
by Subrata Banik (Code Review) 08 Jul '21

08 Jul '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Nick Vaccaro, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51374 ) Change subject: soc/intel/common/../car: Calculate SF Mask#1 based on MSR 0xc87 ...................................................................... Patch Set 9: (2 comments) File src/soc/intel/common/block/cpu/car/cache_as_ram.S: https://review.coreboot.org/c/coreboot/+/51374/comment/54922833_5bd5a860 PS8, Line 527: 2. Set SF_MASK_1 = ((1 << SFWayCnt) - 1) - ((1 << data_ways) - 1) > This can be simplified further to remove 1 subtraction: […] Ack https://review.coreboot.org/c/coreboot/+/51374/comment/1dd48e05_eab72465 PS8, Line 532: mov %al, %cl : mov $0x01, %eax : shl %cl, %eax : subl $0x01, %eax /* contains ((1 << SFWayCnt) - 1) */ : mov %bl, %cl : mov $0x01, %ebx : shl %cl, %ebx : subl $0x01, %ebx /* contains ((1 << data_ways) - 1) */ : sub %ebx, %eax /* contains SF mask */ > Oops, yes, I mixed up the order of registers in that line, you figured out what I meant 😉 Right, wi […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/51374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd0b7e1a90cad4a4837adf6067fe8301dcd0a941 Gerrit-Change-Number: 51374 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Thu, 08 Jul 2021 15:51:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya0: Update the FIVR configurations
by Felix Held (Code Review) 08 Jul '21

08 Jul '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55704 ) Change subject: mb/google/brya0: Update the FIVR configurations ...................................................................... mb/google/brya0: Update the FIVR configurations This patch sets the disable the external voltage rails since brya board doesn't have V1p05 and Vnn bypass rails implemented. Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Change-Id: I1c4fdb38c5c56798935b2c6627a75c3f1ac9fbef Reviewed-on: https://review.coreboot.org/c/coreboot/+/55704 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/brya0/overridetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index 9ef7478..9584b27 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -36,6 +36,12 @@ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port + # FIVR configurations for brya are disabled since the board doesn't have V1p05 and Vnn + # bypass rails implemented. + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + }" + device domain 0 on device ref dtt on chip drivers/intel/dptf -- To view, visit https://review.coreboot.org/c/coreboot/+/55704 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c4fdb38c5c56798935b2c6627a75c3f1ac9fbef Gerrit-Change-Number: 55704 Gerrit-PatchSet: 6 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: vagdevi.p(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: Documentation/drivers/dptf: Add oem variables support
by Felix Held (Code Review) 08 Jul '21

08 Jul '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55846 ) Change subject: Documentation/drivers/dptf: Add oem variables support ...................................................................... Documentation/drivers/dptf: Add oem variables support Add oem variables information with usage example. BRANCH=None BUG=b:187253038 TEST=Built and tested on dedede board Change-Id: I45db17f6ee3328da28f985c6854d65a430c9c61b Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55846 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M Documentation/drivers/dptf.md 1 file changed, 16 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/Documentation/drivers/dptf.md b/Documentation/drivers/dptf.md index 327d686..1e5674c 100644 --- a/Documentation/drivers/dptf.md +++ b/Documentation/drivers/dptf.md @@ -311,3 +311,19 @@ 1) Hysteresis - The amount of hysteresis implemented in either circuitry or the firmware that reads the temperature sensor (in degrees C). 2) Name - This name is applied to the _STR property of the sensor + +## OEM Variables +Platform vendors can define an array of OEM-specific values as OEM variables +to be used under DPTF policy. There are total six OEM variables available. +These can be used in AP policy for more specific actions. These OEM variables +can be defined as below mentioned example and can be used any variable between +[0], [1],...,[5]. Platform vendors can enable and use this for specific platform +by defining OEM variables macro under board variant. + +Example: +```C +register "oem_data.oem_variables" = "{ + [1] = 0x6, + [3] = 0x1 +}" +``` -- To view, visit https://review.coreboot.org/c/coreboot/+/55846 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45db17f6ee3328da28f985c6854d65a430c9c61b Gerrit-Change-Number: 55846 Gerrit-PatchSet: 4 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: supermicro/x11-lga1151-series: Remove SkipExtGfxScan = 1
by Jan Tatje (Code Review) 08 Jul '21

08 Jul '21

Attention is currently required from: Michael Niewöhner. Jan Tatje has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56071 ) Change subject: supermicro/x11-lga1151-series: Remove SkipExtGfxScan = 1 ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > Sorry, I meant testing that option without your patch here :) Without the change and CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y set it also works, I hadn't tried that before because I did not expect it to make a difference. Though CONFIG_VGA_TEXT_FRAMEBUFFER=y does not work without the change, there are no errors or warnings, but there is no video output. Both work with the change applied. -- To view, visit https://review.coreboot.org/c/coreboot/+/56071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41249112c65927b61ca5f791f8eb8c3f3d204fce Gerrit-Change-Number: 56071 Gerrit-PatchSet: 3 Gerrit-Owner: Jan Tatje <jan(a)jnt.io> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Thu, 08 Jul 2021 15:49:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jan Tatje <jan(a)jnt.io> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/tglrvp: Update Power Limit2 minimum value
by Felix Held (Code Review) 08 Jul '21

08 Jul '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56085 ) Change subject: mb/intel/tglrvp: Update Power Limit2 minimum value ...................................................................... mb/intel/tglrvp: Update Power Limit2 minimum value Update Power Limit2 (PL2) minimum value to the same as maximum value. DTT does not throttle PL2, so this minimum value change here does not impact any existing behavior on the system. BUG=None BRANCH=None TEST=Build and test on tglrvp system Change-Id: I6bbbfa8e43a241df721b91425294983c1d561f2c Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56085 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index ce7c3d9..4e3d2e79 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -191,7 +191,7 @@ .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200,}" register "controls.power_limits.pl2" = "{ - .min_power = 15000, + .min_power = 60000, .max_power = 60000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 47ac01e..7f7e16b 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -195,7 +195,7 @@ .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200,}" register "controls.power_limits.pl2" = "{ - .min_power = 9000, + .min_power = 40000, .max_power = 40000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, -- To view, visit https://review.coreboot.org/c/coreboot/+/56085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6bbbfa8e43a241df721b91425294983c1d561f2c Gerrit-Change-Number: 56085 Gerrit-PatchSet: 2 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common: Use SPR for backing up data way and eviction mask
by Subrata Banik (Code Review) 08 Jul '21

08 Jul '21

Attention is currently required from: Patrick Rudolph. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56161 ) Change subject: soc/intel/common: Use SPR for backing up data way and eviction mask ...................................................................... soc/intel/common: Use SPR for backing up data way and eviction mask This patch replaces the usage of GPR (General Purpose Registers) like ECX and EBX for backing up data way and non-eviction mask with SPR (Special Purpose Registers) EDI and ESI. Purpose of this change is to ensure the safety while developers might use ECX often while doing rdmsr/wrmsr rather than making use of EDI. TEST=Able to boot JSL and TGL platform without any hang using eNEM. Change-Id: I12e0cb7bb050e4f7b17ecf30108db335d1d82ab7 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/cpu/car/cache_as_ram.S 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/56161/1 diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 74957ab..784e8ca 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -514,15 +514,15 @@ subl $0x01, %eax set_eviction_mask: - mov %ebx, %ecx /* back up number of ways */ - mov %eax, %ebx /* back up the non-eviction mask*/ + mov %ebx, %edi /* back up number of ways */ + mov %eax, %esi /* back up the non-eviction mask*/ #if CONFIG(CAR_HAS_SF_MASKS) - mov %ecx, %edi /* use number of ways to prepare SF mask */ /* * SF mask is programmed with the double number of bits than * the number of ways */ mov $0x01, %eax + mov %edi, %ecx shl %cl, %eax shl %cl, %eax subl $0x01, %eax /* contains SF mask */ @@ -533,7 +533,6 @@ movl $IA32_CR_SF_QOS_MASK_1, %ecx xorl %edx, %edx wrmsr - mov %edi, %ecx /* restore number of ways */ #endif /* * Program MSR 0xC91 IA32_L3_MASK_1 @@ -542,10 +541,11 @@ * - If this bit is '1' - the way is not protected from eviction */ mov $0x1, %eax + mov %edi, %ecx shl %cl, %eax subl $0x01, %eax mov %eax, %ecx - mov %ebx, %eax + mov %esi, %eax xor $~0, %eax /* invert 32 bits */ and %ecx, %eax @@ -558,7 +558,7 @@ * - If this bit is '0' - the way is protected from eviction * - If this bit is '1' - the way is not protected from eviction */ - mov %ebx, %eax + mov %esi, %eax movl $IA32_L3_MASK_2, %ecx xorl %edx, %edx wrmsr -- To view, visit https://review.coreboot.org/c/coreboot/+/56161 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12e0cb7bb050e4f7b17ecf30108db335d1d82ab7 Gerrit-Change-Number: 56161 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Avoid NULL pointer deference
by Felix Held (Code Review) 08 Jul '21

08 Jul '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56123 ) Change subject: soc/intel/alderlake: Avoid NULL pointer deference ...................................................................... soc/intel/alderlake: Avoid NULL pointer deference Coverity detects dereference pointers req and res that are NULL when calling the pmc_send_ipc_cmd function. This change prevents NULL pointers dereference. Found-by: Coverity CID 1458077, 1458078 TEST=None Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: I151157e7a9a90c43075f431933ac44f29fd25127 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56123 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/alderlake/crashlog.c 1 file changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/crashlog.c b/src/soc/intel/alderlake/crashlog.c index c1eeedf..9435aa0 100644 --- a/src/soc/intel/alderlake/crashlog.c +++ b/src/soc/intel/alderlake/crashlog.c @@ -32,8 +32,8 @@ { u32 tmp_bar_addr = 0, desc_table_addr = 0; - const struct pmc_ipc_buffer *req = { 0 }; - struct pmc_ipc_buffer *res = NULL; + const struct pmc_ipc_buffer req = { 0 }; + struct pmc_ipc_buffer res; uint32_t cmd_reg; int r; @@ -42,13 +42,13 @@ PMC_IPC_CMD_SIZE_SHIFT); printk(BIOS_DEBUG, "cmd_reg from pmc_make_ipc_cmd %d\n", cmd_reg); - r = pmc_send_ipc_cmd(cmd_reg, req, res); + r = pmc_send_ipc_cmd(cmd_reg, &req, &res); if (r < 0) { printk(BIOS_ERR, "pmc_send_ipc_cmd failed in %s\n", __func__); return false; } - discovery_buf.val_64_bits = ((u64)res->buf[1] << 32) | res->buf[0]; + discovery_buf.val_64_bits = ((u64)res.buf[1] << 32) | res.buf[0]; if (discovery_buf.bits.supported != 1) { -- To view, visit https://review.coreboot.org/c/coreboot/+/56123 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I151157e7a9a90c43075f431933ac44f29fd25127 Gerrit-Change-Number: 56123 Gerrit-PatchSet: 2 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <angel.pons(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Create eNEM Kconfig for Alder Lake
by Subrata Banik (Code Review) 08 Jul '21

08 Jul '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Patrick Rudolph, EricR Lai. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Patrick Rudolph, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56090 to look at the new patch set (#3). Change subject: soc/intel/alderlake: Create eNEM Kconfig for Alder Lake ...................................................................... soc/intel/alderlake: Create eNEM Kconfig for Alder Lake Alder Lake SoC specific Kconfig that internally selects all eNEM related Kconfig. CONFIG_ALDERLAKE_CAR_ENHANCED_NEM will get autoselected if platform doesn't have INTEL_CAR_NEM Kconfig selected explicitly. BUG=b:168820083 TEST=Verified CONFIG_INTEL_CAR_NEM is still enable. Change-Id: Ife1c7d2036cece4598275dfc26ed138fb46bd881 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/alderlake/Kconfig 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/56090/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/56090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife1c7d2036cece4598275dfc26ed138fb46bd881 Gerrit-Change-Number: 56090 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/../car: Calculate SF Mask#1 based on MSR 0xc87
by Subrata Banik (Code Review) 08 Jul '21

08 Jul '21

Attention is currently required from: Furquan Shaikh, Nick Vaccaro, EricR Lai. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Patrick Rudolph, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51374 to look at the new patch set (#9). Change subject: soc/intel/common/../car: Calculate SF Mask#1 based on MSR 0xc87 ...................................................................... soc/intel/common/../car: Calculate SF Mask#1 based on MSR 0xc87 MSR IA_SF_QOS_INFO (0xc87) has been introduced since TGL and is used to find out the NUM_SNOOP_FILTER_WAYS. Bit[5:0] of MSR 0xc87 indicates the maximum numbers of bits that may be set in any of the SF MASK register. Hence, this patch calculates SF way count to program SF Mask#1 using below logic: 1. Calculate SFWayCnt = (MSR 0xC87) & 0x3f 2. Set SF_MASK_1 = ((1 << (SFWayCnt - data_ways)) - 1) << data_ways) Change-Id: Ifd0b7e1a90cad4a4837adf6067fe8301dcd0a941 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/include/cpu/x86/msr.h M src/soc/intel/common/block/cpu/car/cache_as_ram.S 2 files changed, 12 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/51374/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/51374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd0b7e1a90cad4a4837adf6067fe8301dcd0a941 Gerrit-Change-Number: 51374 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit July 2021