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Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56158
to look at the new patch set (#2).
Change subject: vc/mediatek/mt8195: add FOR_COREBOOT define
......................................................................
vc/mediatek/mt8195: add FOR_COREBOOT define
The CONFIG(CHROMEOS) in DRAM calibration code was incorrectly used to
identify implementations for Chromebooks (in coreboot) so we want to
introduce a new flag FOR_COREBOOT to prevent confusion.
Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com>
Change-Id: Ic7a6e24f41c1fda167b5d6bb2d8a2c5c79dda8de
---
M src/vendorcode/mediatek/mt8195/Makefile.inc
M src/vendorcode/mediatek/mt8195/dramc/dramc_top.c
2 files changed, 13 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/56158/2
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Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52758 )
Change subject: drivers/intel/gma: Support IGD Opregion 2.1
......................................................................
Patch Set 14:
(2 comments)
File src/drivers/intel/gma/opregion.c:
https://review.coreboot.org/c/coreboot/+/52758/comment/7f3f5fab_27215da5
PS13, Line 277:
> knowing that we have only 2_1 and 2_0. […]
Agreed. Done
https://review.coreboot.org/c/coreboot/+/52758/comment/1d0a32e5_9fd71a2c
PS13, Line 358: Left-shift version field to accommodate Intel Windows driver quirk
: * when not using a VBIOS.
> I think this comment can be dropped? The left shift is required as per 2.0+ spec.
I think the left shift is always needed. Earlier the Major version was shifted by 24.
As now we have a minor version too, it needs a shift by 16.
Bits [31:24] - Major Version Number
BCD Integer representing the major version of the OpRegion
Bits [23:16] - Minor Version Number
BCD Integer representing the minor version of the OpRegion
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Attention is currently required from: Bora Guvendik, Furquan Shaikh, Selma Bensaid, Maulik V Vaghela, Tim Wawrzynczak, Paul Menzel, Meera Ravindranath, Angel Pons, Patrick Rudolph.
Hello Bora Guvendik, build bot (Jenkins), Furquan Shaikh, Selma Bensaid, Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#19).
Change subject: mb/adlrvp: Fix DDR5 Boot issue
......................................................................
mb/adlrvp: Fix DDR5 Boot issue
The coreboot SMBus driver requires additional changes to accomodate
the DDR5 EEPROM read which has resulted in a broken code flow for boot.
This CL serves as a temp WA to let FSP perform the SPD read for DDR5
and pass SPD addresses to FSP UPD array.
BUG=b:180458099
TEST=Build and boot DDR5 adlrvp to OS
Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com>
Change-Id: I9998bfcd12b81c11fcc9f791da2a27d3c788e48a
---
M src/soc/intel/alderlake/meminit.c
1 file changed, 29 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/50996/19
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Attention is currently required from: Rex-BC Chen, Yu-Ping Wu.
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56158 )
Change subject: vc/mediatek/mt8195: add FOR_COREBOOT define
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> I think you should also change the `#elif CONFIG(CHROMEOS)` to `#elif defined(FOR_COREBOOT)` in this […]
And add description:
The CONFIG(CHROMEOS) in DRAM calibration code was incorrectly used to
identify implementations for Chromebooks (in coreboot) so we want to
introduce a new flag FOR_COREBOOT to prevent confusion.
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