coreboot-gerrit July 2021

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Change in coreboot[master]: Revert "drivers/intel/fsp2_0: use FSP to allocate APEI BERT memory re...
by Jonathan Zhang (Code Review) 08 Jul '21

08 Jul '21

Attention is currently required from: Raul Rangel, Rocky Phagura, Tim Wawrzynczak, Subrata Banik, Andrey Petrov, Patrick Rudolph, Felix Held. Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56163 ) Change subject: Revert "drivers/intel/fsp2_0: use FSP to allocate APEI BERT memory region" ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/56163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ca095ca327cbf925edb59b89fff42ff9f96de5d Gerrit-Change-Number: 56163 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Rocky Phagura <rphagura(a)fb.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 08 Jul 2021 16:57:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Revert "drivers/intel/fsp2_0: use FSP to allocate APEI BERT memory re...
by Felix Held (Code Review) 08 Jul '21

08 Jul '21

Attention is currently required from: Raul Rangel, Jonathan Zhang, Tim Wawrzynczak, Subrata Banik, Andrey Petrov, Patrick Rudolph. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56163 ) Change subject: Revert "drivers/intel/fsp2_0: use FSP to allocate APEI BERT memory region" ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/56163/comment/d6737e71_34d83328 PS1, Line 28: TEST=Behavior of the BERT code doesn't change on Mandolin would be good if this gets tested on an Intel system with BERT support as well to make sure that this patch won't cause regressions -- To view, visit https://review.coreboot.org/c/coreboot/+/56163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ca095ca327cbf925edb59b89fff42ff9f96de5d Gerrit-Change-Number: 56163 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 08 Jul 2021 16:39:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Revert "drivers/intel/fsp2_0: use FSP to allocate APEI BERT memory re...
by Felix Held (Code Review) 08 Jul '21

08 Jul '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56163 ) Change subject: Revert "drivers/intel/fsp2_0: use FSP to allocate APEI BERT memory region" ...................................................................... Revert "drivers/intel/fsp2_0: use FSP to allocate APEI BERT memory region" This reverts commit ce0e2a014009390c4527e064efb59260ef4d3a3b which was originally introduced as a workaround for the bug that the Linux kernel doesn't know what to do with type 16 memory region in the e820 table where CBMEM resides and disallowed accessing it. After depthcharge was patched to mark the type 16 region as a normal reserved region, the Linux kernel now can access the BERT region and print BERT errors. When SeaBIOS was used as payload it already marked the memory region correctly, so it already worked in that case. After commit 8c3a8df1021b8a2789c2a285557401837f9fc2b8 that removed the usage of the BERT memory region reserved by the FSP driver by the AMD Picasso and Cezanne SoCs and made them use CBMEM for the BERT region, no other SoC code uses this functionality. The Intel Alderlake and Tigerlake SoCs put the BERT region in CBMEM and never used this reserved memory region and the change for the Intel server CPU to use this was abandoned and never landed in upstream coreboot. AMD Stoneyridge is the only other SoC/chipset that selects ACPI_BERT, but since it doesn't select or use the FSP driver, it also won't be affected by this change. TEST=Behavior of the BERT code doesn't change on Mandolin Change-Id: I6ca095ca327cbf925edb59b89fff42ff9f96de5d Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/drivers/intel/fsp2_0/cbmem.c M src/drivers/intel/fsp2_0/hob_verify.c M src/drivers/intel/fsp2_0/memory_init.c 3 files changed, 2 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/56163/1 diff --git a/src/drivers/intel/fsp2_0/cbmem.c b/src/drivers/intel/fsp2_0/cbmem.c index 5388b89..0efb462 100644 --- a/src/drivers/intel/fsp2_0/cbmem.c +++ b/src/drivers/intel/fsp2_0/cbmem.c @@ -6,14 +6,7 @@ void *cbmem_top_chipset(void) { struct range_entry tolum; - uint8_t *tolum_base; fsp_find_bootloader_tolum(&tolum); - tolum_base = (uint8_t *)(uintptr_t)range_entry_base(&tolum); - - /* - * The TOLUM range may have other memory regions (such as APEI - * BERT region on top of CBMEM (IMD root and IMD small) region. - */ - return tolum_base + cbmem_overhead_size(); + return (void *)(uintptr_t)range_entry_end(&tolum); } diff --git a/src/drivers/intel/fsp2_0/hob_verify.c b/src/drivers/intel/fsp2_0/hob_verify.c index 9bfb0f1..ec526e8 100644 --- a/src/drivers/intel/fsp2_0/hob_verify.c +++ b/src/drivers/intel/fsp2_0/hob_verify.c @@ -43,16 +43,9 @@ die("Space between FSP reserved region and BIOS TOLUM!\n"); } - if (!CONFIG(ACPI_BERT) && range_entry_end(&tolum) != (uintptr_t)cbmem_top()) { + if (range_entry_end(&tolum) != (uintptr_t)cbmem_top()) { printk(BIOS_CRIT, "TOLUM end: 0x%08llx != %p: cbmem_top\n", range_entry_end(&tolum), cbmem_top()); die("Space between cbmem_top and BIOS TOLUM!\n"); } - - if (CONFIG(ACPI_BERT) && - range_entry_end(&tolum) != (uintptr_t)cbmem_top() + CONFIG_ACPI_BERT_SIZE) { - printk(BIOS_CRIT, "TOLUM end: 0x%08llx != %p: cbmem_top + 0x%x: BERT\n", - range_entry_end(&tolum), cbmem_top(), CONFIG_ACPI_BERT_SIZE); - die("Space between cbmem_top and APEI BERT!\n"); - } } diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index b12229d..0c9fe97 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -266,21 +266,6 @@ /* Reserve enough memory under TOLUD to save CBMEM header */ arch_upd->BootLoaderTolumSize = cbmem_overhead_size(); - /* - * If ACPI APEI BERT region size is defined, reserve memory for it. - * +------------------------+ range_entry_top(tolum) - * | Other reserved regions | - * | APEI BERT region | - * +------------------------+ cbmem_top() - * | CBMEM IMD ROOT | - * | CBMEM IMD SMALL | - * +------------------------+ range_entry_base(tolum), TOLUM - * | CBMEM FSP MEMORY | - * | Other CBMEM regions... | - */ - if (CONFIG(ACPI_BERT)) - arch_upd->BootLoaderTolumSize += CONFIG_ACPI_BERT_SIZE; - /* Fill common settings on behalf of chipset. */ if (fsp_fill_common_arch_params(arch_upd, s3wake, fsp_version, memmap) != CB_SUCCESS) -- To view, visit https://review.coreboot.org/c/coreboot/+/56163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ca095ca327cbf925edb59b89fff42ff9f96de5d Gerrit-Change-Number: 56163 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: grunt/treeya: add Realtek ALC5682 codec support
by Kevin Chang (Code Review) 08 Jul '21

08 Jul '21

Attention is currently required from: Daniel Kurtz, Martin Roth, Paul Menzel. Kevin Chang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56100 ) Change subject: grunt/treeya: add Realtek ALC5682 codec support ...................................................................... Patch Set 4: (4 comments) File src/mainboard/google/kahlee/variants/treeya/audio.c: https://review.coreboot.org/c/coreboot/+/56100/comment/1250fe28_48cfea6f PS2, Line 22: 0xfedc2000 > src/soc/amd/stoneyridge/include/soc/iomap. […] Update in patchset 4. https://review.coreboot.org/c/coreboot/+/56100/comment/64e52573_18bbe8fa PS2, Line 24: } > Can one of the checks be moved into the do-while condition? […] Hi Paul Update in patchset 4, Is this what you want to change? https://review.coreboot.org/c/coreboot/+/56100/comment/af167c61_25a42b48 PS2, Line 27: return; > Can’t you return already above? Maybe also print an error? Hi Paul Update in patchset 4, Is this what you want to change? https://review.coreboot.org/c/coreboot/+/56100/comment/7924464e_eaa9fbf0 PS2, Line 32: 0x1a > As long as we're updating things, we could turn this into a #define. […] Update in patchset 4. -- To view, visit https://review.coreboot.org/c/coreboot/+/56100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49c673fd944b2c2a79c4283eee941a16596ba7fa Gerrit-Change-Number: 56100 Gerrit-PatchSet: 4 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alec Wang <alec.wang(a)lcfc.corp-partner.google.com> Gerrit-CC: Allen Cheng <allen.cheng(a)lcfc.corp-partner.google.com> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Daniel Kurtz <djkurtz(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 08 Jul 2021 16:27:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: grunt/treeya: add Realtek ALC5682 codec support
by Kevin Chang (Code Review) 08 Jul '21

08 Jul '21

Attention is currently required from: Daniel Kurtz, Kevin Chang, Paul Menzel. Hello Daniel Kurtz, build bot (Jenkins), Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56100 to look at the new patch set (#4). Change subject: grunt/treeya: add Realtek ALC5682 codec support ...................................................................... grunt/treeya: add Realtek ALC5682 codec support ALC5682 i2c address: 0x1A BUG=b:185972050 BRANCH=master TEST=emerge-grunt coreboot Signed-off-by: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Change-Id: I49c673fd944b2c2a79c4283eee941a16596ba7fa --- M src/mainboard/google/kahlee/variants/treeya/Makefile.inc A src/mainboard/google/kahlee/variants/treeya/audio.c M src/mainboard/google/kahlee/variants/treeya/devicetree.cb A src/mainboard/google/kahlee/variants/treeya/include/variant/sku.h M src/soc/amd/stoneyridge/include/soc/iomap.h 5 files changed, 87 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/56100/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/56100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49c673fd944b2c2a79c4283eee941a16596ba7fa Gerrit-Change-Number: 56100 Gerrit-PatchSet: 4 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alec Wang <alec.wang(a)lcfc.corp-partner.google.com> Gerrit-CC: Allen Cheng <allen.cheng(a)lcfc.corp-partner.google.com> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Daniel Kurtz <djkurtz(a)chromium.org> Gerrit-Attention: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: grunt/treeya: add Realtek ALC5682 codec support
by Kevin Chang (Code Review) 08 Jul '21

08 Jul '21

Attention is currently required from: Daniel Kurtz, Kevin Chang, Paul Menzel. Hello Daniel Kurtz, build bot (Jenkins), Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56100 to look at the new patch set (#3). Change subject: grunt/treeya: add Realtek ALC5682 codec support ...................................................................... grunt/treeya: add Realtek ALC5682 codec support ALC5682 i2c address: 0x1A BUG=b:185972050 BRANCH=master TEST=emerge-grunt coreboot Signed-off-by: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Change-Id: I49c673fd944b2c2a79c4283eee941a16596ba7fa --- M src/mainboard/google/kahlee/variants/treeya/Makefile.inc A src/mainboard/google/kahlee/variants/treeya/audio.c M src/mainboard/google/kahlee/variants/treeya/devicetree.cb A src/mainboard/google/kahlee/variants/treeya/include/variant/sku.h M src/soc/amd/stoneyridge/include/soc/iomap.h 5 files changed, 87 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/56100/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/56100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49c673fd944b2c2a79c4283eee941a16596ba7fa Gerrit-Change-Number: 56100 Gerrit-PatchSet: 3 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alec Wang <alec.wang(a)lcfc.corp-partner.google.com> Gerrit-CC: Allen Cheng <allen.cheng(a)lcfc.corp-partner.google.com> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Daniel Kurtz <djkurtz(a)chromium.org> Gerrit-Attention: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: amdfwtool: Use relative address for EFS gen2
by Felix Held (Code Review) 08 Jul '21

08 Jul '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55211 ) Change subject: amdfwtool: Use relative address for EFS gen2 ...................................................................... amdfwtool: Use relative address for EFS gen2 The second generation EFS (offset 0x24[0]=0) uses "binary relative" offsets and not "x86 physical MMIO address" like gen1. Chips like Cezanne can run in both cases, so no problem comes up so far. BUG=b:188754219 Test=Majolica (Cezanne) Change-Id: I3a54f8ce5004915a7fa407dcd7d59a64d88aad0d Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55211 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M util/amdfwtool/amdfwtool.c 1 file changed, 9 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Felix Held: Looks good to me, but someone else must approve diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 1e75278..9299aec 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -343,11 +343,12 @@ typedef struct _context { char *rom; /* target buffer, size of flash device */ uint32_t rom_size; /* size of flash device */ + uint32_t abs_address; /* produce absolute or relative address */ uint32_t current; /* pointer within flash & proxy buffer */ } context; #define RUN_BASE(ctx) (0xFFFFFFFF - (ctx).rom_size + 1) -#define RUN_OFFSET(ctx, offset) (RUN_BASE(ctx) + (offset)) +#define RUN_OFFSET(ctx, offset) ((ctx).abs_address ? RUN_BASE(ctx) + (offset) : (offset)) #define RUN_CURRENT(ctx) RUN_OFFSET((ctx), (ctx).current) #define BUFF_OFFSET(ctx, offset) ((void *)((ctx).rom + (offset))) #define BUFF_CURRENT(ctx) BUFF_OFFSET((ctx), (ctx).current) @@ -1536,8 +1537,6 @@ romsig_offset = ctx.current = dir_location - rom_base_address; else romsig_offset = ctx.current = AMD_ROMSIG_OFFSET; - printf(" AMDFWTOOL Using firmware directory location of 0x%08x\n", - RUN_CURRENT(ctx)); amd_romsig = BUFF_OFFSET(ctx, romsig_offset); amd_romsig->signature = EMBEDDED_FW_SIGNATURE; @@ -1556,6 +1555,13 @@ fprintf(stderr, "WARNING: No SOC name specified.\n"); } + if (amd_romsig->efs_gen.gen == EFS_SECOND_GEN) + ctx.abs_address = 0; + else + ctx.abs_address = 1; + printf(" AMDFWTOOL Using firmware directory location of %s address: 0x%08x\n", + ctx.abs_address == 1 ? "absolute" : "relative", RUN_CURRENT(ctx)); + integrate_firmwares(&ctx, amd_romsig, amd_fw_table); ctx.current = ALIGN(ctx.current, 0x10000U); /* TODO: is it necessary? */ -- To view, visit https://review.coreboot.org/c/coreboot/+/55211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a54f8ce5004915a7fa407dcd7d59a64d88aad0d Gerrit-Change-Number: 55211 Gerrit-PatchSet: 9 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: amdfwtool: Use relative address for EFS gen2
by Felix Held (Code Review) 08 Jul '21

08 Jul '21

Attention is currently required from: Bao Zheng, Jason Glenesk, Raul Rangel, Paul Menzel, Zheng Bao. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55211 ) Change subject: amdfwtool: Use relative address for EFS gen2 ...................................................................... Patch Set 8: Code-Review+1 (1 comment) Patchset: PS8: looks good to me, but can't check with the specification right now -- To view, visit https://review.coreboot.org/c/coreboot/+/55211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a54f8ce5004915a7fa407dcd7d59a64d88aad0d Gerrit-Change-Number: 55211 Gerrit-PatchSet: 8 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Thu, 08 Jul 2021 15:57:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/var/voema: Remove stop delay time for ELAN TS
by Felix Held (Code Review) 08 Jul '21

08 Jul '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56087 ) Change subject: mb/google/volteer/var/voema: Remove stop delay time for ELAN TS ...................................................................... mb/google/volteer/var/voema: Remove stop delay time for ELAN TS Remove register "generic.stop_delay_ms" and measure data, it still can meet elan touchscreen specification that reset pull high to I2C time > 150ms (T3 > 150ms). BUG=b:185308246 TEST=Measure the T3 delay time is greater than 150ms on voema Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: Id326fd4d9d71eef171580b1c6001505e698b40a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56087 Reviewed-by: YH Lin <yueherngl(a)google.com> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/volteer/variants/voema/overridetree.cb 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified YH Lin: Looks good to me, but someone else must approve Nick Vaccaro: Looks good to me, approved diff --git a/src/mainboard/google/volteer/variants/voema/overridetree.cb b/src/mainboard/google/volteer/variants/voema/overridetree.cb index fcec5eb..745ed51 100644 --- a/src/mainboard/google/volteer/variants/voema/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voema/overridetree.cb @@ -71,7 +71,6 @@ register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F16)" register "generic.enable_delay_ms" = "10" register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E3)" - register "generic.stop_delay_ms" = "150" register "generic.has_power_resource" = "1" register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" -- To view, visit https://review.coreboot.org/c/coreboot/+/56087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id326fd4d9d71eef171580b1c6001505e698b40a3 Gerrit-Change-Number: 56087 Gerrit-PatchSet: 3 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/redrix: Generate SPD ID for supported parts
by Felix Held (Code Review) 08 Jul '21

08 Jul '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55885 ) Change subject: mb/google/brya/var/redrix: Generate SPD ID for supported parts ...................................................................... mb/google/brya/var/redrix: Generate SPD ID for supported parts Add supported memory parts in mem_parts_used.txt, and generate SPD id for these parts. MT53E1G32D2NP-046 WT:A H9HCNNNBKMMLXR-NEE K4U6E3S4AA-MGCR MT53E512M32D2NP-046 WT:E H9HCNNNCPMMLXR-NEE K4UBE3D4AA-MGCR H9HCNNNFAMMLXR-NEE MT53E2G32D4NQ-046 WT:A BUG=b:190818098, b:190874372, b:192052098 TEST=build Change-Id: I62ee401e43bef22b4b09f41ea59bbdbc479f293c Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55885 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/redrix/memory/Makefile.inc M src/mainboard/google/brya/variants/redrix/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt 3 files changed, 22 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/redrix/memory/Makefile.inc b/src/mainboard/google/brya/variants/redrix/memory/Makefile.inc index b0ca222..8fb0ea1 100644 --- a/src/mainboard/google/brya/variants/redrix/memory/Makefile.inc +++ b/src/mainboard/google/brya/variants/redrix/memory/Makefile.inc @@ -1,5 +1,9 @@ ## SPDX-License-Identifier: GPL-2.0-or-later ## This is an auto-generated file. Do not edit!! -## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. -SPD_SOURCES = placeholder.spd.hex +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-4.hex # ID = 0(0b0000) Parts = MT53E1G32D2NP-046 WT:A +SPD_SOURCES += lp4x-spd-1.hex # ID = 1(0b0001) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D2NP-046 WT:E +SPD_SOURCES += lp4x-spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR +SPD_SOURCES += lp4x-spd-2.hex # ID = 3(0b0011) Parts = H9HCNNNFAMMLXR-NEE +SPD_SOURCES += lp4x-spd-7.hex # ID = 4(0b0100) Parts = MT53E2G32D4NQ-046 WT:A diff --git a/src/mainboard/google/brya/variants/redrix/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/redrix/memory/dram_id.generated.txt index fa24790..50b2c2a 100644 --- a/src/mainboard/google/brya/variants/redrix/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/redrix/memory/dram_id.generated.txt @@ -1 +1,9 @@ DRAM Part Name ID to assign +MT53E1G32D2NP-046 WT:A 0 (0000) +H9HCNNNBKMMLXR-NEE 1 (0001) +K4U6E3S4AA-MGCR 1 (0001) +MT53E512M32D2NP-046 WT:E 1 (0001) +H9HCNNNCPMMLXR-NEE 2 (0010) +K4UBE3D4AA-MGCR 2 (0010) +H9HCNNNFAMMLXR-NEE 3 (0011) +MT53E2G32D4NQ-046 WT:A 4 (0100) diff --git a/src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt index 9cff262..eb1c176 100644 --- a/src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt @@ -1,11 +1,8 @@ -# This is a CSV file containing a list of memory parts used by this variant. -# One part per line with an optional fixed ID in column 2. -# Only include a fixed ID if it is required for legacy reasons! -# Generated IDs are dependent on the order of parts in this file, -# so new parts must always be added at the end of the file! -# -# Generate an updated Makefile.inc and dram_id.generated.txt by running the -# gen_part_id tool from util/spd_tools/lp4x. -# See util/spd_tools/lp4x/README.md for more details and instructions. - -# Part Name +MT53E1G32D2NP-046 WT:A +H9HCNNNBKMMLXR-NEE +K4U6E3S4AA-MGCR +MT53E512M32D2NP-046 WT:E +H9HCNNNCPMMLXR-NEE +K4UBE3D4AA-MGCR +H9HCNNNFAMMLXR-NEE +MT53E2G32D4NQ-046 WT:A -- To view, visit https://review.coreboot.org/c/coreboot/+/55885 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62ee401e43bef22b4b09f41ea59bbdbc479f293c Gerrit-Change-Number: 55885 Gerrit-PatchSet: 7 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit July 2021