coreboot-gerrit July 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: grunt/treeya: add Realtek ALC5682 codec support
by Martin Roth (Code Review) 08 Jul '21

08 Jul '21

Attention is currently required from: Daniel Kurtz, Kevin Chang, Paul Menzel. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56100 ) Change subject: grunt/treeya: add Realtek ALC5682 codec support ...................................................................... Patch Set 4: (1 comment) File src/mainboard/google/kahlee/variants/treeya/audio.c: https://review.coreboot.org/c/coreboot/+/56100/comment/716fca95_041a06e6 PS4, Line 21: if (mmio_dev == NULL) : break; I think Paul is saying that this check should be your return. -- To view, visit https://review.coreboot.org/c/coreboot/+/56100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49c673fd944b2c2a79c4283eee941a16596ba7fa Gerrit-Change-Number: 56100 Gerrit-PatchSet: 4 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alec Wang <alec.wang(a)lcfc.corp-partner.google.com> Gerrit-CC: Allen Cheng <allen.cheng(a)lcfc.corp-partner.google.com> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Daniel Kurtz <djkurtz(a)chromium.org> Gerrit-Attention: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 08 Jul 2021 18:13:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Revert "drivers/intel/fsp2_0: use FSP to allocate APEI BERT memory re...
by Raul Rangel (Code Review) 08 Jul '21

08 Jul '21

Attention is currently required from: Rocky Phagura, Tim Wawrzynczak, Subrata Banik, Andrey Petrov, Patrick Rudolph, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56163 ) Change subject: Revert "drivers/intel/fsp2_0: use FSP to allocate APEI BERT memory region" ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/56163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ca095ca327cbf925edb59b89fff42ff9f96de5d Gerrit-Change-Number: 56163 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rocky Phagura <rphagura(a)fb.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 08 Jul 2021 17:52:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86: smbios write 7 table using deterministic cache functions
by Subrata Banik (Code Review) 08 Jul '21

08 Jul '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Angel Pons. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56121 to look at the new patch set (#5). Change subject: arch/x86: smbios write 7 table using deterministic cache functions ...................................................................... arch/x86: smbios write 7 table using deterministic cache functions This patch makes use of deterministic cache helper functions, for example: cpu_get_cache_type(), cpu_get_cache_level() etc. helper functions from arch/x86/cpu_common.c file. Also, changed argument for get_number_of_caches() function that receives cpu_get_max_cache_share() data directly. Drop unused variables partitions, cache_line_size and number_of_sets as struct cpu_cache_info.size would provide the cache size directly. TEST=Able to dump SMBIOS Table 7 with this CL, no changes seen in output. Getting SMBIOS data from sysfs. SMBIOS 3.0 present. Handle 0x0005, DMI type 7, 27 bytes Cache Information Socket Designation: CACHE1 Configuration: Enabled, Not Socketed, Level 1 Operational Mode: Unknown Location: Internal Installed Size: 288 kB Maximum Size: 288 kB Supported SRAM Types: Unknown Installed SRAM Type: Unknown Speed: Unknown Error Correction Type: Unknown System Type: Data Associativity: 12-way Set-associative Handle 0x0006, DMI type 7, 27 bytes Cache Information Socket Designation: CACHE1 Configuration: Enabled, Not Socketed, Level 1 Operational Mode: Unknown Location: Internal Installed Size: 192 kB Maximum Size: 192 kB Supported SRAM Types: Unknown Installed SRAM Type: Unknown Speed: Unknown Error Correction Type: Unknown System Type: Instruction Associativity: 8-way Set-associative Handle 0x0007, DMI type 7, 27 bytes Cache Information Socket Designation: CACHE2 Configuration: Enabled, Not Socketed, Level 2 Operational Mode: Unknown Location: Internal Installed Size: 1280 kB Maximum Size: 1280 kB Supported SRAM Types: Unknown Installed SRAM Type: Unknown Speed: Unknown Error Correction Type: Unknown System Type: Unified Associativity: Unknown Handle 0x0008, DMI type 7, 27 bytes Cache Information Socket Designation: CACHE3 Configuration: Enabled, Not Socketed, Level 3 Operational Mode: Unknown Location: Internal Installed Size: 12288 kB Maximum Size: 12288 kB Supported SRAM Types: Unknown Installed SRAM Type: Unknown Speed: Unknown Error Correction Type: Unknown System Type: Unified Associativity: 12-way Set-associative Change-Id: Iedbd3b745629dea57c3ad6b0d187eab2bcc3f7d3 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/arch/x86/smbios.c 1 file changed, 10 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/56121/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/56121 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iedbd3b745629dea57c3ad6b0d187eab2bcc3f7d3 Gerrit-Change-Number: 56121 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: arch/x86: Helper functions to get deterministic cache parameters
by Subrata Banik (Code Review) 08 Jul '21

08 Jul '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Rizwan Qureshi, Subrata Banik, Patrick Rudolph. Hello build bot (Jenkins), Furquan Shaikh, Rizwan Qureshi, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55965 to look at the new patch set (#6). Change subject: arch/x86: Helper functions to get deterministic cache parameters ...................................................................... arch/x86: Helper functions to get deterministic cache parameters This patch creates helper function that internally detects the CPU type (AMD or Intel) and pick the leaf to send CPUID instruction with different cache level to retrieve deterministic cache parameters. Lists of helper functions generated as part of this CL : 1. cpu_check_deterministic_cache_cpuid_supported => if CPU has support for deterministic cache using CPUID instruction. 2. cpu_get_cache_ways_assoc_info => Get cache ways for associativity. 3. cpu_get_cache_type => Get cache type. 4. cpu_get_cache_level => Get cache level. 5. cpu_get_cache_phy_partition_info => Get cache physical partitions. 6. cpu_get_cache_line_size => Get cahce line size. 7. cpu_get_cache_sets => Get cache number of sets. 8. cpu_is_cache_full_assoc => Check if cache is fully associative. 9. cpu_get_max_cache_share => Cores are sharing this cache. 10. get_cache_size => Calculate the cache size. 11. fill_cpu_cache_info => Fill cpu_cache_info structure. Change-Id: I0dd701fb47460092448b64c7fa2162f762bf3095 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/arch/x86/cpu_common.c M src/arch/x86/include/arch/cpu.h 2 files changed, 239 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/55965/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/55965 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0dd701fb47460092448b64c7fa2162f762bf3095 Gerrit-Change-Number: 55965 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: arch/x86: smbios write 7 table using deterministic cache functions
by build bot (Jenkins) (Code Review) 08 Jul '21

08 Jul '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Angel Pons. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56121 ) Change subject: arch/x86: smbios write 7 table using deterministic cache functions ...................................................................... Patch Set 4: (1 comment) File src/arch/x86/smbios.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123653): https://review.coreboot.org/c/coreboot/+/56121/comment/f2f87400_4e034925 PS4, Line 811: struct cpu_cache_info info = fill_cpu_cahce_info(cnt++); 'cahce' may be misspelled - perhaps 'cache'? -- To view, visit https://review.coreboot.org/c/coreboot/+/56121 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iedbd3b745629dea57c3ad6b0d187eab2bcc3f7d3 Gerrit-Change-Number: 56121 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 08 Jul 2021 17:39:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86: Helper functions to get deterministic cache parameters
by build bot (Jenkins) (Code Review) 08 Jul '21

08 Jul '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Rizwan Qureshi, Subrata Banik, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55965 ) Change subject: arch/x86: Helper functions to get deterministic cache parameters ...................................................................... Patch Set 5: (3 comments) File src/arch/x86/cpu_common.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123652): https://review.coreboot.org/c/coreboot/+/55965/comment/a11e743c_d83b349c PS5, Line 214: struct cpu_cache_info fill_cpu_cahce_info(uint8_t level) 'cahce' may be misspelled - perhaps 'cache'? File src/arch/x86/include/arch/cpu.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123652): https://review.coreboot.org/c/coreboot/+/55965/comment/8428b354_802b6256 PS5, Line 406: * fill_cpu_cahce_info to get all required cache info data and fill into cpu_cache_info 'cahce' may be misspelled - perhaps 'cache'? Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123652): https://review.coreboot.org/c/coreboot/+/55965/comment/e4c65ffd_00133066 PS5, Line 409: struct cpu_cache_info fill_cpu_cahce_info(uint8_t level); 'cahce' may be misspelled - perhaps 'cache'? -- To view, visit https://review.coreboot.org/c/coreboot/+/55965 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0dd701fb47460092448b64c7fa2162f762bf3095 Gerrit-Change-Number: 55965 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 08 Jul 2021 17:39:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86: smbios write 7 table using deterministic cache functions
by Subrata Banik (Code Review) 08 Jul '21

08 Jul '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Angel Pons. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56121 to look at the new patch set (#4). Change subject: arch/x86: smbios write 7 table using deterministic cache functions ...................................................................... arch/x86: smbios write 7 table using deterministic cache functions This patch makes use of deterministic cache helper functions, for example: cpu_get_cache_type(), cpu_get_cache_level() etc. helper functions from arch/x86/cpu_common.c file. Also, changed argument for get_number_of_caches() function that receives cpu_get_max_cache_share() data directly. Drop unused variables partitions, cache_line_size and number_of_sets as struct cpu_cache_info.size would provide the cache size directly. TEST=Able to dump SMBIOS Table 7 with this CL, no changes seen in output. Getting SMBIOS data from sysfs. SMBIOS 3.0 present. Handle 0x0005, DMI type 7, 27 bytes Cache Information Socket Designation: CACHE1 Configuration: Enabled, Not Socketed, Level 1 Operational Mode: Unknown Location: Internal Installed Size: 288 kB Maximum Size: 288 kB Supported SRAM Types: Unknown Installed SRAM Type: Unknown Speed: Unknown Error Correction Type: Unknown System Type: Data Associativity: 12-way Set-associative Handle 0x0006, DMI type 7, 27 bytes Cache Information Socket Designation: CACHE1 Configuration: Enabled, Not Socketed, Level 1 Operational Mode: Unknown Location: Internal Installed Size: 192 kB Maximum Size: 192 kB Supported SRAM Types: Unknown Installed SRAM Type: Unknown Speed: Unknown Error Correction Type: Unknown System Type: Instruction Associativity: 8-way Set-associative Handle 0x0007, DMI type 7, 27 bytes Cache Information Socket Designation: CACHE2 Configuration: Enabled, Not Socketed, Level 2 Operational Mode: Unknown Location: Internal Installed Size: 1280 kB Maximum Size: 1280 kB Supported SRAM Types: Unknown Installed SRAM Type: Unknown Speed: Unknown Error Correction Type: Unknown System Type: Unified Associativity: Unknown Handle 0x0008, DMI type 7, 27 bytes Cache Information Socket Designation: CACHE3 Configuration: Enabled, Not Socketed, Level 3 Operational Mode: Unknown Location: Internal Installed Size: 12288 kB Maximum Size: 12288 kB Supported SRAM Types: Unknown Installed SRAM Type: Unknown Speed: Unknown Error Correction Type: Unknown System Type: Unified Associativity: 12-way Set-associative Change-Id: Iedbd3b745629dea57c3ad6b0d187eab2bcc3f7d3 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/arch/x86/smbios.c 1 file changed, 10 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/56121/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/56121 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iedbd3b745629dea57c3ad6b0d187eab2bcc3f7d3 Gerrit-Change-Number: 56121 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: arch/x86: Helper functions to get deterministic cache parameters
by Subrata Banik (Code Review) 08 Jul '21

08 Jul '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Rizwan Qureshi, Subrata Banik, Patrick Rudolph. Hello build bot (Jenkins), Furquan Shaikh, Rizwan Qureshi, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55965 to look at the new patch set (#5). Change subject: arch/x86: Helper functions to get deterministic cache parameters ...................................................................... arch/x86: Helper functions to get deterministic cache parameters This patch creates helper function that internally detects the CPU type (AMD or Intel) and pick the leaf to send CPUID instruction with different cache level to retrieve deterministic cache parameters. Lists of helper functions generated as part of this CL : 1. cpu_check_deterministic_cache_cpuid_supported => if CPU has support for deterministic cache using CPUID instruction. 2. cpu_get_cache_ways_assoc_info => Get cache ways for associativity. 3. cpu_get_cache_type => Get cache type. 4. cpu_get_cache_level => Get cache level. 5. cpu_get_cache_phy_partition_info => Get cache physical partitions. 6. cpu_get_cache_line_size => Get cahce line size. 7. cpu_get_cache_sets => Get cache number of sets. 8. cpu_is_cache_full_assoc => Check if cache is fully associative. 9. cpu_get_max_cache_share => Cores are sharing this cache. 10. get_cache_size => Calculate the cache size. 11. fill_cpu_cahce_info => Fill cpu_cache_info structure. Change-Id: I0dd701fb47460092448b64c7fa2162f762bf3095 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/arch/x86/cpu_common.c M src/arch/x86/include/arch/cpu.h 2 files changed, 239 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/55965/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/55965 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0dd701fb47460092448b64c7fa2162f762bf3095 Gerrit-Change-Number: 55965 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/{cezanne,common}: Enable IOMMU PCIe Device
by Jason Glenesk (Code Review) 08 Jul '21

08 Jul '21

Attention is currently required from: Raul Rangel, Marshall Dawson, Felix Held. Jason Glenesk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55737 ) Change subject: soc/amd/{cezanne,common}: Enable IOMMU PCIe Device ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > The iommu UPD seemed to write the IVRS table. I wasn't really sure what else it did though... […] The way i'm understanding the plumbing, we might need to set this eventually. Some of these things are not active in fsp currently. I will create a sighting now to track items remaining for iommu enablement in fsp and if this is required, i can set it. -- To view, visit https://review.coreboot.org/c/coreboot/+/55737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c7cae3d25af5a45d48658ffa948a2856adc4346 Gerrit-Change-Number: 55737 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 08 Jul 2021 17:09:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: grunt/treeya: add Realtek ALC5682 codec support
by build bot (Jenkins) (Code Review) 08 Jul '21

08 Jul '21

Attention is currently required from: Daniel Kurtz, Martin Roth, Paul Menzel. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56100 ) Change subject: grunt/treeya: add Realtek ALC5682 codec support ...................................................................... Patch Set 4: (1 comment) File src/mainboard/google/kahlee/variants/treeya/audio.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123650): https://review.coreboot.org/c/coreboot/+/56100/comment/589d72d3_a0fd4547 PS4, Line 25: if (mmio_dev == NULL){ space required before the open brace '{' -- To view, visit https://review.coreboot.org/c/coreboot/+/56100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49c673fd944b2c2a79c4283eee941a16596ba7fa Gerrit-Change-Number: 56100 Gerrit-PatchSet: 4 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alec Wang <alec.wang(a)lcfc.corp-partner.google.com> Gerrit-CC: Allen Cheng <allen.cheng(a)lcfc.corp-partner.google.com> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Daniel Kurtz <djkurtz(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 08 Jul 2021 17:02:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit July 2021