coreboot-gerrit July 2021

coreboot-gerrit@coreboot.org

1 participants
5824 discussions

Change in coreboot[master]: drivers/usb/acpi: Create function to get PLD information
by Tim Wawrzynczak (Code Review) 08 Jul '21

08 Jul '21

Attention is currently required from: Maulik V Vaghela, John Zhao. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56024 ) Change subject: drivers/usb/acpi: Create function to get PLD information ...................................................................... Patch Set 6: (1 comment) File src/drivers/usb/acpi/usb_acpi.c: https://review.coreboot.org/c/coreboot/+/56024/comment/8fdc7552_763249d2 PS6, Line 129: struct acpi_pld pld; : : if (!usb_device || !usb_device->chip_info || : usb_device->chip_ops != &drivers_usb_acpi_ops) : return NULL; : : if (config->use_custom_pld) : memcpy(&pld, &config->custom_pld, sizeof(pld)); : else : acpi_pld_fill_usb(&pld, config->type, &config->group); : : return &pld; You can't return a reference to an object on the stack, it will cease to exist when the function returns. Since the object is so large, maybe this should be malloc'd if it it's not the custom one, i.e.: ``` struct drivers_usb_acpi_config *config; struct acpi_pld *pld; if (!usb_device || !usb_device->chip_info || usb_device->chip_ops != &drivers_usb_acpi_ops) return NULL; config = usb_device->chip_info; if (config->use_custom_pld) return &config->custom_pld; pld = malloc(sizeof(*pld)); if (acpi_pld_fill_usb(pld, config->type, &config->group)) return NULL; return pld; ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/56024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaaf140ce1965dce3a812aa2701ce0e29b34ab3e7 Gerrit-Change-Number: 56024 Gerrit-PatchSet: 6 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Abhijeet Rao <abhijeet.rao(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Comment-Date: Thu, 08 Jul 2021 20:55:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd/*/Makefile.inc: Do some cosmetics
by Arthur Heymans (Code Review) 08 Jul '21

08 Jul '21

Attention is currently required from: Jason Glenesk, Martin Roth, Marshall Dawson, Felix Held. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56117 ) Change subject: soc/amd/*/Makefile.inc: Do some cosmetics ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > I'm not sure this makes things more understandable, but I don't have any outright objection to it. It seems like using $< against a macro is maybe bad since the macro obfuscates what the prerequisites are. I don't feel that strongly about this either. I just saw that it was not very consistent in the tree. -- To view, visit https://review.coreboot.org/c/coreboot/+/56117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea2322ca1abd43900f3631b7965f07fed4235ca0 Gerrit-Change-Number: 56117 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 08 Jul 2021 20:08:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/intel/adlrvp: Enable I2S audio codecs on ADL-M RVP
by Anil Kumar K (Code Review) 08 Jul '21

08 Jul '21

Attention is currently required from: Sathyanarayana Nujella, Selma Bensaid, Tim Wawrzynczak. Anil Kumar K has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52221 ) Change subject: mb/intel/adlrvp: Enable I2S audio codecs on ADL-M RVP ...................................................................... Patch Set 29: (1 comment) File src/mainboard/intel/adlrvp/devicetree_m.cb: https://review.coreboot.org/c/coreboot/+/52221/comment/772b91bf_33b1664f PS28, Line 231: i2c 1a on > can you please also add "probe AUDIO ADL_MAX98373_ALC5682I_I2S" for this entry too? Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/52221 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2649647e58c5f30e2b539d534adf2a4e68f4fda Gerrit-Change-Number: 52221 Gerrit-PatchSet: 29 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Jairaj Arava <jairaj.arava(a)intel.com> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 08 Jul 2021 19:05:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: amdfwtool: Fix the NULL pointer in parameters
by Felix Held (Code Review) 08 Jul '21

08 Jul '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55550 ) Change subject: amdfwtool: Fix the NULL pointer in parameters ...................................................................... amdfwtool: Fix the NULL pointer in parameters Change-Id: Ia2c65013d48fc1ad88d3caf6ef59824745c992de Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55550 Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/amdfwtool/amdfwtool.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 9299aec..b4d1c0c 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -1597,7 +1597,7 @@ combo_dir->entries[0].lvl2_addr = BUFF_TO_RUN(ctx, pspdir); combo_dir->header.lookup = 1; - fill_dir_header(combo_dir, 1, PSP2_COOKIE, NULL); + fill_dir_header(combo_dir, 1, PSP2_COOKIE, &ctx); #endif if (have_bios_tables(amd_bios_table)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/55550 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2c65013d48fc1ad88d3caf6ef59824745c992de Gerrit-Change-Number: 55550 Gerrit-PatchSet: 4 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: Revert "drivers/intel/fsp2_0: use FSP to allocate APEI BERT memory re...
by Felix Held (Code Review) 08 Jul '21

08 Jul '21

Attention is currently required from: Arthur Heymans, Rocky Phagura, Tim Wawrzynczak, Subrata Banik, Andrey Petrov, Patrick Rudolph. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56163 ) Change subject: Revert "drivers/intel/fsp2_0: use FSP to allocate APEI BERT memory region" ...................................................................... Patch Set 1: (1 comment) File src/drivers/intel/fsp2_0/hob_verify.c: https://review.coreboot.org/c/coreboot/+/56163/comment/438d24de_9bb709ac PS1, Line 52: > Will this condition ever occur? Should it be caught elsewhere? this doesn't need to be checked any more and i'm not even 100% certain if the second part of the condition in line 53 ever evaluated to true. before we could just put the BERT region into CBMEM due to the unexpected memory type 16 of CBMEM which the Linux kernel didn't know/like, the BERT region was put above CBMEM; see the diagram in https://review.coreboot.org/c/coreboot/+/56163/1/src/drivers/intel/fsp2_0/m… this check checked that the BERT region on top of CBMEM ends at TOLUM. When putting the BERT region into CBMEM and not reserving a section above CBMEM, CBMEM will end at TOLUM. Or did you mean ACPI_BERT being selected? only 2 of the recent Intel laptop SoCs and the AMD laptop SoCs select this option -- To view, visit https://review.coreboot.org/c/coreboot/+/56163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ca095ca327cbf925edb59b89fff42ff9f96de5d Gerrit-Change-Number: 56163 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rocky Phagura Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Rocky Phagura <rphagura(a)fb.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rocky Phagura Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 08 Jul 2021 18:50:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Rocky Phagura Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/intel/adlrvp: Add TCSS USB device for ADL-M RVP
by Selma Bensaid (Code Review) 08 Jul '21

08 Jul '21

Attention is currently required from: Bora Guvendik, Shaunak Saha, Tim Wawrzynczak, John Zhao, Bernardo Perez Priego, Sanrio Alvares, Deepti Deshatty, Patrick Rudolph. Selma Bensaid has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55362 ) Change subject: mb/intel/adlrvp: Add TCSS USB device for ADL-M RVP ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/55362 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I058b789a9169d48af4e7d2314ed98e8f7884538f Gerrit-Change-Number: 55362 Gerrit-PatchSet: 1 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sanrio Alvares <sanrio.alvares(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Sanrio Alvares <sanrio.alvares(a)intel.com> Gerrit-Attention: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 08 Jul 2021 18:48:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: arch/x86: Helper functions to get deterministic cache parameters
by Subrata Banik (Code Review) 08 Jul '21

08 Jul '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Rizwan Qureshi, Angel Pons, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55965 ) Change subject: arch/x86: Helper functions to get deterministic cache parameters ...................................................................... Patch Set 7: (1 comment) File src/arch/x86/include/arch/cpu.h: https://review.coreboot.org/c/coreboot/+/55965/comment/c28dcf72_024a29e1 PS4, Line 325: CACHE_L0 > Its not L0 cache, rather its like ECX=0, i don;t find any nicer way to convey that, ideally we can s […] renamed to L1D and L1I which would make it meaningful. -- To view, visit https://review.coreboot.org/c/coreboot/+/55965 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0dd701fb47460092448b64c7fa2162f762bf3095 Gerrit-Change-Number: 55965 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 08 Jul 2021 18:43:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: arch/x86: smbios write 7 table using deterministic cache functions
by Subrata Banik (Code Review) 08 Jul '21

08 Jul '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Angel Pons. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56121 to look at the new patch set (#6). Change subject: arch/x86: smbios write 7 table using deterministic cache functions ...................................................................... arch/x86: smbios write 7 table using deterministic cache functions This patch makes use of deterministic cache helper functions, for example: cpu_get_cache_type(), cpu_get_cache_level() etc. helper functions from arch/x86/cpu_common.c file. Also, changed argument for get_number_of_caches() function that receives cpu_get_max_cache_share() data directly. Drop unused variables partitions, cache_line_size and number_of_sets as struct cpu_cache_info.size would provide the cache size directly. TEST=Able to dump SMBIOS Table 7 with this CL, no changes seen in output. Getting SMBIOS data from sysfs. SMBIOS 3.0 present. Handle 0x0005, DMI type 7, 27 bytes Cache Information Socket Designation: CACHE1 Configuration: Enabled, Not Socketed, Level 1 Operational Mode: Unknown Location: Internal Installed Size: 288 kB Maximum Size: 288 kB Supported SRAM Types: Unknown Installed SRAM Type: Unknown Speed: Unknown Error Correction Type: Unknown System Type: Data Associativity: 12-way Set-associative Handle 0x0006, DMI type 7, 27 bytes Cache Information Socket Designation: CACHE1 Configuration: Enabled, Not Socketed, Level 1 Operational Mode: Unknown Location: Internal Installed Size: 192 kB Maximum Size: 192 kB Supported SRAM Types: Unknown Installed SRAM Type: Unknown Speed: Unknown Error Correction Type: Unknown System Type: Instruction Associativity: 8-way Set-associative Handle 0x0007, DMI type 7, 27 bytes Cache Information Socket Designation: CACHE2 Configuration: Enabled, Not Socketed, Level 2 Operational Mode: Unknown Location: Internal Installed Size: 1280 kB Maximum Size: 1280 kB Supported SRAM Types: Unknown Installed SRAM Type: Unknown Speed: Unknown Error Correction Type: Unknown System Type: Unified Associativity: Unknown Handle 0x0008, DMI type 7, 27 bytes Cache Information Socket Designation: CACHE3 Configuration: Enabled, Not Socketed, Level 3 Operational Mode: Unknown Location: Internal Installed Size: 12288 kB Maximum Size: 12288 kB Supported SRAM Types: Unknown Installed SRAM Type: Unknown Speed: Unknown Error Correction Type: Unknown System Type: Unified Associativity: 12-way Set-associative Change-Id: Iedbd3b745629dea57c3ad6b0d187eab2bcc3f7d3 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/arch/x86/smbios.c 1 file changed, 10 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/56121/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/56121 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iedbd3b745629dea57c3ad6b0d187eab2bcc3f7d3 Gerrit-Change-Number: 56121 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: arch/x86: Helper functions to get deterministic cache parameters
by Subrata Banik (Code Review) 08 Jul '21

08 Jul '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Rizwan Qureshi, Subrata Banik, Patrick Rudolph. Hello build bot (Jenkins), Furquan Shaikh, Rizwan Qureshi, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55965 to look at the new patch set (#7). Change subject: arch/x86: Helper functions to get deterministic cache parameters ...................................................................... arch/x86: Helper functions to get deterministic cache parameters This patch creates helper function that internally detects the CPU type (AMD or Intel) and pick the leaf to send CPUID instruction with different cache level to retrieve deterministic cache parameters. Lists of helper functions generated as part of this CL : 1. cpu_check_deterministic_cache_cpuid_supported => if CPU has support for deterministic cache using CPUID instruction. 2. cpu_get_cache_ways_assoc_info => Get cache ways for associativity. 3. cpu_get_cache_type => Get cache type. 4. cpu_get_cache_level => Get cache level. 5. cpu_get_cache_phy_partition_info => Get cache physical partitions. 6. cpu_get_cache_line_size => Get cahce line size. 7. cpu_get_cache_sets => Get cache number of sets. 8. cpu_is_cache_full_assoc => Check if cache is fully associative. 9. cpu_get_max_cache_share => Cores are sharing this cache. 10. get_cache_size => Calculate the cache size. 11. fill_cpu_cache_info => Fill cpu_cache_info structure. Change-Id: I0dd701fb47460092448b64c7fa2162f762bf3095 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/arch/x86/cpu_common.c M src/arch/x86/include/arch/cpu.h 2 files changed, 239 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/55965/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/55965 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0dd701fb47460092448b64c7fa2162f762bf3095 Gerrit-Change-Number: 55965 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: Revert "drivers/intel/fsp2_0: use FSP to allocate APEI BERT memory re...
by Rocky Phagura (Code Review) 08 Jul '21

08 Jul '21

Attention is currently required from: Arthur Heymans, Rocky Phagura, Tim Wawrzynczak, Subrata Banik, Andrey Petrov, Patrick Rudolph, Felix Held. Rocky Phagura has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56163 ) Change subject: Revert "drivers/intel/fsp2_0: use FSP to allocate APEI BERT memory region" ...................................................................... Patch Set 1: (1 comment) File src/drivers/intel/fsp2_0/hob_verify.c: https://review.coreboot.org/c/coreboot/+/56163/comment/6bbf676e_96772522 PS1, Line 52: Will this condition ever occur? Should it be caught elsewhere? -- To view, visit https://review.coreboot.org/c/coreboot/+/56163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ca095ca327cbf925edb59b89fff42ff9f96de5d Gerrit-Change-Number: 56163 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rocky Phagura Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Rocky Phagura <rphagura(a)fb.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 08 Jul 2021 18:16:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit July 2021