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Change subject: Kconfig: Fix BOOT_DEVICE_MEMORY_MAPPED
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/54302/comment/cf0818ab_40dbbf71
PS1, Line 7: Fix BOOT_DEVICE_MEMORY_MAPPED
:
: Also non SPI x86 is memory mapped.
> > On some older boards there is LPC flash instead of SPI. […]
I think the issue is that there isn't a LPC_FLASH Kconfig notion. We've married interconnect and boot media together with the Kconfigs, but Arthur is wanting a way to make sure things are memory mapped regardless of interconnect. However, there aren't many supported systems that have LPC any longer.
This change modifies the default behavior, but there's no reason one couldn't select BOOT_DEVICE_MEMORY_MAPPED from the chipset or mainboard level to achieve that same notion. A counter point is that some x86 systems don't actually have memory mapped boot media under certain circumstances. So modifying the default doesn't hold either.
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Change subject: mb/google/brya: move MIPI camera setting into overridetree
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/brya/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/55134/comment/36be0bf2_60b1edbe
PS1, Line 132: device ref ipu on end
Should this be dropped from baseboard/devicetree so that the ipu is default off?
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Change subject: Documentation: Add proposal to allow enabling serial console with a flag
......................................................................
Patch Set 3:
(3 comments)
File Documentation/technotes/2021-05-selectable-serial-console.md:
https://review.coreboot.org/c/coreboot/+/54385/comment/17f4c862_b2849a93
PS2, Line 69: have already been saying that decades ago.)
> I’d put the dot/period behind the ).
Ack
https://review.coreboot.org/c/coreboot/+/54385/comment/b4fc2c15_c1b88cc2
PS2, Line 121: disabled
> disables
Done
https://review.coreboot.org/c/coreboot/+/54385/comment/9cd58329_1e4e9ef0
PS2, Line 125: turning it off entirely).
> Let’s do this from the beginning and use the log level numbers? I’d like that.
We should discuss that so I can adapt the implementation to match.
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I'd like you to reexamine a change. Please visit
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Change subject: Documentation: Add proposal to allow enabling serial console with a flag
......................................................................
Documentation: Add proposal to allow enabling serial console with a flag
BUG=b:172341184, b:151780766
Change-Id: If1b0efc55880095f9d5d6d6e448f2c8677d57ff5
Signed-off-by: Patrick Georgi <pgeorgi(a)google.com>
---
A Documentation/technotes/2021-05-selectable-serial-console.md
M Documentation/technotes/index.md
2 files changed, 126 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/54385/3
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Change subject: mb/google/guybrush: Add helpers for cbi fw_config settings.
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/google/guybrush/variants/guybrush/helpers.c:
https://review.coreboot.org/c/coreboot/+/54639/comment/0677250d_23dafd29
PS4, Line 44: get_variant_wwan_type
> The helper functions at the baseboard level don't need to use fw_config at all. […]
Furquan, I understand what you're saying. I just disagree with the approach. You're making things more complex than the need to be.
The problem with variant_has_fpmcu() is that it's getting called before anything is initialized - that was what was causing the initial failure. The serial port is not configured, and probing it didn't work.
So for FPMCU, it's always just going to be whatever the fw_config says it is.
It's either on in fw_config and there's a fingerprint sensor, or it's not present. There's no need to go look at the device in devicetree. If we had global fw_config, this wouldn't even be an issue, but because you didn't like that idea, now we need to go with a more complex solution of probing devices in devicetree.
It would be far easier, in my opinion to just fix fw_config to expect being probed for things that didn't exist on that platform and return that they were disabled.
What I'm saying is that your solution adds a lot of additional runtime complexity that isn't needed on a per platform basis without really helping in the bootblock where I need this code to be.
I'm sure I'm going to be on the losing end of this argument, but I don't think it's a good solution for this problem.
Is there a design doc that we can look at and comment on?
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Change subject: mb/google/volteer:intel/common/block: Move mainboard api to tcss common block
......................................................................
Patch Set 7: Code-Review+2
(7 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/54733/comment/3e7716e7_44becdea
PS7, Line 6:
: mb/google/volteer:intel/common/block: Move mainboard api to tcss common block
`intel/common/block` is enough of a prefix
https://review.coreboot.org/c/coreboot/+/54733/comment/f0c660bf_81f38722
PS7, Line 9: As per the comments in CB:54090 mainboard api
: mainboard_tcss_get_port_info() is simplified and moved
: to tcss common block code.
This text should be 72 characters wide
Patchset:
PS7:
Looks good Deepti, just a few nits 😊
File src/drivers/intel/pmc_mux/conn/chip.h:
https://review.coreboot.org/c/coreboot/+/54733/comment/1118ca18_3162c820
PS7, Line 32:
nit: line up with `const struct device...`
File src/soc/intel/common/block/tcss/tcss.c:
https://review.coreboot.org/c/coreboot/+/54733/comment/54815359_44285219
PS7, Line 346: static struct tcss_port_map port_map[MAX_TYPE_C_PORTS];
nit: place static variables first in the declaration order
https://review.coreboot.org/c/coreboot/+/54733/comment/ea86d36a_0c966f96
PS7, Line 349:
nit: extra blank line
https://review.coreboot.org/c/coreboot/+/54733/comment/1a88fbd6_0c39b64a
PS7, Line 352: {.type = DEVICE_PATH_GENERIC, .generic.id = 0, .generic.subid = 0},
good catch, I forgot about that one 😊
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Change subject: Kconfig: Fix BOOT_DEVICE_MEMORY_MAPPED
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/54302/comment/307f579a_1612d484
PS1, Line 7: Fix BOOT_DEVICE_MEMORY_MAPPED
:
: Also non SPI x86 is memory mapped.
> On some older boards there is LPC flash instead of SPI. Emulation qemu boards also don't have SPI emulated.
In these cases, is the boot medium still memory mapped? If so, it looks like you need the selection of `BOOT_DEVICE_MEMORY_MAPPED` config for the mainboards rather than changing the default selection of the config. Or are there more things to consider?
> To answer Furquans question: It looks like it is only used in arch/x86/postcar_loader.c to set up a WP MTRR for the ROM.
Sorry, I still did not understand the intention. For the case that you are considering:
1. What is the boot medium?
2. Is it still SPI flash?
3. If not:
a. Is the non-SPI flash boot medium memory mapped?
b. In this case, is the SPI flash still memory mapped? Do you intend to configure things for the memory mapped SPI flash in postcar even though it is not the boot medium?
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Hello build bot (Jenkins), Raul Rangel, Furquan Shaikh, Felix Held,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/guybrush: Move variant_has_fpmcu() after eSPI init
......................................................................
mb/google/guybrush: Move variant_has_fpmcu() after eSPI init
Currently variant_has_fpmcu() is called very early in bootblock, before
eSPI is initialized. When checking CBI for its presence, that causes
an error and nothing else can be read from CBI in bootblock.
Moving it slightly later in bootblock doesn't hurt anything from a
timing standpoint, and allows CBI to be read.
BUG=None
TEST=See CBI get read and the FPMCU field read correctly.
Signed-off-by: Martin Roth <martinroth(a)chromium.org>
Change-Id: I6de44119e92c8820b266f9f07287706c7d4eb505
---
M src/mainboard/google/guybrush/bootblock.c
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/54740/4
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Anjaneya "Reddy" Chagam, Marshall Dawson, Jonathan Zhang, Johnny Lin, Morgan Jang, Kyösti Mälkki, Aaron Durbin, Patrick Rudolph, Felix Held,
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Change subject: [WIP]arch/x86: Tear down CAR in ramstage
......................................................................
[WIP]arch/x86: Tear down CAR in ramstage
Postcar is a 'full' stage to just run a few instructions to disable
CAR and setup MTRR for ramstage. This takes up a lot of place in ROM.
This functionality can be moved into ramstage.
Notes: Typically no caching is set up around cbmem so the LZMA
compressed ramstage is being decompressed in uncached memory, which is
likely to be slow.
Change-Id: I02e5017ab2b6a6fd30b37edad19165c2531c8fd1
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/arch/x86/Kconfig
M src/arch/x86/c_start.S
M src/arch/x86/exit_car.S
A src/arch/x86/exit_car.inc
M src/arch/x86/postcar_loader.c
M src/cpu/qemu-x86/Kconfig
M src/cpu/x86/mtrr/Makefile.inc
M src/lib/program.ld
M src/mainboard/emulation/qemu-i440fx/Kconfig
M src/mainboard/emulation/qemu-i440fx/Makefile.inc
M src/soc/amd/common/block/cpu/car/Makefile.inc
M src/soc/intel/common/block/cpu/Makefile.inc
M src/soc/intel/xeon_sp/Kconfig
13 files changed, 56 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/54301/3
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