coreboot-gerrit June 2021

coreboot-gerrit@coreboot.org

1 participants
7127 discussions

Change in coreboot[master]: payloads/tianocore: Restrict bootsplash option to UEFIPAYLOAD
by Matt DeVillier (Code Review) 02 Jun '21

02 Jun '21

Attention is currently required from: Martin Roth, Stefan Reinauer. Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55145 ) Change subject: payloads/tianocore: Restrict bootsplash option to UEFIPAYLOAD ...................................................................... payloads/tianocore: Restrict bootsplash option to UEFIPAYLOAD The custom bootsplash option only functions when using the UEFIPAYLOAD payload option, so restrict visibility to when that option is selected. Change-Id: If5fe46b629e5275da54a5e86465a68271110397b Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M payloads/external/tianocore/Kconfig 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/55145/1 diff --git a/payloads/external/tianocore/Kconfig b/payloads/external/tianocore/Kconfig index 68016aa..6499127 100644 --- a/payloads/external/tianocore/Kconfig +++ b/payloads/external/tianocore/Kconfig @@ -62,8 +62,6 @@ You may want to increase the default cbmem buffer size when selecting this option, especially if using a debug (vs release) build. -endif - config TIANOCORE_BOOTSPLASH_IMAGE bool "Use a custom bootsplash image" help @@ -83,6 +81,8 @@ If an absolute path is not given, the path will assumed to be relative to the coreboot root directory. +endif + config TIANOCORE_BOOT_TIMEOUT int default 2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55145 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5fe46b629e5275da54a5e86465a68271110397b Gerrit-Change-Number: 55145 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: payloads/tianocore: Add Kconfig option to enable cbmem logging
by Matt DeVillier (Code Review) 02 Jun '21

02 Jun '21

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55144 ) Change subject: payloads/tianocore: Add Kconfig option to enable cbmem logging ...................................................................... payloads/tianocore: Add Kconfig option to enable cbmem logging Logging to coreboot cbmem, instead of a serial console, was added to MrChromebox's uefipayloadpkg branch. Add a Kconfig option to enable this, and restrict it to the UEFIPAYLOAD payload option, since this feature does not exist in upstream edk2. Change-Id: Idef125235dc7ba885eb22ac69c6f752588a9e295 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M payloads/external/Makefile.inc M payloads/external/tianocore/Kconfig M payloads/external/tianocore/Makefile 3 files changed, 17 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/55144/1 diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index e30f570..3d46553 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -148,6 +148,7 @@ CONFIG_TIANOCORE_UPSTREAM=$(CONFIG_TIANOCORE_UPSTREAM) \ CONFIG_MMCONF_BASE_ADDRESS=$(CONFIG_MMCONF_BASE_ADDRESS) \ CONFIG_TIANOCORE_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT) \ + CONFIG_TIANOCORE_CBMEM_LOGGING=$(CONFIG_TIANOCORE_CBMEM_LOGGING) \ GCC_CC_x86_32=$(GCC_CC_x86_32) \ GCC_CC_x86_64=$(GCC_CC_x86_64) \ GCC_CC_arm=$(GCC_CC_arm) \ diff --git a/payloads/external/tianocore/Kconfig b/payloads/external/tianocore/Kconfig index c227bf3..68016aa 100644 --- a/payloads/external/tianocore/Kconfig +++ b/payloads/external/tianocore/Kconfig @@ -53,6 +53,17 @@ endchoice +if TIANOCORE_UEFIPAYLOAD + +config TIANOCORE_CBMEM_LOGGING + bool "Enable Tianocore logging to CBMEM" + help + Select this option if you want to enable Tianocore logging to CBMEM. + You may want to increase the default cbmem buffer size when selecting + this option, especially if using a debug (vs release) build. + +endif + config TIANOCORE_BOOTSPLASH_IMAGE bool "Use a custom bootsplash image" help diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile index 7ab4f9e..e23d946 100644 --- a/payloads/external/tianocore/Makefile +++ b/payloads/external/tianocore/Makefile @@ -30,9 +30,13 @@ BUILD_TYPE=RELEASE endif +ifeq ($(CONFIG_TIANOCORE_CBMEM_LOGGING),y) +CBMEM=-D USE_CBMEM_FOR_CONSOLE=TRUE +endif + TIMEOUT=-D PLATFORM_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT) -BUILD_STR=-q -a IA32 -a X64 -p UefiPayloadPkg/UefiPayloadPkg.dsc -t COREBOOT -b $(BUILD_TYPE) $(TIMEOUT) $(build_flavor) +BUILD_STR=-q -a IA32 -a X64 -p UefiPayloadPkg/UefiPayloadPkg.dsc -t COREBOOT -b $(BUILD_TYPE) $(TIMEOUT) $(build_flavor) $(CBMEM) all: clean build -- To view, visit https://review.coreboot.org/c/coreboot/+/55144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idef125235dc7ba885eb22ac69c6f752588a9e295 Gerrit-Change-Number: 55144 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: intel/common/block: Move mainboard api to tcss common block
by Deepti Deshatty (Code Review) 02 Jun '21

02 Jun '21

Attention is currently required from: Furquan Shaikh, Paul Menzel, Sridhar Siricilla, Deepti Deshatty, Patrick Rudolph. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Sridhar Siricilla, Deepti Deshatty, Patrick Rudolph, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54733 to look at the new patch set (#8). Change subject: intel/common/block: Move mainboard api to tcss common block ...................................................................... intel/common/block: Move mainboard api to tcss common block As per the comments in CB:54090 mainboard api mainboard_tcss_get_port_info() is simplified and moved to tcss common block code. Signed-off-by: Deepti Deshatty <deepti.deshatty(a)intel.com> Change-Id: I7894363df4862f7cfe733d93e6160677fb8a9e31 --- M src/drivers/intel/pmc_mux/conn/chip.h M src/drivers/intel/pmc_mux/conn/conn.c M src/mainboard/google/volteer/mainboard.c M src/soc/intel/common/block/include/intelblocks/tcss.h M src/soc/intel/common/block/tcss/tcss.c 5 files changed, 58 insertions(+), 60 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/54733/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/54733 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7894363df4862f7cfe733d93e6160677fb8a9e31 Gerrit-Change-Number: 54733 Gerrit-PatchSet: 8 Gerrit-Owner: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Deepti Deshatty <deepti.deshatty(a)intel.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Deepti Deshatty <deepti.deshatty(a)intel.corp-partner.google.com> Gerrit-Attention: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/common/block/pcie/rtd3: Make changes to support S3
by Duncan Laurie (Code Review) 02 Jun '21

02 Jun '21

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48682 ) Change subject: soc/intel/common/block/pcie/rtd3: Make changes to support S3 ...................................................................... soc/intel/common/block/pcie/rtd3: Make changes to support S3 The RTD3 ACPI _ON method will unconditionally attempt to re-initialize the device, setting up GPIOs, clocks, and the L23 ready exit flow. When using S3 instead of S0ix this work is not needed and instead results in the device disappearing and the resume failing in the OS. BUG=b:174776411 TEST=test S3 and S0ix on volteer device with both NVMe and SD using the RTD3 driver to ensure suspend/resume works in both cases. Change-Id: I6bd7d001890939850381858fe663366472aacefc --- M src/soc/intel/common/block/pcie/rtd3/rtd3.c 1 file changed, 36 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/48682/1 diff --git a/src/soc/intel/common/block/pcie/rtd3/rtd3.c b/src/soc/intel/common/block/pcie/rtd3/rtd3.c index be412e7..52a7d03 100644 --- a/src/soc/intel/common/block/pcie/rtd3/rtd3.c +++ b/src/soc/intel/common/block/pcie/rtd3/rtd3.c @@ -74,12 +74,46 @@ acpigen_write_store_int_to_namestr(1, ACPI_REG_PCI_L23_SAVE_STATE); } +static void pcie_rtd3_check_gpio(const struct soc_intel_common_block_pcie_rtd3_config *config) +{ + const struct acpi_gpio *gpio; + + /* Use enable GPIO for status if provided, otherwise use reset GPIO. */ + if (config->enable_gpio.pin_count) + gpio = &config->enable_gpio; + else + gpio = &config->reset_gpio; + + /* Read current GPIO value into Local0. */ + acpigen_get_tx_gpio(gpio); + + /* Ensure check works for both active low and active high GPIOs. */ + acpigen_write_store_int_to_op(gpio->active_low, LOCAL1_OP); + + acpigen_write_if_lequal_op_op(LOCAL0_OP, LOCAL1_OP); + acpigen_write_store_int_to_op(0, LOCAL0_OP); + acpigen_pop_len(); /* If */ + acpigen_write_else(); + acpigen_write_store_int_to_op(1, LOCAL0_OP); + acpigen_pop_len(); /* Else */ +} + static void pcie_rtd3_acpi_method_on(unsigned int pcie_rp, const struct soc_intel_common_block_pcie_rtd3_config *config) { acpigen_write_method_serialized("_ON", 0); + /* + * Exit early if device status GPIOs indicate device is already in the on/ready state. + * This will happen if S3 resume is used instead of S0ix resume where coreboot has + * already re-initalized the device and the ACPI code does not need to run. + */ + pcie_rtd3_check_gpio(config); + acpigen_write_if_lequal_op_int(LOCAL0_OP, 1); + acpigen_write_return_op(ZERO_OP); + acpigen_pop_len(); /* If */ + /* Assert enable GPIO to turn on device power. */ if (config->enable_gpio.pin_count) { acpigen_enable_tx_gpio(&config->enable_gpio); @@ -140,28 +174,10 @@ pcie_rtd3_acpi_method_status(int pcie_rp, const struct soc_intel_common_block_pcie_rtd3_config *config) { - const struct acpi_gpio *gpio; - acpigen_write_method("_STA", 0); - /* Use enable GPIO for status if provided, otherwise use reset GPIO. */ - if (config->enable_gpio.pin_count) - gpio = &config->enable_gpio; - else - gpio = &config->reset_gpio; - - /* Read current GPIO value into Local0. */ - acpigen_get_tx_gpio(gpio); - - /* Ensure check works for both active low and active high GPIOs. */ - acpigen_write_store_int_to_op(gpio->active_low, LOCAL1_OP); - - acpigen_write_if_lequal_op_op(LOCAL0_OP, LOCAL1_OP); - acpigen_write_return_op(ZERO_OP); - acpigen_pop_len(); /* If */ - acpigen_write_else(); - acpigen_write_return_op(ONE_OP); - acpigen_pop_len(); /* Else */ + pcie_rtd3_check_gpio(config); + acpigen_write_return_op(LOCAL0_OP); acpigen_pop_len(); /* Method */ } -- To view, visit https://review.coreboot.org/c/coreboot/+/48682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6bd7d001890939850381858fe663366472aacefc Gerrit-Change-Number: 48682 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: mb/google/guybrush: initialize i2c in psp_verstage
by Furquan Shaikh (Code Review) 02 Jun '21

02 Jun '21

Attention is currently required from: Raul Rangel, Kangheui Won, Felix Held. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55136 ) Change subject: mb/google/guybrush: initialize i2c in psp_verstage ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/guybrush/verstage.c: https://review.coreboot.org/c/coreboot/+/55136/comment/8d03815e_5124e961 PS1, Line 28: if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) { : enable_aoac_devices(); : printk(BIOS_DEBUG, "Setting up i2c\n"); : i2c_soc_early_init(); : printk(BIOS_DEBUG, "i2c setup\n"); : } I think this should be done as part of `verstage_soc_init()` and not mainboard init. It is similar to how i2c early init and other inits are performed in bootblock and/or other stages. -- To view, visit https://review.coreboot.org/c/coreboot/+/55136 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f7b73be67a692ea7de31ae53bd111d0e4b6998c Gerrit-Change-Number: 55136 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 02 Jun 2021 19:38:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/alderlake: Set SaIpuEnable UPD from device state
by Furquan Shaikh (Code Review) 02 Jun '21

02 Jun '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55143 ) Change subject: soc/intel/alderlake: Set SaIpuEnable UPD from device state ...................................................................... Patch Set 1: Code-Review+2 (1 comment) File src/soc/intel/alderlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/55143/comment/27918fb3_14903df9 PS1, Line 214: m_cfg->SaIpuEnable > Yes, it could, but to me this is more maintainable, rather than relying on `dev` which was set 10+ l […] You won't really be reusing `dev` here, but SaIpuEnable. I understand that it still leaves the door open for missing out the configuration if the code get re-ordered. -- To view, visit https://review.coreboot.org/c/coreboot/+/55143 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53752f92c4b49093218cc34848727a72b63e84eb Gerrit-Change-Number: 55143 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 02 Jun 2021 19:34:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/alderlake: Set SaIpuEnable UPD from device state
by Tim Wawrzynczak (Code Review) 02 Jun '21

02 Jun '21

Attention is currently required from: Furquan Shaikh, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55143 ) Change subject: soc/intel/alderlake: Set SaIpuEnable UPD from device state ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/alderlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/55143/comment/8066943f_c447607b PS1, Line 214: m_cfg->SaIpuEnable > This check can be left as is, right? Since we have already evaluated the state of SA_DEVFN_IPU devic […] Yes, it could, but to me this is more maintainable, rather than relying on `dev` which was set 10+ lines ago -- To view, visit https://review.coreboot.org/c/coreboot/+/55143 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53752f92c4b49093218cc34848727a72b63e84eb Gerrit-Change-Number: 55143 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 02 Jun 2021 19:32:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/adl: Add SKU specific power limits support
by Tim Wawrzynczak (Code Review) 02 Jun '21

02 Jun '21

Attention is currently required from: Furquan Shaikh, Paul Menzel, Sumeet R Pawnikar, Rajasekhar Venkatanagapavan, Patrick Rudolph, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54676 ) Change subject: soc/intel/adl: Add SKU specific power limits support ...................................................................... Patch Set 8: (1 comment) File src/mainboard/intel/adlrvp/devicetree.cb: https://review.coreboot.org/c/coreboot/+/54676/comment/07dcc420_1144a968 PS8, Line 137: register "power_limits_config" = "{ : .tdp_pl1_override = 45, : .tdp_pl2_override = 56, : }" : adlrvp still needs to override these, or else this patch will change them to 45 and 115 -- To view, visit https://review.coreboot.org/c/coreboot/+/54676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1676e2b4d611cdc85e770f131d5b6d5ecd180be Gerrit-Change-Number: 54676 Gerrit-PatchSet: 8 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rajasekhar Venkatanagapavan <rajasekhar.venkatanagapavan(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Rajasekhar Venkatanagapavan <rajasekhar.venkatanagapavan(a)intel.corp-partner.google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 02 Jun 2021 19:22:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya: Create primus variant
by Tim Wawrzynczak (Code Review) 02 Jun '21

02 Jun '21

Attention is currently required from: Scott Chao. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55132 ) Change subject: mb/google/brya: Create primus variant ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26787f296793b281b7f1ee1a7d240006163c6015 Gerrit-Change-Number: 55132 Gerrit-PatchSet: 6 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Comment-Date: Wed, 02 Jun 2021 19:20:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/xeon_sp/cpx: Move MSR Locks to CPU init and fix them
by Rocky Phagura (Code Review) 02 Jun '21

02 Jun '21

Attention is currently required from: Marc Jones, Anjaneya "Reddy" Chagam, Jonathan Zhang, Arthur Heymans, Morgan Jang, Patrick Rudolph. Rocky Phagura has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55098 ) Change subject: soc/intel/xeon_sp/cpx: Move MSR Locks to CPU init and fix them ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/55098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21598c3e9a153dce25a09b187ddf9cf6363039d3 Gerrit-Change-Number: 55098 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rocky Phagura Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 02 Jun 2021 19:20:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2021