coreboot-gerrit June 2021

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Change in coreboot[master]: arch/x86/postcar: Set up postcar in C code
by Arthur Heymans (Code Review) 02 Jun '21

02 Jun '21

Attention is currently required from: Aaron Durbin. Hello build bot (Jenkins), Aaron Durbin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54299 to look at the new patch set (#4). Change subject: arch/x86/postcar: Set up postcar in C code ...................................................................... arch/x86/postcar: Set up postcar in C code TESTED on Qemu. Change-Id: I5ec10e84118197a04de0a5194336ef8bb049bba4 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/exit_car.S M src/arch/x86/include/arch/romstage.h M src/arch/x86/postcar.c M src/arch/x86/postcar_loader.c M src/cpu/x86/mtrr/Makefile.inc M src/cpu/x86/mtrr/earlymtrr.c M src/include/cpu/x86/mtrr.h 7 files changed, 59 insertions(+), 211 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/54299/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/54299 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ec10e84118197a04de0a5194336ef8bb049bba4 Gerrit-Change-Number: 54299 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/intel: Add LOCKDIS to mark SPI as writable in SKL
by Sean Rhodes (Code Review) 02 Jun '21

02 Jun '21

Sean Rhodes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/52796 ) Change subject: src/intel: Add LOCKDIS to mark SPI as writable in SKL ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/52796 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I712972428dd22373d8655ce72d36c0957ee9a900 Gerrit-Change-Number: 52796 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: Kconfig: Fix BOOT_DEVICE_MEMORY_MAPPED
by Arthur Heymans (Code Review) 02 Jun '21

02 Jun '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Aaron Durbin. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54302 ) Change subject: Kconfig: Fix BOOT_DEVICE_MEMORY_MAPPED ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/54302/comment/979df360_009fb124 PS1, Line 7: Fix BOOT_DEVICE_MEMORY_MAPPED : : Also non SPI x86 is memory mapped. > A follow up question would be: > > What do you consider 'non SPI'? What sort of protocols or boot mediums are being considered? As Furquan mentioned, the intention of the change isn't clear in what the change is trying to achieve. On some older boards there is LPC flash instead of SPI. Emulation qemu boards also don't have SPI emulated. To answer Furquans question: It looks like it is only used in arch/x86/postcar_loader.c to set up a WP MTRR for the ROM. -- To view, visit https://review.coreboot.org/c/coreboot/+/54302 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c21e87d3375220a50645e0bf8b56fd23983f0c0 Gerrit-Change-Number: 54302 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Wed, 02 Jun 2021 15:50:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush/var/guybrush: Reconfigure left speaker amplifier
by Raul Rangel (Code Review) 02 Jun '21

02 Jun '21

Attention is currently required from: Furquan Shaikh, Martin Roth, Marshall Dawson, Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55028 ) Change subject: mb/google/guybrush/var/guybrush: Reconfigure left speaker amplifier ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55028 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69a7e7dd65a459c2e5629ada1dea1f1660dd9990 Gerrit-Change-Number: 55028 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 02 Jun 2021 15:49:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: Add proposal to allow enabling serial console with a flag
by Arthur Heymans (Code Review) 02 Jun '21

02 Jun '21

Attention is currently required from: Stefan Reinauer. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54385 ) Change subject: Documentation: Add proposal to allow enabling serial console with a flag ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/54385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1b0efc55880095f9d5d6d6e448f2c8677d57ff5 Gerrit-Change-Number: 54385 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Wed, 02 Jun 2021 15:42:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/i2c/designware: Report I2C timings for additional bus speeds
by Tim Wawrzynczak (Code Review) 02 Jun '21

02 Jun '21

Attention is currently required from: Paul Menzel, Tim Wawrzynczak, Werner Zeh, Kyösti Mälkki. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55088 ) Change subject: drivers/i2c/designware: Report I2C timings for additional bus speeds ...................................................................... Patch Set 4: Code-Review+1 (1 comment) File src/drivers/i2c/designware/dw_i2c.c: https://review.coreboot.org/c/coreboot/+/55088/comment/92756d84_80118da0 PS3, Line 839: acpigen_pop_len > Oh, these functions are new (added in CB:50910), I wasn't aware. Thank you for the pointer. […] Oops sorry yes, I meant acpigen_write_scope_end() 😊 They're great for readability! -- To view, visit https://review.coreboot.org/c/coreboot/+/55088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If921e0613864660dc1bb8d7c1b30fb9db8ac655d Gerrit-Change-Number: 55088 Gerrit-PatchSet: 4 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Wed, 02 Jun 2021 15:28:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: remove warm reset flag code
by Felix Held (Code Review) 02 Jun '21

02 Jun '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55059 ) Change subject: soc/amd/picasso: remove warm reset flag code ...................................................................... soc/amd/picasso: remove warm reset flag code Since the MCA(X) registers have defined values on the cold boot path, the is_warm_reset check can be dropped. Also the warm reset bit in the NCP_ERR register doesn't behave as the PPR [1] suggested; no matter if something was written to the register or the machine went through a warm reset cycle, the NCP_WARM_BOOT bit never got set. [1] checked with PPR for AMD Family 17h Models 11h,18h B1 (RV,PCO) #55570 Rev 3.15 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I4e6df98ffd5d15ca204c9847a76c19c753726737 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55059 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/picasso/cpu.c M src/soc/amd/picasso/include/soc/iomap.h M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/picasso/mca.c M src/soc/amd/picasso/reset.c 5 files changed, 25 insertions(+), 47 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index 5acaa69..4e9c9a9 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -59,8 +59,6 @@ /* pre_mp_init made the flash not cacheable. Reset to WP for performance. */ mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); - - set_warm_reset_flag(); } static void model_17_init(struct device *dev) diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index 5b75ecb..b6f5dbb 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -83,7 +83,6 @@ #define ACPI_GPE0_BLK (ACPI_IO_BASE + 0x20) /* 8 bytes */ #define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) /* 4 bytes */ #define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) /* 4 bytes */ -#define NCP_ERR 0xf0 #define SMB_BASE_ADDR 0xb00 #define PM2_INDEX 0xcd0 #define PM2_DATA 0xcd1 diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 11660aa..b623ed3 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -140,9 +140,6 @@ #define SATA_CAPABILITIES_REG 0xfc #define SATA_CAPABILITY_SPM BIT(12) -/* IO 0xf0 NCP Error */ -#define NCP_WARM_BOOT BIT(7) /* Write-once */ - typedef struct aoac_devs { unsigned int :7; unsigned int ic2e:1; /* 7: I2C2 */ diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c index aab95ca..2576f6e 100644 --- a/src/soc/amd/picasso/mca.c +++ b/src/soc/amd/picasso/mca.c @@ -159,36 +159,34 @@ cap = rdmsr(IA32_MCG_CAP); num_banks = cap.lo & MCA_BANKS_MASK; - if (is_warm_reset()) { - for (i = 0 ; i < num_banks ; i++) { - mci.sts = rdmsr(MCAX_STATUS_MSR(i)); - if (mci.sts.hi || mci.sts.lo) { - int core = cpuid_ebx(1) >> 24; + for (i = 0 ; i < num_banks ; i++) { + mci.sts = rdmsr(MCAX_STATUS_MSR(i)); + if (mci.sts.hi || mci.sts.lo) { + int core = cpuid_ebx(1) >> 24; - printk(BIOS_WARNING, "#MC Error: core %d, bank %d %s\n", - core, i, - i < ARRAY_SIZE(mca_bank_name) ? mca_bank_name[i] : ""); + printk(BIOS_WARNING, "#MC Error: core %d, bank %d %s\n", + core, i, + i < ARRAY_SIZE(mca_bank_name) ? mca_bank_name[i] : ""); - printk(BIOS_WARNING, " MC%d_STATUS = %08x_%08x\n", - i, mci.sts.hi, mci.sts.lo); - mci.addr = rdmsr(MCAX_ADDR_MSR(i)); - printk(BIOS_WARNING, " MC%d_ADDR = %08x_%08x\n", - i, mci.addr.hi, mci.addr.lo); - mci.misc = rdmsr(MCAX_MISC0_MSR(i)); - printk(BIOS_WARNING, " MC%d_MISC = %08x_%08x\n", - i, mci.misc.hi, mci.misc.lo); - mci.ctl = rdmsr(MCAX_CTL_MSR(i)); - printk(BIOS_WARNING, " MC%d_CTL = %08x_%08x\n", - i, mci.ctl.hi, mci.ctl.lo); - mci.cmask = rdmsr(MCA_CTL_MASK_MSR(i)); - printk(BIOS_WARNING, " MC%d_CTL_MASK = %08x_%08x\n", - i, mci.cmask.hi, mci.cmask.lo); + printk(BIOS_WARNING, " MC%d_STATUS = %08x_%08x\n", + i, mci.sts.hi, mci.sts.lo); + mci.addr = rdmsr(MCAX_ADDR_MSR(i)); + printk(BIOS_WARNING, " MC%d_ADDR = %08x_%08x\n", + i, mci.addr.hi, mci.addr.lo); + mci.misc = rdmsr(MCAX_MISC0_MSR(i)); + printk(BIOS_WARNING, " MC%d_MISC = %08x_%08x\n", + i, mci.misc.hi, mci.misc.lo); + mci.ctl = rdmsr(MCAX_CTL_MSR(i)); + printk(BIOS_WARNING, " MC%d_CTL = %08x_%08x\n", + i, mci.ctl.hi, mci.ctl.lo); + mci.cmask = rdmsr(MCA_CTL_MASK_MSR(i)); + printk(BIOS_WARNING, " MC%d_CTL_MASK = %08x_%08x\n", + i, mci.cmask.hi, mci.cmask.lo); - mci.bank = i; - if (CONFIG(ACPI_BERT) - && mca_valid(mci.sts)) - build_bert_mca_error(&mci); - } + mci.bank = i; + if (CONFIG(ACPI_BERT) + && mca_valid(mci.sts)) + build_bert_mca_error(&mci); } } diff --git a/src/soc/amd/picasso/reset.c b/src/soc/amd/picasso/reset.c index 84226ea..8181d90 100644 --- a/src/soc/amd/picasso/reset.c +++ b/src/soc/amd/picasso/reset.c @@ -7,18 +7,6 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/reset.h> -void set_warm_reset_flag(void) -{ - uint8_t ncp = inb(NCP_ERR); - - outb(NCP_ERR, ncp | NCP_WARM_BOOT); -} - -int is_warm_reset(void) -{ - return !!(inb(NCP_ERR) & NCP_WARM_BOOT); -} - void do_cold_reset(void) { /* De-assert and then assert all PwrGood signals on CF9 reset. */ @@ -29,8 +17,6 @@ void do_warm_reset(void) { - set_warm_reset_flag(); - /* Assert reset signals only. */ outb(RST_CPU | SYS_RST, RST_CNT); } -- To view, visit https://review.coreboot.org/c/coreboot/+/55059 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e6df98ffd5d15ca204c9847a76c19c753726737 Gerrit-Change-Number: 55059 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: Kconfig: Fix BOOT_DEVICE_MEMORY_MAPPED
by Aaron Durbin (Code Review) 02 Jun '21

02 Jun '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Arthur Heymans. Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54302 ) Change subject: Kconfig: Fix BOOT_DEVICE_MEMORY_MAPPED ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/54302/comment/e520be1a_5e76446b PS1, Line 7: Fix BOOT_DEVICE_MEMORY_MAPPED : : Also non SPI x86 is memory mapped. > This does not explain what really is being fixed. The change as it exists is intentional. A follow up question would be: What do you consider 'non SPI'? What sort of protocols or boot mediums are being considered? As Furquan mentioned, the intention of the change isn't clear in what the change is trying to achieve. -- To view, visit https://review.coreboot.org/c/coreboot/+/54302 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c21e87d3375220a50645e0bf8b56fd23983f0c0 Gerrit-Change-Number: 54302 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 02 Jun 2021 15:27:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: Add proposal to allow enabling serial console with a flag
by Paul Menzel (Code Review) 02 Jun '21

02 Jun '21

Attention is currently required from: Stefan Reinauer. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54385 ) Change subject: Documentation: Add proposal to allow enabling serial console with a flag ...................................................................... Patch Set 2: Code-Review+1 (4 comments) Patchset: PS2: Thank you for writing this up. File Documentation/technotes/2021-05-selectable-serial-console.md: https://review.coreboot.org/c/coreboot/+/54385/comment/e09eb301_6888310a PS2, Line 69: have already been saying that decades ago.) I’d put the dot/period behind the ). https://review.coreboot.org/c/coreboot/+/54385/comment/3a10ba14_96a28b92 PS2, Line 121: disabled disables https://review.coreboot.org/c/coreboot/+/54385/comment/99a82b9e_19a4dff4 PS2, Line 125: turning it off entirely). Let’s do this from the beginning and use the log level numbers? I’d like that. -- To view, visit https://review.coreboot.org/c/coreboot/+/54385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1b0efc55880095f9d5d6d6e448f2c8677d57ff5 Gerrit-Change-Number: 54385 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Wed, 02 Jun 2021 15:24:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: FSP2.0 platforms: Use bootloader reserved memory for BERT
by Tim Wawrzynczak (Code Review) 02 Jun '21

02 Jun '21

Attention is currently required from: Tim Wawrzynczak, Andrey Petrov, Patrick Rudolph. Hello build bot (Jenkins), Andrey Petrov, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55142 to look at the new patch set (#2). Change subject: FSP2.0 platforms: Use bootloader reserved memory for BERT ...................................................................... FSP2.0 platforms: Use bootloader reserved memory for BERT Currently, a cbmem entry is used to store the BERT data, but when ACPI_BERT is defined, the FSP will save some memory in its reserved area above TOLUM to store the ACPI BERT. This patch moves the area BERT data is stored from cbmem to this reserved region. TEST=1) Trigger an event which will create a BERT 2) Verify BERT contents look valid 3) Ensure reserved region is covered by an e820 entry marked RESERVED 4) Ensure cbmem contents are still valid Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Ibd99fc4a89d559be32be69f8fc73c30782e6ae97 --- M src/drivers/intel/fsp2_0/Makefile.inc A src/drivers/intel/fsp2_0/bert.c M src/soc/intel/common/block/acpi/Kconfig M src/soc/intel/common/block/systemagent/memmap.c 4 files changed, 26 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/55142/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55142 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd99fc4a89d559be32be69f8fc73c30782e6ae97 Gerrit-Change-Number: 55142 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit June 2021