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Hello build bot (Jenkins), Patrick Georgi, Jonathan Zhang, Rocky Phagura, Angel Pons, Arthur Heymans, Patrick Rudolph, Lance Zhao, Marc Jones, Anjaneya "Reddy" Chagam, Johnny Lin, Christian Walter, Tim Wawrzynczak, David Hendricks, Morgan Jang, Tim Chu,
I'd like you to reexamine a change. Please visit
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Change subject: src/intel/xeon_sp: add hardware error support (HEST)
......................................................................
src/intel/xeon_sp: add hardware error support (HEST)
This patch adds the ACPI hardware error source table (HEST) support.
This involves a few different parts: (1) The ACPI HEST table which is filled
with the appropriate fields (2) Reserved memory which is used by runtime
SW to provide error information. OS will not accept a HEST table with
this memory set to 0.
The ASL code to enable APEI bit will be submitted in a separate patch.
Tested on DeltaLake mainboard with following options enabled
SOC_INTEL_XEON_RAS
After boot to Linux, the following will show in dmesg:
HEST: Table parsing has been initialized
Change-Id: If76b2af153616182cc053ca878f30fe056e9c8bd
Signed-off-by: Rocky Phagura <rphagura(a)fb.com>
---
M src/commonlib/include/commonlib/cbmem_id.h
M src/soc/intel/common/block/acpi/acpi/globalnvs.asl
M src/soc/intel/common/block/include/intelblocks/nvs.h
M src/soc/intel/xeon_sp/Kconfig
M src/soc/intel/xeon_sp/Makefile.inc
A src/soc/intel/xeon_sp/include/soc/hest.h
M src/soc/intel/xeon_sp/nb_acpi.c
A src/soc/intel/xeon_sp/ras/Kconfig
A src/soc/intel/xeon_sp/ras/Makefile.inc
A src/soc/intel/xeon_sp/ras/hest.c
10 files changed, 179 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/52090/21
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Change subject: src/intel/xeon_sp: add hardware error support (HEST)
......................................................................
Patch Set 20:
(1 comment)
File src/soc/intel/xeon_sp/uncore.c:
https://review.coreboot.org/c/coreboot/+/52090/comment/5bbac885_fae7c2c4
PS18, Line 149: * +--------------------------+ cbmem_top
: * | HEST ELOG | (CONFIG_ERROR_LOG_BUFFER_SIZE)
: * +--------------------------+
> > > > 1. Done...corrected the map so that HEST ELOG is above cbmem_top. […]
Done....changes made based on the above patch. CBMEM is now properly labeling the memory as "reserved" instead of "unknown" in E820. Changes in src/soc/intel/xeon_sp/uncore.c are no longer needed and have been removed. Thank you
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Change subject: src/intel/xeon_sp: add hardware error support (HEST)
......................................................................
Patch Set 20: Code-Review+1
(2 comments)
Patchset:
PS20:
Looks good
File src/soc/intel/xeon_sp/ras/hest.c:
https://review.coreboot.org/c/coreboot/+/52090/comment/4a2aafab_d1695725
PS20, Line 80: gnvs = acpi_get_gnvs();
nit: check for NULL
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#20).
Change subject: src/intel/xeon_sp: add hardware error support (HEST)
......................................................................
src/intel/xeon_sp: add hardware error support (HEST)
This patch adds the ACPI hardware error source table (HEST) support.
This involves a few different parts: (1) The ACPI HEST table which is filled
with the appropriate fields (2) Reserved memory which is used by runtime
SW to provide error information. OS will not accept a HEST table with
this memory set to 0.
The ASL code to enable APEI bit will be submitted in a separate patch.
Tested on DeltaLake mainboard with following options enabled
SOC_INTEL_XEON_RAS
After boot to Linux, the following will show in dmesg:
HEST: Table parsing has been initialized
Change-Id: If76b2af153616182cc053ca878f30fe056e9c8bd
Signed-off-by: Rocky Phagura <rphagura(a)fb.com>
---
M src/commonlib/include/commonlib/cbmem_id.h
M src/soc/intel/common/block/acpi/acpi/globalnvs.asl
M src/soc/intel/common/block/include/intelblocks/nvs.h
M src/soc/intel/xeon_sp/Kconfig
M src/soc/intel/xeon_sp/Makefile.inc
A src/soc/intel/xeon_sp/include/soc/hest.h
M src/soc/intel/xeon_sp/nb_acpi.c
A src/soc/intel/xeon_sp/ras/Kconfig
A src/soc/intel/xeon_sp/ras/Makefile.inc
A src/soc/intel/xeon_sp/ras/hest.c
10 files changed, 170 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/52090/20
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Change subject: soc/intel/elkhartlake: Update FSP-S storage related configs
......................................................................
Patch Set 13: Code-Review+2
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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/volteer:intel/common/block: Move mainboard api to tcss common block
......................................................................
mb/google/volteer:intel/common/block: Move mainboard api to tcss common block
As per the comments in CB:54090 mainboard api
mainboard_tcss_get_port_info() is simplified and moved
to tcss common block code.
Signed-off-by: Deepti Deshatty <deepti.deshatty(a)intel.com>
Change-Id: I7894363df4862f7cfe733d93e6160677fb8a9e31
---
M src/drivers/intel/pmc_mux/conn/chip.h
M src/drivers/intel/pmc_mux/conn/conn.c
M src/mainboard/google/volteer/mainboard.c
M src/soc/intel/common/block/include/intelblocks/tcss.h
M src/soc/intel/common/block/tcss/tcss.c
5 files changed, 59 insertions(+), 60 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/54733/7
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Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55128 )
Change subject: src/mainboard: Add Star Labs labtop series
......................................................................
Patch Set 6:
(1 comment)
File src/mainboard/starlabs/labtop/variants/cml/romstage.c:
https://review.coreboot.org/c/coreboot/+/55128/comment/f40f1ba5_638a47de
PS6, Line 114: const uint8_t ht = get_uint_option("hyper_threading", memupd->FspmConfig.HyperThreading);
> line over 96 characters
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Change subject: src/mainboard: Add Star Labs labtop series
......................................................................
Patch Set 6:
(1 comment)
File src/mainboard/starlabs/labtop/variants/cml/romstage.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120538):
https://review.coreboot.org/c/coreboot/+/55128/comment/7861fcc9_3980225a
PS6, Line 114: const uint8_t ht = get_uint_option("hyper_threading", memupd->FspmConfig.HyperThreading);
line over 96 characters
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/55128
to look at the new patch set (#6).
Change subject: src/mainboard: Add Star Labs labtop series
......................................................................
src/mainboard: Add Star Labs labtop series
Add support for LabTop Mk III (kblr) and LabTop Mk IV (cml)
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: Iffa6061b0e600880b0c93746f35b1731e4841e31
---
M Documentation/distributions.md
M Documentation/mainboard/index.md
A src/mainboard/starlabs/Kconfig
A src/mainboard/starlabs/Kconfig.name
A src/mainboard/starlabs/labtop/Kconfig
A src/mainboard/starlabs/labtop/Kconfig.name
A src/mainboard/starlabs/labtop/Makefile.inc
A src/mainboard/starlabs/labtop/acpi/ec.asl
A src/mainboard/starlabs/labtop/acpi/mainboard.asl
A src/mainboard/starlabs/labtop/acpi/sleep.asl
A src/mainboard/starlabs/labtop/acpi/superio.asl
A src/mainboard/starlabs/labtop/board_info.txt
A src/mainboard/starlabs/labtop/bootblock.c
A src/mainboard/starlabs/labtop/cmos.default
A src/mainboard/starlabs/labtop/cmos.layout
A src/mainboard/starlabs/labtop/dsdt.asl
A src/mainboard/starlabs/labtop/hda_verb.c
A src/mainboard/starlabs/labtop/mainboard.c
A src/mainboard/starlabs/labtop/ramstage.c
A src/mainboard/starlabs/labtop/spd/Makefile.inc
A src/mainboard/starlabs/labtop/spd/empty_ddr4.spd.hex
A src/mainboard/starlabs/labtop/spd/micron-MT40A1G16KD-062E-E.spd.hex
A src/mainboard/starlabs/labtop/spd/samsung-K4A8G165WB-BCRC.spd.hex
A src/mainboard/starlabs/labtop/spd/spd.h
A src/mainboard/starlabs/labtop/spd/spd_util.c
A src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/memory.h
A src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/romstage.h
A src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/variants.h
A src/mainboard/starlabs/labtop/variants/cml/Makefile.inc
A src/mainboard/starlabs/labtop/variants/cml/board.fmd
A src/mainboard/starlabs/labtop/variants/cml/data.vbt
A src/mainboard/starlabs/labtop/variants/cml/devicetree.cb
A src/mainboard/starlabs/labtop/variants/cml/gma-mainboard.ads
A src/mainboard/starlabs/labtop/variants/cml/include/variant/gpio.h
A src/mainboard/starlabs/labtop/variants/cml/include/variant/hda_verb.h
A src/mainboard/starlabs/labtop/variants/cml/romstage.c
A src/mainboard/starlabs/labtop/variants/kbl/Makefile.inc
A src/mainboard/starlabs/labtop/variants/kbl/board.fmd
A src/mainboard/starlabs/labtop/variants/kbl/data.vbt
A src/mainboard/starlabs/labtop/variants/kbl/devicetree.cb
A src/mainboard/starlabs/labtop/variants/kbl/gma-mainboard.ads
A src/mainboard/starlabs/labtop/variants/kbl/include/variant/gpio.h
A src/mainboard/starlabs/labtop/variants/kbl/include/variant/hda_verb.h
A src/mainboard/starlabs/labtop/variants/kbl/romstage.c
44 files changed, 1,990 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/55128/6
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Iffa6061b0e600880b0c93746f35b1731e4841e31
Gerrit-Change-Number: 55128
Gerrit-PatchSet: 6
Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: newpatchset