coreboot-gerrit June 2021

coreboot-gerrit@coreboot.org

1 participants
7127 discussions

Change in coreboot[master]: amdfwtool: Add a function to extract firmwares
by Bao Zheng (Code Review) 02 Jun '21

02 Jun '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson, Zheng Bao, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson, Paul Menzel, Zheng Bao, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54901 to look at the new patch set (#10). Change subject: amdfwtool: Add a function to extract firmwares ...................................................................... amdfwtool: Add a function to extract firmwares This is one of the steps to replace the firmwares of an image. The brief steps would be: o cbfstool to extract and/or remove files from the image o amdfwtool to regenerate the amdfw.rom image - extract all the firmwares in the image (* this change) - replace the fireware - regenerate the amdfw.rom o cbfstool to insert the new one Change-Id: I74a6c7ff56cc11530695d1068763ecdd86282a17 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/Makefile M util/amdfwtool/Makefile.inc M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h A util/amdfwtool/extract.c 5 files changed, 317 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/54901/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/54901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74a6c7ff56cc11530695d1068763ecdd86282a17 Gerrit-Change-Number: 54901 Gerrit-PatchSet: 10 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/emulation/qemu-q35: Add support for SMM_TSEG with parallel MP init
by Arthur Heymans (Code Review) 02 Jun '21

02 Jun '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48262 ) Change subject: mb/emulation/qemu-q35: Add support for SMM_TSEG with parallel MP init ...................................................................... mb/emulation/qemu-q35: Add support for SMM_TSEG with parallel MP init Change-Id: I612cebcd2ddef809434eb9bfae9d8681cda112ef Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/qemu-x86/Kconfig M src/mainboard/emulation/qemu-i440fx/northbridge.c M src/mainboard/emulation/qemu-q35/Makefile.inc A src/mainboard/emulation/qemu-q35/cpu.c M src/mainboard/emulation/qemu-q35/memmap.c 5 files changed, 92 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/48262/1 diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index 641cea8..0f59b9c 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -36,9 +36,10 @@ depends on !PARALLEL_MP select SMM_ASEG -#config CPU_QEMU_X86_TSEG_SMM -# bool "SMM in TSEG" -# select SMM_TSEG +config CPU_QEMU_X86_TSEG_SMM + bool "SMM in TSEG" + select SMM_TSEG + depends on PARALLEL_MP endchoice diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index f49d47da..7ee38d3 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -249,9 +249,15 @@ .get_cpu_count = fw_cfg_max_cpus, }; +extern const struct mp_ops mp_ops_with_smm; + void mp_init_cpus(struct bus *cpu_bus) { - if (mp_init_with_smm(cpu_bus, &mp_ops_no_smm)) + const struct mp_ops *ops = &mp_ops_no_smm; + if (CONFIG(SMM_TSEG)) + ops = &mp_ops_with_smm; + + if (mp_init_with_smm(cpu_bus, ops)) printk(BIOS_ERR, "MP initialization failure.\n"); } diff --git a/src/mainboard/emulation/qemu-q35/Makefile.inc b/src/mainboard/emulation/qemu-q35/Makefile.inc index 4bd91f0..f717405 100644 --- a/src/mainboard/emulation/qemu-q35/Makefile.inc +++ b/src/mainboard/emulation/qemu-q35/Makefile.inc @@ -13,6 +13,7 @@ ramstage-y += ../qemu-i440fx/memmap.c ramstage-y += ../qemu-i440fx/northbridge.c ramstage-y += memmap.c +ramstage-y += cpu.c verstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-$(CONFIG_CHROMEOS) += ../qemu-i440fx/fw_cfg.c diff --git a/src/mainboard/emulation/qemu-q35/cpu.c b/src/mainboard/emulation/qemu-q35/cpu.c new file mode 100644 index 0000000..c0f4ee5 --- /dev/null +++ b/src/mainboard/emulation/qemu-q35/cpu.c @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <cpu/x86/mp.h> +#include <stdint.h> +#include <cpu/intel/smm_reloc.h> +#include <cpu/amd/amd64_save_state.h> +#include <mainboard/emulation/qemu-i440fx/fw_cfg.h> + +static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, + size_t *smm_save_state_size) +{ + printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); + + smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); + +// *smm_save_state_size = sizeof(amd64_smm_state_save_area_t); + *smm_save_state_size = 0x400; + printk(BIOS_DEBUG, "Save state size: 0x%lx bytes\n", *smm_save_state_size); +} + +static void per_cpu_smm_trigger(void) +{ + /* Relocate SMM space. */ + smm_initiate_relocation(); +} + +/* The relocation work is actually performed in SMM context, but the code + * resides in the ramstage module. This occurs by trampolining from the default + * SMRAM entry point to here. */ +static void relocation_handler(int cpu, uintptr_t curr_smbase, + uintptr_t staggered_smbase) +{ + /* The em64t101 save state is sufficiently compatible with older + save states with regards of smbase, smm_revision. */ + amd64_smm_state_save_area_t *save_state; + u32 smbase = staggered_smbase; + + save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - sizeof(*save_state)); + save_state->smbase = smbase; + + printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu); + printk(BIOS_SPEW, "SMM revision: 0x%08x\n", save_state->smm_revision); + printk(BIOS_DEBUG, "New SMBASE=0x%08x\n", smbase); +} + +static void post_mp_init(void) +{ + /* Now that all APs have been relocated as well as the BSP let SMIs + * start flowing. */ + global_smi_enable(); + + /* Lock down the SMRAM space. */ + smm_lock(); +} + +const struct mp_ops mp_ops_with_smm = { + .get_cpu_count = fw_cfg_max_cpus, + .get_smm_info = get_smm_info, + .pre_mp_smm_init = smm_southbridge_clear_state, + .per_cpu_smm_trigger = per_cpu_smm_trigger, + .relocation_handler = relocation_handler, + .post_mp_init = post_mp_init, +}; diff --git a/src/mainboard/emulation/qemu-q35/memmap.c b/src/mainboard/emulation/qemu-q35/memmap.c index c288680..04cf285 100644 --- a/src/mainboard/emulation/qemu-q35/memmap.c +++ b/src/mainboard/emulation/qemu-q35/memmap.c @@ -2,14 +2,17 @@ #define __SIMPLE_DEVICE__ +#include <console/console.h> #include <cpu/x86/smm.h> #include <device/pci_ops.h> #include <mainboard/emulation/qemu-i440fx/memory.h> #include <mainboard/emulation/qemu-i440fx/fw_cfg.h> +#include <cpu/intel/smm_reloc.h> #define EXT_TSEG_MBYTES 0x50 #define SMRAMC 0x9d +#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) #define G_SMRAME (1 << 3) #define D_LCK (1 << 4) #define D_CLS (1 << 5) @@ -40,3 +43,16 @@ *start = qemu_get_memory_size() * KiB - *size; printk(BIOS_SPEW, "SMM_BASE: 0x%08lx, SMM_SIZE: %ld MiB\n", *start, *size / MiB); } + +void smm_lock(void) +{ + /* LOCK the SMM memory window and enable normal SMM. + * After running this function, only a full reset can + * make the SMM registers writable again. + */ + printk(BIOS_DEBUG, "Locking SMM.\n"); + + pci_or_config8(PCI_DEV(0, 0, 0), ESMRAMC, T_EN); + pci_write_config8(PCI_DEV(0, 0, 0), SMRAMC, D_LCK | G_SMRAME | C_BASE_SEG); +} + -- To view, visit https://review.coreboot.org/c/coreboot/+/48262 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I612cebcd2ddef809434eb9bfae9d8681cda112ef Gerrit-Change-Number: 48262 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

5 25

Change in coreboot[master]: mb/emulation/q35: Fix running with qemu-i386 with SMM_TSEG
by build bot (Jenkins) (Code Review) 02 Jun '21

02 Jun '21

Attention is currently required from: Kyösti Mälkki. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55138 ) Change subject: mb/emulation/q35: Fix running with qemu-i386 with SMM_TSEG ...................................................................... Patch Set 1: (2 comments) File src/mainboard/emulation/qemu-q35/cpu.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120519): https://review.coreboot.org/c/coreboot/+/55138/comment/053eeb34_66d16612 PS1, Line 41: save_state_i386 = (void *)(curr_smbase + SMM_DEFAULT_SIZE - sizeof(*save_state_i386)); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120519): https://review.coreboot.org/c/coreboot/+/55138/comment/af40357e_b56ae80d PS1, Line 50: printk(BIOS_DEBUG, "Unknown SMM revision 0x%08x, not relocating SMM\n", smm_revision); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/55138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6994c8d6e10fd06655129dbd801f1f9d5fd639f Gerrit-Change-Number: 55138 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Wed, 02 Jun 2021 09:49:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/emulation/q35: Fix running with qemu-i386 with SMM_TSEG
by Arthur Heymans (Code Review) 02 Jun '21

02 Jun '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55138 ) Change subject: mb/emulation/q35: Fix running with qemu-i386 with SMM_TSEG ...................................................................... mb/emulation/q35: Fix running with qemu-i386 with SMM_TSEG Qemu now uses the legacy x86 SMM save state for i386, where it previously always used the amd64 save state. The smbase offsets are incompatible between those save states. Change-Id: Ic6994c8d6e10fd06655129dbd801f1f9d5fd639f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/emulation/qemu-q35/cpu.c 1 file changed, 22 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/55138/1 diff --git a/src/mainboard/emulation/qemu-q35/cpu.c b/src/mainboard/emulation/qemu-q35/cpu.c index fb31fc5..d95393b 100644 --- a/src/mainboard/emulation/qemu-q35/cpu.c +++ b/src/mainboard/emulation/qemu-q35/cpu.c @@ -1,10 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include "cpu/x86/smm.h" #include <console/console.h> #include <cpu/x86/mp.h> #include <stdint.h> #include <cpu/intel/smm_reloc.h> #include <cpu/amd/amd64_save_state.h> +#include <cpu/x86/legacy_save_state.h> #include <mainboard/emulation/qemu-i440fx/fw_cfg.h> static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, @@ -27,16 +29,30 @@ static void relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase) { - /* The em64t101 save state is sufficiently compatible with older - save states with regards of smbase, smm_revision. */ - amd64_smm_state_save_area_t *save_state; + amd64_smm_state_save_area_t *save_state_amd64; + legacy_smm_state_save_area_t *save_state_i386; + + uint32_t smm_revision = (uint32_t)*(uint32_t *)(curr_smbase + SMM_DEFAULT_SIZE + - SMM_REVISION_OFFSET_FROM_TOP); u32 smbase = staggered_smbase; - save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - sizeof(*save_state)); - save_state->smbase = smbase; + switch (smm_revision) { + case 0x00020000: + save_state_i386 = (void *)(curr_smbase + SMM_DEFAULT_SIZE - sizeof(*save_state_i386)); + save_state_i386->smbase = smbase; + break; + case 0x00020064: + save_state_amd64 = + (void *)(curr_smbase + SMM_DEFAULT_SIZE - sizeof(*save_state_amd64)); + save_state_amd64->smbase = smbase; + break; + default: + printk(BIOS_DEBUG, "Unknown SMM revision 0x%08x, not relocating SMM\n", smm_revision); + return; + }; printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu); - printk(BIOS_DEBUG, "SMM revision: 0x%08x\n", save_state->smm_revision); + printk(BIOS_DEBUG, "SMM revision: 0x%08x\n", smm_revision); printk(BIOS_DEBUG, "New SMBASE=0x%08x\n", smbase); } -- To view, visit https://review.coreboot.org/c/coreboot/+/55138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6994c8d6e10fd06655129dbd801f1f9d5fd639f Gerrit-Change-Number: 55138 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/intel/common/acpi: add ACPI S0ix _DSM for Intel Power Engine Plug-in
by Paul Menzel (Code Review) 02 Jun '21

02 Jun '21

Attention is currently required from: Cliff Huang, Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55127 ) Change subject: soc/intel/common/acpi: add ACPI S0ix _DSM for Intel Power Engine Plug-in ...................................................................... Patch Set 4: Code-Review+1 (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/55127/comment/2667c8ff_5f17b7c5 PS4, Line 9: ( UUID: Please remove the space after (. https://review.coreboot.org/c/coreboot/+/55127/comment/a72de2a0_10f24a06 PS4, Line 22: need to implemented needs to be implemented File src/soc/intel/common/block/acpi/Kconfig: https://review.coreboot.org/c/coreboot/+/55127/comment/1e5699fb_7a0ef0f4 PS4, Line 34: s0ix S0ix https://review.coreboot.org/c/coreboot/+/55127/comment/4e4b44b6_653195e0 PS4, Line 34: Generate s0ix entries for Intel power engine plug-in Maybe add: > Linux exposes this under `/sys/kernel/debug/pmc_core/substate_requirement_registers`. File src/soc/intel/common/block/acpi/acpi/pep.asl: https://review.coreboot.org/c/coreboot/+/55127/comment/92c99a78_58f69f11 PS4, Line 16: #define PEPD_PMC_PWRM_LPM_REQ_BITS_DATA_LEN 1536 I’d only use the first macro, and calculate the bit value from it. -- To view, visit https://review.coreboot.org/c/coreboot/+/55127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I991662cbebf63bd71139ed37ff2588ba73f30398 Gerrit-Change-Number: 55127 Gerrit-PatchSet: 4 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sukumar Ghorai <sukumar.ghorai(a)gmail.com> Gerrit-CC: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 02 Jun 2021 09:28:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/dedede/var/kracko:Add P-sensor support
by Paul Menzel (Code Review) 02 Jun '21

02 Jun '21

Attention is currently required from: Tony Huang, Wisley Chen, Karthik Ramasubramanian. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55133 ) Change subject: mb/google/dedede/var/kracko:Add P-sensor support ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/55133/comment/79715b4a_866a39c7 PS1, Line 7: mb/google/dedede/var/kracko:Add P-sensor support Please add a space after the colon. https://review.coreboot.org/c/coreboot/+/55133/comment/6355dbc4_e2b8dc04 PS1, Line 10: would be fine tune later will be fine tuned later. -- To view, visit https://review.coreboot.org/c/coreboot/+/55133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c8feedd6efc1a471304322a17480c836e22349e Gerrit-Change-Number: 55133 Gerrit-PatchSet: 1 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 02 Jun 2021 09:20:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel: Allow enable/disable ME via CMOS
by Sean Rhodes (Code Review) 02 Jun '21

02 Jun '21

Attention is currently required from: Andy Pont, Tim Wawrzynczak, Paul Menzel, Arthur Heymans, Patrick Rudolph. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52800 ) Change subject: soc/intel: Allow enable/disable ME via CMOS ...................................................................... Patch Set 20: (1 comment) File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/52800/comment/37b2855c_5e59af30 PS20, Line 847: print_me_fw_version > > Would renaming the method be an acceptable solution? Otherwise, we're going to end up with 2 almos […] The heci_reset will cause problems if the ME is disabled, so even if we move it, we'd have to change the print_fw to stop that running. PCI device disappears and bars stop working. -- To view, visit https://review.coreboot.org/c/coreboot/+/52800 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I374db3b7c0ded71cdc18f27970252fec7220cc20 Gerrit-Change-Number: 52800 Gerrit-PatchSet: 20 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 02 Jun 2021 09:16:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <admin(a)starlabs.systems> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: cezanne/psp_verstage: add reset/timer svc
by Kangheui Won (Code Review) 02 Jun '21

02 Jun '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Kangheui Won has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55137 ) Change subject: cezanne/psp_verstage: add reset/timer svc ...................................................................... cezanne/psp_verstage: add reset/timer svc The new cezanne PSP release added support for these svcs. So add those functionality back to cezanne psp_verstage. BUG=b:187906425 Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: Id542f5ed0762f582ea966466d67ed938ecb9c1f0 --- M src/soc/amd/cezanne/psp_verstage/chipset.c M src/soc/amd/cezanne/psp_verstage/svc.c M src/soc/amd/common/psp_verstage/Makefile.inc M src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h 4 files changed, 55 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/55137/1 diff --git a/src/soc/amd/cezanne/psp_verstage/chipset.c b/src/soc/amd/cezanne/psp_verstage/chipset.c index c0593bf..7ad2149 100644 --- a/src/soc/amd/cezanne/psp_verstage/chipset.c +++ b/src/soc/amd/cezanne/psp_verstage/chipset.c @@ -8,8 +8,6 @@ #include <bl_uapp/bl_syscall_public.h> #include <console/console.h> #include <psp_verstage.h> -#include <reset.h> -#include <timer.h> uint32_t update_psp_bios_dir(uint32_t *psp_dir_offset, uint32_t *bios_dir_offset) { @@ -35,17 +33,3 @@ { return 0; } - -static uint64_t tmp_timer_value = 0; -void timer_monotonic_get(struct mono_time *mt) -{ - mt->microseconds = tmp_timer_value / 1000; - tmp_timer_value++; -} - -void do_board_reset(void) -{ - printk(BIOS_ERR, "Reset not implemented yet.\n"); - while (1) - ; -} diff --git a/src/soc/amd/cezanne/psp_verstage/svc.c b/src/soc/amd/cezanne/psp_verstage/svc.c index 70cb369..bd4bec5 100644 --- a/src/soc/amd/cezanne/psp_verstage/svc.c +++ b/src/soc/amd/cezanne/psp_verstage/svc.c @@ -35,9 +35,8 @@ void svc_delay_in_usec(uint32_t delay) { - uint32_t i; - for (i = 0; i < delay * 1000; i++) - asm volatile ("nop"); + uint32_t unused = 0; + SVC_CALL1(SVC_DELAY_IN_MICRO_SECONDS, delay, unused); } uint32_t svc_get_spi_rom_info(struct spirom_info *spi_rom_info) @@ -97,3 +96,19 @@ SVC_CALL2(SVC_COPY_DATA_FROM_UAPP, (uint32_t)address, size, retval); return retval; } + +uint32_t svc_read_timer_val(enum psp_timer_type type, uint64_t *counter_value) +{ + unsigned int retval = 0; + assert(type < PSP_TIMER_TYPE_MAX); + SVC_CALL2(SVC_READ_TIMER_VAL, type, counter_value, retval); + return retval; +} + +uint32_t svc_reset_system(enum reset_type reset_type) +{ + unsigned int retval = 0; + assert(reset_type < RESET_TYPE_MAX); + SVC_CALL1(SVC_RESET_SYSTEM, reset_type, retval); + return retval; +} diff --git a/src/soc/amd/common/psp_verstage/Makefile.inc b/src/soc/amd/common/psp_verstage/Makefile.inc index 7272de4..678bc45 100644 --- a/src/soc/amd/common/psp_verstage/Makefile.inc +++ b/src/soc/amd/common/psp_verstage/Makefile.inc @@ -14,10 +14,10 @@ verstage-y += printk.c verstage-y += psp_verstage.c verstage-y += psp.c -ifneq ($(CONFIG_SOC_AMD_CEZANNE),y) -# cezanne PSP does not support these functions yet (b/187906425) verstage-y += reset.c verstage-y += timer.c +ifneq ($(CONFIG_SOC_AMD_CEZANNE),y) +# cezanne PSP does not support these functions yet (b/187906425) verstage-y += vboot_crypto.c endif diff --git a/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h b/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h index 25a15e6..75458c3 100644 --- a/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h +++ b/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h @@ -37,6 +37,7 @@ #define SVC_DEBUG_PRINT 0x06 #define SVC_DEBUG_PRINT_EX 0x1A #define SVC_GET_BOOT_MODE 0x1C +#define SVC_DELAY_IN_MICRO_SECONDS 0x2F #define SVC_GET_SPI_INFO 0x60 #define SVC_MAP_SPIROM_DEVICE 0x61 #define SVC_UNMAP_SPIROM_DEVICE 0x62 @@ -44,6 +45,8 @@ #define SVC_UNMAP_FCH_IO_DEVICE 0x64 #define SVC_UPDATE_PSP_BIOS_DIR 0x65 #define SVC_COPY_DATA_FROM_UAPP 0x66 +#define SVC_RESET_SYSTEM 0x67 +#define SVC_READ_TIMER_VAL 0x68 enum psp_boot_mode { PSP_BOOT_MODE_S0 = 0x0, @@ -54,6 +57,13 @@ PSP_BOOT_MODE_S5_WARM = 0x5, }; +enum reset_type +{ + RESET_TYPE_COLD = 0, + RESET_TYPE_WARM = 1, + RESET_TYPE_MAX = 2, +}; + enum fch_io_device { FCH_IO_DEVICE_SPI, FCH_IO_DEVICE_I2C, @@ -81,6 +91,12 @@ uint32_t SpiBiosSize; }; +enum psp_timer_type { + PSP_TIMER_TYPE_CHRONO = 0, + PSP_TIMER_TYPE_SECURE_RTC = 1, + PSP_TIMER_TYPE_MAX = 2, +}; + /* * Exit to the main Boot Loader. This does not return back to user application. * @@ -206,6 +222,25 @@ uint32_t svc_save_uapp_data(void *address, uint32_t size); /* + * Read timer raw (currently CHRONO and RTC) value + * + * Parameters: + * type - [in] Type of timer UAPP would like to read from + * (currently CHRONO and RTC) + * counter_value - [out] return the raw counter value read from + * RTC or CHRONO_LO/HI counter register + -----------------------------------------------------------------------------*/ +uint32_t svc_read_timer_val(enum psp_timer_type type, uint64_t *counter_value); + +/* + * Reset the system + * + * Parameters: + * reset_type - Cold or Warm reset + */ +uint32_t svc_reset_system(enum reset_type reset_type); + +/* * Write postcode to Port-80 * * Parameters: -- To view, visit https://review.coreboot.org/c/coreboot/+/55137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id542f5ed0762f582ea966466d67ed938ecb9c1f0 Gerrit-Change-Number: 55137 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/google/guybrush: initialize i2c in psp_verstage
by Kangheui Won (Code Review) 02 Jun '21

02 Jun '21

Kangheui Won has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55136 ) Change subject: mb/google/guybrush: initialize i2c in psp_verstage ...................................................................... mb/google/guybrush: initialize i2c in psp_verstage GSC is connected with AP via i2c bus so we need to enable i2c in psp_verstage. Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: I5f7b73be67a692ea7de31ae53bd111d0e4b6998c --- M src/mainboard/google/guybrush/verstage.c 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/55136/1 diff --git a/src/mainboard/google/guybrush/verstage.c b/src/mainboard/google/guybrush/verstage.c index e7543c0..462b43c 100644 --- a/src/mainboard/google/guybrush/verstage.c +++ b/src/mainboard/google/guybrush/verstage.c @@ -1,8 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <amdblocks/gpio_banks.h> +#include <amdblocks/i2c.h> #include <baseboard/variants.h> +#include <console/console.h> #include <security/vboot/vboot_common.h> +#include <soc/southbridge.h> static void setup_gpio(void) { @@ -22,4 +25,10 @@ void verstage_mainboard_init(void) { + if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) { + enable_aoac_devices(); + printk(BIOS_DEBUG, "Setting up i2c\n"); + i2c_soc_early_init(); + printk(BIOS_DEBUG, "i2c setup\n"); + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/55136 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f7b73be67a692ea7de31ae53bd111d0e4b6998c Gerrit-Change-Number: 55136 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/intel: Allow enable/disable ME via CMOS
by Arthur Heymans (Code Review) 02 Jun '21

02 Jun '21

Attention is currently required from: Sean Rhodes, Andy Pont, Tim Wawrzynczak, Paul Menzel, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52800 ) Change subject: soc/intel: Allow enable/disable ME via CMOS ...................................................................... Patch Set 20: (2 comments) File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/52800/comment/c1f00ddd_0d43d2ae PS20, Line 67: /* : * Initialize the device with provided temporary BAR. If BAR is 0 use a : * default. This is intended for pre-mem usage only where BARs haven't been : * assigned yet and devices are not enabled. : */ This comment is not in the right place anymore. https://review.coreboot.org/c/coreboot/+/52800/comment/88df9997_6cc6c5a8 PS20, Line 847: print_me_fw_version > Would renaming the method be an acceptable solution? Otherwise, we're going to end up with 2 almost identical functions. Why not enable/disable it in the cse_ops 'enable' function instead of highjacking a different function to do this? Also what happens to the PCI device after you send those messages? Does it dissapear? Are the BARs still working? If the PCI device cannot be enumerated after this message, you might want to add a different hook that is run earlier: before BS_DEV_ENUMERATE is run. -- To view, visit https://review.coreboot.org/c/coreboot/+/52800 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I374db3b7c0ded71cdc18f27970252fec7220cc20 Gerrit-Change-Number: 52800 Gerrit-PatchSet: 20 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 02 Jun 2021 08:11:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <admin(a)starlabs.systems> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2021